<s>
Grounded-gate	O
NMOS	B-Architecture
,	O
commonly	O
known	O
as	O
ggNMOS	B-Algorithm
,	O
is	O
an	O
electrostatic	O
discharge	O
(	O
ESD	O
)	O
protection	O
device	O
used	O
within	O
CMOS	B-Device
integrated	O
circuits	O
(	O
ICs	O
)	O
.	O
</s>
<s>
Such	O
devices	O
are	O
used	O
to	O
protect	O
the	O
inputs	O
and	O
outputs	O
of	O
an	O
IC	O
,	O
which	O
can	O
be	O
accessed	O
off-chip	O
(	O
wire-bonded	B-Algorithm
to	O
the	O
pins	O
of	O
a	O
package	B-Algorithm
or	O
directly	O
to	O
a	O
printed	O
circuit	O
board	O
)	O
and	O
are	O
therefore	O
subject	O
to	O
ESD	O
when	O
touched	O
.	O
</s>
<s>
An	O
ESD	O
event	O
can	O
deliver	O
a	O
large	O
amount	O
of	O
energy	O
to	O
the	O
chip	O
,	O
potentially	O
destroying	O
input/output	O
circuitry	O
;	O
a	O
ggNMOS	B-Algorithm
device	O
or	O
other	O
ESD	O
protective	O
devices	O
provide	O
a	O
safe	O
path	O
for	O
current	O
to	O
flow	O
,	O
instead	O
of	O
through	O
more	O
sensitive	O
circuitry	O
.	O
</s>
<s>
As	O
the	O
name	O
implies	O
,	O
a	O
ggNMOS	B-Algorithm
device	O
consists	O
of	O
a	O
relatively	O
wide	O
NMOS	B-Architecture
device	O
in	O
which	O
the	O
gate	O
,	O
source	O
,	O
and	O
body	O
are	O
tied	O
together	O
to	O
ground	O
.	O
</s>
<s>
The	O
drain	O
of	O
the	O
ggNMOS	B-Algorithm
is	O
connected	O
to	O
the	O
I/O	O
pad	O
under	O
protection	O
.	O
</s>
<s>
A	O
parasitic	O
NPN	O
bipolar	O
junction	O
transistor	O
(	O
BJT	O
)	O
is	O
thus	O
formed	O
with	O
the	O
drain	O
(	O
n-type	O
)	O
acting	O
as	O
the	O
collector	O
,	O
the	O
base/source	O
combination	O
(	O
n-type	O
)	O
as	O
the	O
emitter	O
,	O
and	O
the	O
substrate	B-Architecture
(	O
p-type	O
)	O
as	O
the	O
base	O
.	O
</s>
<s>
As	O
is	O
explained	O
below	O
,	O
a	O
key	O
element	O
to	O
the	O
operation	O
of	O
the	O
ggNMOS	B-Algorithm
is	O
the	O
parasitic	O
resistance	O
present	O
between	O
the	O
emitter	O
and	O
base	O
terminals	O
of	O
the	O
parasitic	O
npn	O
BJT	O
.	O
</s>
<s>
This	O
resistance	O
is	O
a	O
result	O
of	O
the	O
finite	O
conductivity	O
of	O
the	O
p-type	O
doped	O
substrate	B-Architecture
.	O
</s>
