<s>
GIO	B-Architecture
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
standard	O
developed	O
by	O
SGI	O
and	O
used	O
in	O
a	O
variety	O
of	O
their	O
products	O
in	O
the	O
1990s	O
as	O
their	O
primary	O
expansion	O
system	O
.	O
</s>
<s>
GIO	B-Architecture
was	O
similar	O
in	O
concept	O
to	O
competing	O
standards	O
such	O
as	O
NuBus	B-Device
or	O
(	O
later	O
)	O
PCI	B-Protocol
,	O
but	O
saw	O
little	O
use	O
outside	O
SGI	O
and	O
severely	O
limited	O
the	O
devices	O
available	O
on	O
their	O
platform	O
as	O
a	O
result	O
.	O
</s>
<s>
Most	O
devices	O
using	O
GIO	B-Architecture
were	O
SGI	O
's	O
own	O
graphics	O
cards	O
,	O
although	O
a	O
number	O
of	O
cards	O
supporting	O
high-speed	O
data	O
access	O
such	O
as	O
Fibre	B-Architecture
Channel	I-Architecture
and	O
FDDI	B-Protocol
were	O
available	O
from	O
third	O
parties	O
.	O
</s>
<s>
Later	O
SGI	O
machines	O
use	O
the	O
XIO	B-Architecture
bus	O
,	O
which	O
is	O
laid	O
out	O
as	O
a	O
computer	B-Architecture
network	I-Architecture
as	O
opposed	O
to	O
a	O
bus	O
.	O
</s>
<s>
Like	O
most	O
busses	O
of	O
the	O
era	O
,	O
GIO	B-Architecture
was	O
a	O
32-bit	O
address	O
and	O
data	O
multiplexed	B-Architecture
bus	O
that	O
was	O
normally	O
clocked	O
at	O
25	O
or	O
33MHz	O
.	O
</s>
<s>
GIO	B-Architecture
also	O
included	O
a	O
"	O
real	O
time	O
"	O
interrupt	O
allowing	O
devices	O
to	O
interrupt	O
these	O
long	O
transfers	O
if	O
needed	O
.	O
</s>
<s>
Bus	O
arbitration	O
was	O
controlled	O
by	O
the	O
Processor	O
Interface	O
Controller	O
(	O
PIC	O
)	O
in	O
the	O
original	O
R3000-based	O
SGI	B-Device
Indigo	I-Device
systems	O
.	O
</s>
<s>
Physically	O
,	O
GIO	B-Architecture
used	O
a	O
96-pin	O
connector	O
and	O
fairly	O
small	O
cards	O
6.44inches	O
(	O
16.3576cm	O
)	O
long	O
by	O
3.375inches	O
(	O
8.5725cm	O
)	O
wide	O
.	O
</s>
<s>
In	O
the	O
Indigo	O
series	O
,	O
the	O
cards	O
were	O
aligned	O
vertically	O
above	O
each	O
other	O
within	O
the	O
case	O
,	O
as	O
opposed	O
to	O
the	O
more	O
common	O
arrangement	O
where	O
the	O
cards	O
lie	O
at	O
right	O
angles	O
to	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Since	O
the	O
cards	O
were	O
"	O
above	O
"	O
each	O
other	O
in-line	O
,	O
it	O
was	O
possible	O
to	O
build	O
a	O
card	O
that	O
connected	O
to	O
both	O
connectors	O
on	O
the	O
computer	O
's	O
motherboard	B-Device
,	O
thereby	O
offering	O
more	O
room	O
.	O
</s>
<s>
GIO	B-Architecture
was	O
later	O
expanded	O
to	O
a	O
64-bit	O
form	O
,	O
GIO64	O
,	O
retroactively	O
renaming	O
the	O
earlier	O
version	O
GIO32	O
.	O
</s>
<s>
The	O
page	O
sizes	O
were	O
also	O
adjusted	O
to	O
allow	O
for	O
the	O
changing	O
CPU	B-Device
's	O
,	O
starting	O
at	O
4	O
kbyte	O
for	O
R3000	O
based	O
machines	O
,	O
and	O
up	O
to	O
16	O
Mbyte	O
for	O
R4400	O
based	O
ones	O
.	O
</s>
<s>
Physically	O
the	O
GIO64	O
bus	O
used	O
much	O
larger	O
cards	O
that	O
were	O
generally	O
similar	O
in	O
size	O
and	O
layout	O
to	O
EISA	B-Device
cards	O
,	O
a	O
deliberate	O
choice	O
that	O
made	O
development	O
somewhat	O
easier	O
as	O
well	O
as	O
allowing	O
SGI	O
to	O
place	O
EISA	B-Device
slots	O
in	O
the	O
same	O
machines	O
.	O
</s>
<s>
Specifically	O
the	O
external	O
connector	O
(	O
the	O
metal	O
flange	O
)	O
was	O
identical	O
to	O
EISA	B-Device
,	O
but	O
the	O
shape	O
of	O
the	O
board	O
itself	O
was	O
slightly	O
different	O
.	O
</s>
<s>
Internally	O
the	O
non-pipelined	O
bus	O
transferred	O
data	O
between	O
the	O
various	O
parts	O
of	O
the	O
computer	O
,	O
including	O
GIO	B-Architecture
cards	O
,	O
EISA	B-Device
devices	O
,	O
SCSI	B-Architecture
and	O
so	O
forth	O
.	O
</s>
<s>
GIO	B-Architecture
cards	O
used	O
the	O
pipelined	O
controller	O
to	O
arbitrate	O
and	O
control	O
timing	O
,	O
the	O
data	O
then	O
being	O
fed	O
into	O
main	O
memory	O
via	O
the	O
internal	O
non-pipelined	O
side	O
.	O
</s>
<s>
For	O
low-throughput	O
cards	O
,	O
GIO32-bis	O
allowed	O
a	O
single	O
device	O
to	O
be	O
used	O
on	O
any	O
machine	O
supporting	O
GIO	B-Architecture
,	O
no	O
matter	O
what	O
generation	O
.	O
</s>
