<s>
The	O
GAL22V10	B-General_Concept
is	O
a	O
series	O
of	O
programmable-logic	O
devices	O
from	O
Lattice	O
Semiconductor	O
,	O
implemented	O
as	O
CMOS-based	O
generic	O
array	O
logic	O
ICs	O
,	O
and	O
available	O
in	O
dual	B-Algorithm
inline	I-Algorithm
packages	I-Algorithm
or	O
plastic	B-Algorithm
leaded	I-Algorithm
chip	I-Algorithm
carriers	I-Algorithm
.	O
</s>
<s>
The	O
GAL22V10	B-General_Concept
has	O
12	O
input	O
pins	O
,	O
and	O
10	O
pins	O
that	O
can	O
be	O
configured	O
as	O
either	O
inputs	O
or	O
outputs	O
,	O
and	O
exists	O
in	O
various	O
switching	O
speeds	O
,	O
from	O
25	O
to	O
4	O
ns	O
.	O
</s>
<s>
Combinations	O
are	O
set	O
using	O
an	O
E2PROM	B-General_Concept
.	O
</s>
<s>
The	O
output	O
registers	O
can	O
be	O
preloaded	O
into	O
a	O
potentially	O
invalid	O
state	O
for	O
testing	O
by	O
a	O
GAL22V10	B-General_Concept
programmer	O
.	O
</s>
<s>
Inputs	O
and	O
outputs	O
include	O
active	O
pull-ups	O
and	O
are	O
transistor-transistor	B-General_Concept
logic	I-General_Concept
compatible	O
due	O
to	O
high-impedance	O
buffers	O
.	O
</s>
<s>
A	O
user	O
electronic	O
signature	O
section	O
is	O
included	O
for	O
details	O
such	O
as	O
user	O
ID	O
codes	O
,	O
revision	O
IDs	O
,	O
or	O
asset	O
tagging	O
on	O
official	O
Lattice	O
Semiconductor	O
units	O
,	O
as	O
well	O
as	O
a	O
static	O
ES	O
section	O
for	O
compatibility	O
with	O
non-Lattice	O
Semiconductor	O
GAL22V10	B-General_Concept
units	O
.	O
</s>
