<s>
Fully	B-General_Concept
Buffered	I-General_Concept
DIMM	I-General_Concept
(	O
or	O
FB-DIMM	B-General_Concept
)	O
is	O
a	O
memory	O
technology	O
that	O
can	O
be	O
used	O
to	O
increase	O
reliability	O
and	O
density	O
of	O
memory	O
systems	O
.	O
</s>
<s>
Unlike	O
the	O
parallel	O
bus	O
architecture	O
of	O
traditional	O
DRAMs	O
,	O
an	O
FB-DIMM	B-General_Concept
has	O
a	O
serial	B-Protocol
interface	I-Protocol
between	O
the	O
memory	B-General_Concept
controller	I-General_Concept
and	O
the	O
advanced	O
memory	O
buffer	O
(	O
AMB	O
)	O
.	O
</s>
<s>
Conventionally	O
,	O
data	O
lines	O
from	O
the	O
memory	B-General_Concept
controller	I-General_Concept
have	O
to	O
be	O
connected	O
to	O
data	O
lines	O
in	O
every	O
DRAM	O
module	O
,	O
i.e.	O
</s>
<s>
via	O
multidrop	B-Architecture
buses	O
.	O
</s>
<s>
This	O
limits	O
the	O
speed	O
and	O
memory	O
density	O
,	O
so	O
FB-DIMMs	B-General_Concept
take	O
a	O
different	O
approach	O
to	O
solve	O
the	O
problem	O
.	O
</s>
<s>
240-pin	O
DDR2	O
FB-DIMMs	B-General_Concept
are	O
neither	O
mechanically	O
nor	O
electrically	O
compatible	O
with	O
conventional	O
240-pin	O
DDR2	O
DIMMs	B-General_Concept
.	O
</s>
<s>
As	O
a	O
result	O
,	O
those	O
two	O
DIMM	B-General_Concept
types	O
are	O
notched	O
differently	O
to	O
prevent	O
using	O
the	O
wrong	O
one	O
.	O
</s>
<s>
As	O
with	O
nearly	O
all	O
RAM	O
specifications	O
,	O
the	O
FB-DIMM	B-General_Concept
specification	O
was	O
published	O
by	O
JEDEC	O
.	O
</s>
<s>
Fully	B-General_Concept
buffered	I-General_Concept
DIMM	I-General_Concept
architecture	O
introduces	O
an	O
advanced	O
memory	O
buffer	O
(	O
AMB	O
)	O
between	O
the	O
memory	B-General_Concept
controller	I-General_Concept
and	O
the	O
memory	O
module	O
.	O
</s>
<s>
Unlike	O
the	O
parallel	O
bus	O
architecture	O
of	O
traditional	O
DRAMs	O
,	O
an	O
FB-DIMM	B-General_Concept
has	O
a	O
serial	B-Protocol
interface	I-Protocol
between	O
the	O
memory	B-General_Concept
controller	I-General_Concept
and	O
the	O
AMB	O
.	O
</s>
<s>
This	O
enables	O
an	O
increase	O
to	O
the	O
width	O
of	O
the	O
memory	O
without	O
increasing	O
the	O
pin	O
count	O
of	O
the	O
memory	B-General_Concept
controller	I-General_Concept
beyond	O
a	O
feasible	O
level	O
.	O
</s>
<s>
With	O
this	O
architecture	O
,	O
the	O
memory	B-General_Concept
controller	I-General_Concept
does	O
not	O
write	O
to	O
the	O
memory	O
module	O
directly	O
;	O
rather	O
it	O
is	O
done	O
via	O
the	O
AMB	O
.	O
</s>
<s>
The	O
AMB	O
can	O
also	O
offer	O
error	B-Error_Name
correction	I-Error_Name
,	O
without	O
imposing	O
any	O
additional	O
overhead	O
on	O
the	O
processor	O
or	O
the	O
system	O
's	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
Also	O
,	O
since	O
reads	O
and	O
writes	O
are	O
buffered	O
,	O
they	O
can	O
be	O
done	O
in	O
parallel	O
by	O
the	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
This	O
allows	O
simpler	O
interconnects	O
,	O
and	O
(	O
in	O
theory	O
)	O
hardware-agnostic	O
memory	B-General_Concept
controller	I-General_Concept
chips	O
(	O
such	O
as	O
DDR2	O
and	O
DDR3	O
)	O
that	O
can	O
be	O
used	O
interchangeably	O
.	O
</s>
<s>
The	O
downsides	O
to	O
this	O
approach	O
are	O
;	O
it	O
introduces	O
latency	B-General_Concept
to	O
the	O
memory	O
request	O
,	O
it	O
requires	O
additional	O
power	O
consumption	O
for	O
the	O
buffer	O
chips	O
,	O
and	O
current	O
implementations	O
create	O
a	O
memory	O
write	O
bus	O
significantly	O
narrower	O
than	O
the	O
memory	O
read	O
bus	O
.	O
</s>
<s>
This	O
means	O
workloads	O
that	O
use	O
many	O
writes	O
(	O
such	O
as	O
high-performance	B-Architecture
computing	I-Architecture
)	O
will	O
be	O
significantly	O
slowed	O
.	O
</s>
<s>
However	O
,	O
this	O
slowdown	O
is	O
nowhere	O
near	O
as	O
bad	O
as	O
not	O
having	O
enough	O
memory	O
capacity	O
to	O
avoid	O
using	O
significant	O
amounts	O
of	O
virtual	B-Architecture
memory	I-Architecture
,	O
so	O
workloads	O
that	O
use	O
extreme	O
amounts	O
of	O
memory	O
in	O
irregular	O
patterns	O
might	O
be	O
helped	O
by	O
using	O
fully	B-General_Concept
buffered	I-General_Concept
DIMMs	I-General_Concept
.	O
</s>
<s>
The	O
FB-DIMM	B-General_Concept
channel	O
consists	O
of	O
14	O
"	O
northbound	O
"	O
bit	O
lanes	O
carrying	O
data	O
from	O
memory	O
to	O
the	O
processor	O
and	O
10	O
"	O
southbound	O
"	O
bit	O
lanes	O
carrying	O
commands	O
and	O
data	O
from	O
the	O
processor	O
to	O
memory	O
.	O
</s>
<s>
One	O
northbound	O
frame	O
carries	O
144	O
data	O
bits	O
,	O
the	O
amount	O
of	O
data	O
produced	O
by	O
a	O
72-bit	O
wide	O
DDR	O
SDRAM	O
array	O
in	O
that	O
time	O
,	O
and	O
24	O
bits	O
of	O
CRC	O
for	O
error	B-Error_Name
detection	I-Error_Name
.	O
</s>
<s>
All	O
commands	O
include	O
a	O
3-bit	O
FB-DIMM	B-General_Concept
address	O
,	O
allowing	O
up	O
to	O
8	O
FB-DIMM	B-General_Concept
modules	O
on	O
a	O
channel	O
.	O
</s>
<s>
Note	O
that	O
the	O
bandwidth	O
of	O
an	O
FB-DIMM	B-General_Concept
channel	O
is	O
equal	O
to	O
the	O
peak	O
read	O
bandwidth	O
of	O
a	O
DDR	O
memory	O
channel	O
(	O
and	O
this	O
speed	O
can	O
be	O
sustained	O
,	O
as	O
there	O
is	O
no	O
contention	O
for	O
the	O
northbound	O
channel	O
)	O
,	O
plus	O
half	O
of	O
the	O
peak	O
write	O
bandwidth	O
of	O
a	O
DDR	O
memory	O
channel	O
(	O
which	O
can	O
often	O
be	O
sustained	O
,	O
if	O
one	O
command	O
per	O
frame	O
is	O
sufficient	O
)	O
.	O
</s>
<s>
Intel	O
has	O
adopted	O
the	O
technology	O
for	O
their	O
Xeon	B-Device
5000/5100	O
series	O
and	O
beyond	O
,	O
which	O
they	O
consider	O
"	O
a	O
long-term	O
strategic	O
direction	O
for	O
servers	O
"	O
.	O
</s>
<s>
Sun	O
Microsystems	O
used	O
FB-DIMMs	B-General_Concept
for	O
the	O
Niagara	B-Device
II	I-Device
(	O
UltraSparc	B-Device
T2	I-Device
)	O
server	O
processor	O
.	O
</s>
<s>
Intel	O
's	O
enthusiast	O
system	O
platform	O
Skulltrail	B-Device
uses	O
FB-DIMMs	B-General_Concept
for	O
their	O
dual	O
CPU	O
socket	O
,	O
multi-GPU	O
system	O
.	O
</s>
<s>
FB-DIMMS	B-General_Concept
have	O
240	O
pins	O
and	O
are	O
the	O
same	O
total	O
length	O
as	O
other	O
DDR	O
DIMMs	B-General_Concept
but	O
differ	O
by	O
having	O
indents	O
on	O
both	O
ends	O
within	O
the	O
slot	O
.	O
</s>
<s>
The	O
cost	O
of	O
FB-DIMM	B-General_Concept
memory	O
was	O
initially	O
much	O
higher	O
than	O
registered	B-General_Concept
DIMM	I-General_Concept
,	O
which	O
may	O
be	O
one	O
of	O
the	O
factors	O
behind	O
its	O
current	O
level	O
of	O
acceptance	O
.	O
</s>
<s>
Although	O
strenuous	O
efforts	O
were	O
made	O
to	O
minimize	O
delay	O
in	O
the	O
AMB	O
,	O
there	O
is	O
some	O
noticeable	O
cost	O
in	O
memory	O
access	O
latency	B-General_Concept
.	O
</s>
<s>
As	O
of	O
September	O
2006	O
,	O
AMD	O
has	O
taken	O
FB-DIMM	B-General_Concept
off	O
their	O
roadmap	O
.	O
</s>
<s>
In	O
December	O
2006	O
,	O
AMD	O
has	O
revealed	O
in	O
one	O
of	O
the	O
slides	O
that	O
microprocessors	O
based	O
on	O
the	O
new	O
K10	O
microarchitecture	O
has	O
the	O
support	O
for	O
FB-DIMM	B-General_Concept
"	O
when	O
appropriate	O
"	O
.	O
</s>
<s>
In	O
addition	O
,	O
AMD	O
also	O
developed	O
Socket	B-Device
G3	I-Device
Memory	I-Device
Extender	I-Device
(	O
G3MX	B-Device
)	O
,	O
which	O
uses	O
a	O
single	O
buffer	O
for	O
every	O
4	O
modules	O
instead	O
of	O
one	O
for	O
each	O
,	O
to	O
be	O
used	O
by	O
Opteron-based	O
systems	O
in	O
2009	O
.	O
</s>
<s>
At	O
the	O
2007	O
Intel	O
Developer	O
Forum	O
,	O
it	O
was	O
revealed	O
that	O
major	O
memory	O
manufacturers	O
have	O
no	O
plans	O
to	O
extend	O
FB-DIMM	B-General_Concept
to	O
support	O
DDR3	O
SDRAM	O
.	O
</s>
<s>
Instead	O
,	O
only	O
registered	B-General_Concept
DIMM	I-General_Concept
for	O
DDR3	O
SDRAM	O
had	O
been	O
demonstrated	O
.	O
</s>
<s>
In	O
2007	O
,	O
Intel	O
demonstrated	O
FB-DIMM	B-General_Concept
with	O
shorter	O
latencies	O
,	O
CL5	O
and	O
CL3	O
,	O
showing	O
improvement	O
in	O
latencies	O
.	O
</s>
<s>
On	O
August	O
5	O
,	O
2008	O
,	O
Elpida	O
Memory	O
announced	O
that	O
it	O
would	O
mass-produce	O
the	O
world	O
's	O
first	O
FB-DIMM	B-General_Concept
at	O
16	O
Gigabyte	O
capacity	O
,	O
as	O
from	O
Q4	O
2008	O
,	O
however	O
the	O
product	O
has	O
not	O
appeared	O
and	O
the	O
press	O
release	O
has	O
been	O
deleted	O
from	O
Elpida	O
's	O
site	O
.	O
</s>
