<s>
The	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
is	O
a	O
computer	O
communication	O
interface	O
(	O
bus	B-General_Concept
)	O
that	O
was	O
often	O
used	O
in	O
Intel-chip-based	O
computers	O
during	O
the	O
1990s	O
and	O
2000s	O
.	O
</s>
<s>
The	O
EV6	O
bus	B-General_Concept
served	O
the	O
same	O
function	O
for	O
competing	O
AMD	O
CPUs	O
.	O
</s>
<s>
Both	O
typically	O
carry	O
data	O
between	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
a	O
memory	B-Device
controller	I-Device
hub	I-Device
,	O
known	O
as	O
the	O
northbridge	B-Device
.	O
</s>
<s>
Depending	O
on	O
the	O
implementation	O
,	O
some	O
computers	O
may	O
also	O
have	O
a	O
back-side	B-Architecture
bus	I-Architecture
that	O
connects	O
the	O
CPU	O
to	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
This	O
bus	B-General_Concept
and	O
the	O
cache	B-General_Concept
connected	O
to	O
it	O
are	O
faster	O
than	O
accessing	O
the	O
system	B-Architecture
memory	I-Architecture
(	O
or	O
RAM	B-Architecture
)	O
via	O
the	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
speed	O
of	O
the	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
is	O
often	O
used	O
as	O
an	O
important	O
measure	O
of	O
the	O
performance	O
of	O
a	O
computer	O
.	O
</s>
<s>
The	O
original	O
front-side	B-Architecture
bus	I-Architecture
architecture	O
has	O
been	O
replaced	O
by	O
HyperTransport	B-Device
,	O
Intel	B-Architecture
QuickPath	I-Architecture
Interconnect	I-Architecture
or	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
in	O
modern	O
volume	O
CPUs	O
.	O
</s>
<s>
The	O
term	O
came	O
into	O
use	O
by	O
Intel	O
Corporation	O
about	O
the	O
time	O
the	O
Pentium	B-Device
Pro	I-Device
and	O
Pentium	B-General_Concept
II	I-General_Concept
products	O
were	O
announced	O
,	O
in	O
the	O
1990s	O
.	O
</s>
<s>
"	O
Front	O
side	O
"	O
refers	O
to	O
the	O
external	O
interface	O
from	O
the	O
processor	O
to	O
the	O
rest	O
of	O
the	O
computer	O
system	O
,	O
as	O
opposed	O
to	O
the	O
back	O
side	O
,	O
where	O
the	O
back-side	B-Architecture
bus	I-Architecture
connects	O
the	O
cache	B-General_Concept
(	O
and	O
potentially	O
other	O
CPUs	O
)	O
.	O
</s>
<s>
A	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
is	O
mostly	O
used	O
on	O
PC-related	O
motherboards	B-Device
(	O
including	O
personal	B-Device
computers	I-Device
and	O
servers	O
)	O
.	O
</s>
<s>
They	O
are	O
seldom	O
used	O
in	O
embedded	B-Architecture
systems	I-Architecture
or	O
similar	O
small	O
computers	O
.	O
</s>
<s>
The	O
FSB	O
design	O
was	O
a	O
performance	O
improvement	O
over	O
the	O
single	O
system	B-Architecture
bus	I-Architecture
designs	O
of	O
the	O
previous	O
decades	O
,	O
but	O
these	O
front-side	O
buses	O
are	O
sometimes	O
referred	O
to	O
as	O
the	O
"	O
system	B-Architecture
bus	I-Architecture
"	O
.	O
</s>
<s>
Front-side	O
buses	O
usually	O
connect	O
the	O
CPU	O
and	O
the	O
rest	O
of	O
the	O
hardware	O
via	O
a	O
chipset	B-Device
,	O
which	O
Intel	O
implemented	O
as	O
a	O
northbridge	B-Device
and	O
a	O
southbridge	B-Device
.	O
</s>
<s>
Other	O
buses	O
like	O
the	O
Peripheral	B-Protocol
Component	I-Protocol
Interconnect	I-Protocol
(	O
PCI	B-Protocol
)	O
,	O
Accelerated	B-Architecture
Graphics	I-Architecture
Port	I-Architecture
(	O
AGP	O
)	O
,	O
and	O
memory	O
buses	O
all	O
connect	O
to	O
the	O
chipset	B-Device
in	O
order	O
for	O
data	O
to	O
flow	O
between	O
the	O
connected	O
devices	O
.	O
</s>
<s>
These	O
secondary	O
system	O
buses	O
usually	O
run	O
at	O
speeds	O
derived	O
from	O
the	O
front-side	B-Architecture
bus	I-Architecture
clock	O
,	O
but	O
are	O
not	O
necessarily	O
synchronized	O
to	O
it	O
.	O
</s>
<s>
In	O
response	O
to	O
AMD	O
's	O
Torrenza	B-General_Concept
initiative	O
,	O
Intel	O
opened	O
its	O
FSB	O
CPU	O
socket	O
to	O
third	O
party	O
devices	O
.	O
</s>
<s>
The	O
first	O
example	O
was	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
co-processors	O
,	O
a	O
result	O
of	O
collaboration	O
between	O
Intel-Xilinx-Nallatech	O
and	O
Intel-Altera-XtremeData	O
(	O
which	O
shipped	O
in	O
2008	O
)	O
.	O
</s>
<s>
The	O
frequency	O
at	O
which	O
a	O
processor	O
(	O
CPU	O
)	O
operates	O
is	O
determined	O
by	O
applying	O
a	O
clock	O
multiplier	O
to	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
speed	O
in	O
some	O
cases	O
.	O
</s>
<s>
This	O
means	O
there	O
is	O
an	O
internal	O
clock	O
multiplier	O
setting	O
(	O
also	O
called	O
bus/core	O
ratio	O
)	O
of	O
8	O
.	O
</s>
<s>
That	O
is	O
,	O
the	O
CPU	O
is	O
set	O
to	O
run	O
at	O
8	O
times	O
the	O
frequency	O
of	O
the	O
front-side	B-Architecture
bus	I-Architecture
:	O
400MHz	O
×	O
8	O
=	O
3200MHz	O
.	O
</s>
<s>
Different	O
CPU	O
speeds	O
are	O
achieved	O
by	O
varying	O
either	O
the	O
FSB	O
frequency	O
or	O
the	O
CPU	O
multiplier	O
,	O
this	O
is	O
referred	O
to	O
as	O
Overclocking	B-Application
or	O
Underclocking	B-Device
.	O
</s>
<s>
The	O
memory	O
bus	B-General_Concept
connects	O
the	O
northbridge	B-Device
and	O
RAM	B-Architecture
,	O
just	O
as	O
the	O
front-side	B-Architecture
bus	I-Architecture
connects	O
the	O
CPU	O
and	O
northbridge	B-Device
.	O
</s>
<s>
Increasing	O
the	O
front-side	B-Architecture
bus	I-Architecture
to	O
450MHz	O
in	O
most	O
cases	O
also	O
means	O
running	O
the	O
memory	O
at	O
450MHz	O
.	O
</s>
<s>
The	O
memory	O
will	O
run	O
5/4	O
times	O
as	O
fast	O
as	O
the	O
FSB	O
in	O
this	O
situation	O
,	O
meaning	O
a	O
400MHz	O
bus	B-General_Concept
can	O
run	O
with	O
the	O
memory	O
at	O
500MHz	O
.	O
</s>
<s>
In	O
image	O
,	O
audio	O
,	O
video	O
,	O
gaming	O
,	O
FPGA	B-Architecture
synthesis	O
and	O
scientific	O
applications	O
that	O
perform	O
a	O
small	O
amount	O
of	O
work	O
on	O
each	O
element	O
of	O
a	O
large	O
data	B-General_Concept
set	I-General_Concept
,	O
FSB	O
speed	O
becomes	O
a	O
major	O
performance	O
issue	O
.	O
</s>
<s>
A	O
slow	O
FSB	O
will	O
cause	O
the	O
CPU	O
to	O
spend	O
significant	O
amounts	O
of	O
time	O
waiting	O
for	O
data	O
to	O
arrive	O
from	O
system	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Similar	O
to	O
the	O
memory	O
bus	B-General_Concept
,	O
the	O
PCI	B-Protocol
and	O
AGP	O
buses	O
can	O
also	O
be	O
run	O
asynchronously	O
from	O
the	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
In	O
older	O
systems	O
,	O
these	O
buses	O
are	O
operated	O
at	O
a	O
set	O
fraction	O
of	O
the	O
front-side	B-Architecture
bus	I-Architecture
frequency	O
.	O
</s>
<s>
This	O
fraction	O
was	O
set	O
by	O
the	O
BIOS	B-Operating_System
.	O
</s>
<s>
In	O
newer	O
systems	O
,	O
the	O
PCI	B-Protocol
,	O
AGP	O
,	O
and	O
PCI	B-Protocol
Express	O
peripheral	O
buses	O
often	O
receive	O
their	O
own	O
clock	O
signals	O
,	O
which	O
eliminates	O
their	O
dependence	O
on	O
the	O
front-side	B-Architecture
bus	I-Architecture
for	O
timing	O
.	O
</s>
<s>
Overclocking	B-Application
is	O
the	O
practice	O
of	O
making	O
computer	O
components	O
operate	O
beyond	O
their	O
stock	O
performance	O
levels	O
by	O
manipulating	O
the	O
frequencies	O
at	O
which	O
the	O
component	O
is	O
set	O
to	O
run	O
,	O
and	O
,	O
when	O
necessary	O
,	O
modifying	O
the	O
voltage	O
sent	O
to	O
the	O
component	O
to	O
allow	O
it	O
to	O
operate	O
at	O
these	O
higher	O
frequencies	O
with	O
more	O
stability	O
.	O
</s>
<s>
Many	O
motherboards	B-Device
allow	O
the	O
user	O
to	O
manually	O
set	O
the	O
clock	O
multiplier	O
and	O
FSB	O
settings	O
by	O
changing	O
jumpers	B-Device
or	O
BIOS	B-Operating_System
settings	I-Operating_System
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
unlock	O
some	O
locked	O
CPUs	O
;	O
for	O
instance	O
,	O
some	O
AMD	B-Architecture
Athlon	I-Architecture
processors	O
can	O
be	O
unlocked	O
by	O
connecting	O
electrical	O
contacts	O
across	O
points	O
on	O
the	O
CPU	O
's	O
surface	O
.	O
</s>
<s>
For	O
all	O
processors	O
,	O
increasing	O
the	O
FSB	O
speed	O
can	O
be	O
done	O
to	O
boost	O
processing	O
speed	O
by	O
reducing	O
latency	O
between	O
CPU	O
and	O
the	O
northbridge	B-Device
.	O
</s>
<s>
Most	O
PCs	B-Device
purchased	O
from	O
retailers	O
or	O
manufacturers	O
,	O
such	O
as	O
Hewlett-Packard	O
or	O
Dell	O
,	O
do	O
not	O
allow	O
the	O
user	O
to	O
change	O
the	O
multiplier	O
or	O
FSB	O
settings	O
due	O
to	O
the	O
probability	O
of	O
erratic	O
behavior	O
or	O
failure	O
.	O
</s>
<s>
Motherboards	B-Device
purchased	O
separately	O
to	O
build	O
a	O
custom	O
machine	O
are	O
more	O
likely	O
to	O
allow	O
the	O
user	O
to	O
edit	O
the	O
multiplier	O
and	O
FSB	O
settings	O
in	O
the	O
PC	B-Device
's	O
BIOS	B-Operating_System
.	O
</s>
<s>
The	O
front-side	B-Architecture
bus	I-Architecture
had	O
the	O
advantage	O
of	O
high	O
flexibility	O
and	O
low	O
cost	O
when	O
it	O
was	O
first	O
designed	O
.	O
</s>
<s>
Simple	O
symmetric	B-Operating_System
multiprocessors	I-Operating_System
place	O
a	O
number	O
of	O
CPUs	O
on	O
a	O
shared	O
FSB	O
,	O
though	O
performance	O
could	O
not	O
scale	O
linearly	O
due	O
to	O
bandwidth	O
bottlenecks	O
.	O
</s>
<s>
The	O
front-side	B-Architecture
bus	I-Architecture
was	O
used	O
in	O
all	O
Intel	B-Device
Atom	I-Device
,	O
Celeron	B-Device
,	O
Pentium	B-General_Concept
,	O
Core	B-Device
2	I-Device
,	O
and	O
Xeon	B-Device
processor	O
models	O
through	O
about	O
2008	O
.	O
</s>
<s>
Originally	O
,	O
this	O
bus	B-General_Concept
was	O
a	O
central	O
connecting	O
point	O
for	O
all	O
system	O
devices	O
and	O
the	O
CPU	O
.	O
</s>
<s>
The	O
front-side	B-Architecture
bus	I-Architecture
was	O
criticized	O
by	O
AMD	O
as	O
being	O
an	O
old	O
and	O
slow	O
technology	O
that	O
limits	O
system	O
performance	O
.	O
</s>
<s>
More	O
modern	O
designs	O
use	O
point-to-point	O
and	O
serial	O
connections	O
like	O
AMD	O
's	O
HyperTransport	B-Device
and	O
Intel	O
's	O
DMI	B-Architecture
2.0	I-Architecture
or	O
QuickPath	B-Architecture
Interconnect	I-Architecture
(	O
QPI	B-Architecture
)	O
.	O
</s>
<s>
These	O
implementations	O
remove	O
the	O
traditional	O
northbridge	B-Device
in	O
favor	O
of	O
a	O
direct	O
link	O
from	O
the	O
CPU	O
to	O
the	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
,	O
southbridge	B-Device
or	O
I/O	O
controller	O
.	O
</s>
<s>
In	O
a	O
traditional	O
architecture	O
,	O
the	O
front-side	B-Architecture
bus	I-Architecture
served	O
as	O
the	O
immediate	O
data	O
link	O
between	O
the	O
CPU	O
and	O
all	O
other	O
devices	O
in	O
the	O
system	O
,	O
including	O
main	O
memory	O
.	O
</s>
<s>
In	O
HyperTransport	B-Device
-	O
and	O
QPI-based	O
systems	O
,	O
system	B-Architecture
memory	I-Architecture
is	O
accessed	O
independently	O
by	O
means	O
of	O
a	O
memory	B-General_Concept
controller	I-General_Concept
integrated	O
into	O
the	O
CPU	O
,	O
leaving	O
the	O
bandwidth	O
on	O
the	O
HyperTransport	B-Device
or	O
QPI	B-Architecture
link	O
for	O
other	O
uses	O
.	O
</s>
<s>
The	O
bandwidth	O
or	O
maximum	O
theoretical	O
throughput	O
of	O
the	O
front-side	B-Architecture
bus	I-Architecture
is	O
determined	O
by	O
the	O
product	O
of	O
the	O
width	O
of	O
its	O
data	O
path	O
,	O
its	O
clock	O
frequency	O
(	O
cycles	O
per	O
second	O
)	O
and	O
the	O
number	O
of	O
data	O
transfers	O
it	O
performs	O
per	O
clock	O
cycle	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
64-bit	O
(	O
8-byte	O
)	O
wide	O
FSB	O
operating	O
at	O
a	O
frequency	O
of	O
100MHz	O
that	O
performs	O
4	O
transfers	O
per	O
cycle	O
has	O
a	O
bandwidth	O
of	O
3200	O
megabytes	O
per	O
second	O
(	O
MB/s	O
)	O
:	O
</s>
<s>
For	O
example	O
,	O
GTL+	B-General_Concept
performs	O
1	O
transfer/cycle	O
,	O
EV6	O
2	O
transfers/cycle	O
,	O
and	O
AGTL+	B-General_Concept
4	O
transfers/cycle	O
.	O
</s>
<s>
Intel	O
calls	O
the	O
technique	O
of	O
four	O
transfers	O
per	O
cycle	O
Quad	B-Device
Pumping	I-Device
.	O
</s>
<s>
Many	O
manufacturers	O
publish	O
the	O
frequency	O
of	O
the	O
front-side	B-Architecture
bus	I-Architecture
in	O
MHz	O
,	O
but	O
marketing	O
materials	O
often	O
list	O
the	O
theoretical	O
effective	O
signaling	O
rate	O
(	O
which	O
is	O
commonly	O
called	O
megatransfers	O
per	O
second	O
or	O
MT/s	O
)	O
.	O
</s>
<s>
For	O
example	O
,	O
if	O
a	O
motherboard	B-Device
(	O
or	O
processor	O
)	O
has	O
its	O
bus	B-General_Concept
set	O
at	O
200MHz	O
and	O
performs	O
4	O
transfers	O
per	O
clock	O
cycle	O
,	O
the	O
FSB	O
is	O
rated	O
at	O
800	O
MT/s	O
.	O
</s>
