<s>
The	O
Freescale	B-Device
683xx	I-Device
(	O
formerly	O
Motorola	B-Device
683xx	I-Device
)	O
is	O
a	O
family	O
of	O
compatible	O
microcontrollers	B-Architecture
by	O
Freescale	O
that	O
use	O
a	O
Motorola	O
68000-based	O
CPU	B-General_Concept
core	O
.	O
</s>
<s>
There	O
are	O
two	O
CPU	B-General_Concept
cores	O
used	O
in	O
the	O
683xx	O
family	O
:	O
the	O
68EC000	O
and	O
the	O
CPU32	B-Device
.	O
</s>
<s>
The	O
instruction	O
set	O
of	O
the	O
CPU32	B-Device
core	O
is	O
similar	O
to	O
the	O
68020	B-Device
without	O
bitfield	O
instructions	O
,	O
and	O
with	O
a	O
few	O
instructions	O
unique	O
to	O
the	O
CPU32	B-Device
core	O
,	O
such	O
as	O
table	O
lookup	O
and	O
interpolate	O
instructions	O
,	O
and	O
a	O
low-power	O
stop	O
mode	O
.	O
</s>
<s>
The	O
modules	O
of	O
the	O
microcontroller	B-Architecture
were	O
designed	O
independently	O
and	O
released	O
as	O
new	O
CPUs	O
could	O
be	O
tested	O
.	O
</s>
<s>
The	O
microcontrollers	B-Architecture
consist	O
of	O
a	O
series	O
of	O
modules	O
,	O
connected	O
by	O
an	O
internal	O
bus	O
:	O
</s>
<s>
A	O
fully	O
static	O
CPU	B-General_Concept
core	O
,	O
capable	O
of	O
running	O
at	O
any	O
clock	O
speed	O
from	O
dead	O
stop	O
to	O
maximum	O
rated	O
speed	O
(	O
25	O
or	O
33MHz	O
)	O
.	O
</s>
<s>
A	O
CPU	B-General_Concept
core	O
designed	O
to	O
minimize	O
transistors	O
while	O
maximizing	O
performance	O
.	O
</s>
<s>
A	O
high-speed	O
clocked	O
serial	O
interface	O
for	O
debugging	O
called	O
background	B-Application
debug	I-Application
mode	I-Application
(	O
BDM	O
)	O
.	O
</s>
<s>
The	O
683xx-series	O
was	O
the	O
first	O
to	O
have	O
a	O
clocked	O
serial	O
interface	O
to	O
the	O
CPU	B-General_Concept
to	O
perform	O
debugging	O
.	O
</s>
<s>
An	O
auxiliary	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
doubles	O
as	O
a	O
programmable	O
microcontroller	B-Architecture
store	O
for	O
the	O
TPU	O
.	O
</s>
<s>
A	O
general	O
purpose	O
timer	O
(	O
GPT	O
)	O
module	O
provides	O
pulse	O
accumulators	O
,	O
capture/compare	O
,	O
and	O
pulse-width	B-Algorithm
modulation	I-Algorithm
capabilities	O
.	O
</s>
<s>
Some	O
models	O
have	O
a	O
network	B-General_Concept
interface	I-General_Concept
processor	I-General_Concept
in	O
the	O
form	O
of	O
a	O
communication	B-Device
processor	I-Device
module	I-Device
(	O
CPM	O
)	O
and	O
serial	O
communications	O
controllers	O
(	O
SCC	O
)	O
which	O
can	O
be	O
interfaced	O
to	O
Ethernet	O
or	O
HDLC	O
busses	O
.	O
</s>
<s>
Most	O
models	O
have	O
a	O
queued	O
serial	O
module	O
(	O
QSM	O
)	O
which	O
provides	O
both	O
synchronous	O
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
(	O
SPI	O
)	O
,	O
and	O
logic-level	O
RS-232	O
UART	O
capabilities	O
.	O
</s>
