<s>
Foxton	O
is	O
an	O
Intel	O
code-name	O
for	O
a	O
power-management	O
technology	O
that	O
was	O
originally	O
planned	O
for	O
inclusion	O
in	O
the	O
first	O
dual-core	O
Itanium	O
2	O
processor	O
(	O
code-named	O
Montecito	B-Device
)	O
.	O
</s>
<s>
Due	O
to	O
unspecified	O
issues	O
,	O
Foxton	O
was	O
not	O
included	O
in	O
the	O
initial	O
release	O
of	O
Montecito	B-Device
.	O
</s>
<s>
Foxton	B-Device
technology	I-Device
includes	O
a	O
highly	O
advanced	O
clock	O
generation	O
and	O
distribution	O
network	O
.	O
</s>
<s>
However	O
,	O
many	O
software	O
applications	O
can	O
not	O
utilize	O
all	O
the	O
available	O
execution	O
resources	O
,	O
lacking	O
adequate	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
.	O
</s>
<s>
Since	O
modern	O
MPUs	B-Architecture
clock	O
rates	O
are	O
constrained	O
by	O
power	O
,	O
not	O
filling	O
out	O
the	O
power	O
envelope	O
translates	O
to	O
lost	O
performance	O
.	O
</s>
<s>
Foxton	B-Device
technology	I-Device
should	O
increase	O
performance	O
for	O
these	O
applications	O
by	O
about	O
10%	O
compared	O
with	O
the	O
same	O
processor	O
running	O
with	O
a	O
"	O
fixed	O
clock.	O
"	O
</s>
<s>
Intel	O
said	O
Foxton	B-Device
technology	I-Device
will	O
not	O
only	O
appear	O
in	O
the	O
Itanium	O
family	O
,	O
but	O
later	O
in	O
Xeons	O
as	O
well	O
.	O
</s>
