<s>
The	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
(	O
FGMOS	B-Algorithm
)	O
,	O
also	O
known	O
as	O
a	O
floating-gate	B-Algorithm
MOS	B-Architecture
transistor	I-Architecture
or	O
floating-gate	B-Algorithm
transistor	I-Algorithm
,	O
is	O
a	O
type	O
of	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MOSFET	B-Architecture
)	O
where	O
the	O
gate	O
is	O
electrically	O
isolated	O
,	O
creating	O
a	O
floating	O
node	O
in	O
direct	O
current	O
,	O
and	O
a	O
number	O
of	O
secondary	O
gates	O
or	O
inputs	O
are	O
deposited	O
above	O
the	O
floating	B-Algorithm
gate	I-Algorithm
(	O
FG	O
)	O
and	O
are	O
electrically	O
isolated	O
from	O
it	O
.	O
</s>
<s>
The	O
FGMOS	B-Algorithm
is	O
commonly	O
used	O
as	O
a	O
floating-gate	B-Algorithm
memory	B-Algorithm
cell	I-Algorithm
,	O
the	O
digital	B-General_Concept
storage	I-General_Concept
element	O
in	O
EPROM	B-General_Concept
,	O
EEPROM	B-General_Concept
and	O
flash	B-Device
memory	I-Device
technologies	O
.	O
</s>
<s>
Other	O
uses	O
of	O
the	O
FGMOS	B-Algorithm
include	O
a	O
neuronal	O
computational	O
element	O
in	O
neural	B-Architecture
networks	I-Architecture
,	O
analog	O
storage	O
element	O
,	O
digital	O
potentiometers	O
and	O
single-transistor	O
DACs	O
.	O
</s>
<s>
The	O
first	O
MOSFET	B-Architecture
was	O
invented	O
by	O
Mohamed	O
Atalla	O
and	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
,	O
and	O
presented	O
in	O
1960	O
.	O
</s>
<s>
The	O
first	O
report	O
of	O
a	O
FGMOS	B-Algorithm
was	O
later	O
made	O
by	O
Dawon	O
Kahng	O
and	O
Simon	O
Min	O
Sze	O
at	O
Bell	O
Labs	O
,	O
and	O
dates	O
from	O
1967	O
.	O
</s>
<s>
The	O
earliest	O
practical	O
application	O
of	O
FGMOS	B-Algorithm
was	O
floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
,	O
which	O
Kahng	O
and	O
Sze	O
proposed	O
could	O
be	O
used	O
to	O
produce	O
reprogrammable	B-General_Concept
ROM	I-General_Concept
(	O
read-only	B-Device
memory	I-Device
)	O
.	O
</s>
<s>
Initial	O
applications	O
of	O
FGMOS	B-Algorithm
was	O
digital	O
semiconductor	B-Architecture
memory	I-Architecture
,	O
to	O
store	O
nonvolatile	B-General_Concept
data	O
in	O
EPROM	B-General_Concept
,	O
EEPROM	B-General_Concept
and	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
In	O
1989	O
,	O
Intel	O
employed	O
the	O
FGMOS	B-Algorithm
as	O
an	O
analog	O
nonvolatile	B-General_Concept
memory	I-General_Concept
element	O
in	O
its	O
electrically	O
trainable	O
artificial	B-Architecture
neural	I-Architecture
network	I-Architecture
(	O
ETANN	O
)	O
chip	O
,	O
demonstrating	O
the	O
potential	O
of	O
using	O
FGMOS	B-Algorithm
devices	O
for	O
applications	O
other	O
than	O
digital	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Three	O
research	O
accomplishments	O
laid	O
the	O
groundwork	O
for	O
much	O
of	O
the	O
current	O
FGMOS	B-Algorithm
circuit	O
development	O
:	O
</s>
<s>
Thomsen	O
and	O
Brooke	O
's	O
demonstration	O
and	O
use	O
of	O
electron	O
tunneling	O
in	O
a	O
standard	O
CMOS	O
double-poly	O
process	O
allowed	O
many	O
researchers	O
to	O
investigate	O
FGMOS	B-Algorithm
circuits	O
concepts	O
without	O
requiring	O
access	O
to	O
specialized	O
fabrication	O
processes	O
.	O
</s>
<s>
These	O
researchers	O
concentrated	O
on	O
the	O
FG	O
circuit	O
properties	O
instead	O
of	O
the	O
device	O
properties	O
,	O
and	O
used	O
either	O
UV	B-Application
light	O
to	O
equalize	O
charge	O
,	O
or	O
simulated	O
FG	O
elements	O
by	O
opening	O
and	O
closing	O
MOSFET	B-Architecture
switches	O
.	O
</s>
<s>
Carver	O
Mead	O
's	O
adaptive	O
retina	O
gave	O
the	O
first	O
example	O
of	O
using	O
continuously-operating	O
FG	O
programming/erasing	O
techniques	O
,	O
in	O
this	O
case	O
UV	B-Application
light	O
,	O
as	O
the	O
backbone	O
of	O
an	O
adaptive	O
circuit	O
technology	O
.	O
</s>
<s>
An	O
FGMOS	B-Algorithm
can	O
be	O
fabricated	O
by	O
electrically	O
isolating	O
the	O
gate	O
of	O
a	O
standard	O
MOS	B-Architecture
transistor	I-Architecture
,	O
so	O
that	O
there	O
are	O
no	O
resistive	O
connections	O
to	O
its	O
gate	O
.	O
</s>
<s>
A	O
number	O
of	O
secondary	O
gates	O
or	O
inputs	O
are	O
then	O
deposited	O
above	O
the	O
floating	B-Algorithm
gate	I-Algorithm
(	O
FG	O
)	O
and	O
are	O
electrically	O
isolated	O
from	O
it	O
.	O
</s>
<s>
For	O
applications	O
where	O
the	O
charge	O
of	O
the	O
FG	O
needs	O
to	O
be	O
modified	O
,	O
a	O
pair	O
of	O
small	O
extra	O
transistors	O
are	O
added	O
to	O
each	O
FGMOS	B-Algorithm
transistor	O
to	O
conduct	O
the	O
injection	O
and	O
tunneling	O
operations	O
.	O
</s>
<s>
The	O
injection	O
transistor	O
is	O
connected	O
normally	O
and	O
specific	O
voltages	O
are	O
applied	O
to	O
create	O
hot	O
carriers	O
that	O
are	O
then	O
injected	O
via	O
an	O
electric	O
field	O
into	O
the	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
FGMOS	B-Algorithm
transistor	O
for	O
purely	O
capacitive	O
use	O
can	O
be	O
fabricated	O
on	O
N	O
or	O
P	O
versions	O
.	O
</s>
<s>
For	O
charge	O
modification	O
applications	O
,	O
the	O
tunneling	O
transistor	O
(	O
and	O
therefore	O
the	O
operating	O
FGMOS	B-Algorithm
)	O
needs	O
to	O
be	O
embedded	O
into	O
a	O
well	O
,	O
hence	O
the	O
technology	O
dictates	O
the	O
type	O
of	O
FGMOS	B-Algorithm
that	O
can	O
be	O
fabricated	O
.	O
</s>
<s>
The	O
equations	O
modeling	O
the	O
DC	O
operation	O
of	O
the	O
FGMOS	B-Algorithm
can	O
be	O
derived	O
from	O
the	O
equations	O
that	O
describe	O
the	O
operation	O
of	O
the	O
MOS	B-Architecture
transistor	I-Architecture
used	O
to	O
build	O
the	O
FGMOS	B-Algorithm
.	O
</s>
<s>
If	O
it	O
is	O
possible	O
to	O
determine	O
the	O
voltage	O
at	O
the	O
FG	O
of	O
an	O
FGMOS	B-Algorithm
device	O
,	O
it	O
is	O
then	O
possible	O
to	O
express	O
its	O
drain	O
to	O
source	O
current	O
using	O
standard	O
MOS	B-Architecture
transistor	I-Architecture
models	O
.	O
</s>
<s>
Therefore	O
,	O
to	O
derive	O
a	O
set	O
of	O
equations	O
that	O
model	O
the	O
large	O
signal	O
operation	O
of	O
an	O
FGMOS	B-Algorithm
device	O
,	O
it	O
is	O
necessary	O
to	O
find	O
the	O
relationship	O
between	O
its	O
effective	O
input	O
voltages	O
and	O
the	O
voltage	O
at	O
its	O
FG	O
.	O
</s>
<s>
An	O
N-input	O
FGMOS	B-Algorithm
device	O
has	O
N−1	O
more	O
terminals	O
than	O
a	O
MOS	B-Architecture
transistor	I-Architecture
,	O
and	O
therefore	O
,	O
N+2	O
small	O
signal	O
parameters	O
can	O
be	O
defined	O
:	O
N	O
effective	O
input	O
transconductances	B-Algorithm
,	O
an	O
output	O
transconductance	B-Algorithm
and	O
a	O
bulk	O
transconductance	B-Algorithm
.	O
</s>
<s>
where	O
is	O
the	O
total	O
capacitance	O
seen	O
by	O
the	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
These	O
equations	O
show	O
two	O
drawbacks	O
of	O
the	O
FGMOS	B-Algorithm
compared	O
with	O
the	O
MOS	B-Architecture
transistor	I-Architecture
:	O
</s>
<s>
This	O
generates	O
two	O
problems	O
:	O
first	O
,	O
it	O
is	O
not	O
easy	O
to	O
simulate	O
these	O
circuits	O
;	O
and	O
second	O
,	O
an	O
unknown	O
amount	O
of	O
charge	O
might	O
stay	O
trapped	O
at	O
the	O
floating	B-Algorithm
gate	I-Algorithm
during	O
the	O
fabrication	O
process	O
which	O
will	O
result	O
in	O
an	O
unknown	O
initial	O
condition	O
for	O
the	O
FG	O
voltage	O
.	O
</s>
<s>
The	O
values	O
of	O
the	O
FGs	O
can	O
then	O
be	O
extracted	O
and	O
used	O
for	O
posterior	O
small-signal	O
simulations	O
,	O
connecting	O
a	O
voltage	O
supply	O
with	O
the	O
initial	O
FG	O
value	O
to	O
the	O
floating	B-Algorithm
gate	I-Algorithm
using	O
a	O
very-high-value	O
inductor	O
.	O
</s>
<s>
The	O
usage	O
and	O
applications	O
of	O
the	O
FGMOS	B-Algorithm
can	O
be	O
broadly	O
classified	O
in	O
two	O
cases	O
.	O
</s>
<s>
If	O
the	O
charge	O
in	O
the	O
floating	B-Algorithm
gate	I-Algorithm
is	O
not	O
modified	O
during	O
the	O
circuit	O
usage	O
,	O
the	O
operation	O
is	O
capacitively	O
coupled	O
.	O
</s>
<s>
In	O
the	O
capacitively	O
coupled	O
regime	O
of	O
operation	O
,	O
the	O
net	O
charge	O
in	O
the	O
floating	B-Algorithm
gate	I-Algorithm
is	O
not	O
modified	O
.	O
</s>
<s>
Using	O
the	O
FGMOS	B-Algorithm
as	O
a	O
programmable	O
charge	O
element	O
,	O
it	O
is	O
commonly	O
used	O
for	O
non-volatile	B-General_Concept
storage	I-General_Concept
such	O
as	O
flash	B-Device
,	O
EPROM	B-General_Concept
and	O
EEPROM	B-General_Concept
memory	B-General_Concept
.	O
</s>
<s>
In	O
this	O
context	O
,	O
floating-gate	B-Algorithm
MOSFETs	I-Algorithm
are	O
useful	O
because	O
of	O
their	O
ability	O
to	O
store	O
an	O
electrical	O
charge	O
for	O
extended	O
periods	O
of	O
time	O
without	O
a	O
connection	O
to	O
a	O
power	O
supply	O
.	O
</s>
<s>
Other	O
applications	O
of	O
the	O
FGMOS	B-Algorithm
are	O
neuronal	O
computational	O
element	O
in	O
neural	B-Architecture
networks	I-Architecture
,	O
analog	O
storage	O
element	O
and	O
e-pots	O
.	O
</s>
