<s>
In	O
electronics	O
,	O
flip-flops	B-General_Concept
and	O
latches	B-General_Concept
are	O
circuits	O
that	O
have	O
two	O
stable	O
states	O
that	O
can	O
store	O
state	B-Application
information	O
–	O
a	O
bistable	O
multivibrator	O
.	O
</s>
<s>
The	O
circuit	O
can	O
be	O
made	O
to	O
change	O
state	B-Application
by	O
signals	O
applied	O
to	O
one	O
or	O
more	O
control	O
inputs	O
and	O
will	O
output	O
its	O
state	B-Application
(	O
often	O
along	O
with	O
its	O
logical	O
complement	O
too	O
)	O
.	O
</s>
<s>
Flip-flops	B-General_Concept
and	O
latches	B-General_Concept
are	O
fundamental	O
building	O
blocks	O
of	O
digital	O
electronics	O
systems	O
used	O
in	O
computers	O
,	O
communications	O
,	O
and	O
many	O
other	O
types	O
of	O
systems	O
.	O
</s>
<s>
Flip-flops	B-General_Concept
and	O
latches	B-General_Concept
are	O
used	O
as	O
data	O
storage	O
elements	O
to	O
store	O
a	O
single	O
bit	O
(	O
binary	O
digit	O
)	O
of	O
data	O
;	O
one	O
of	O
its	O
two	O
states	O
represents	O
a	O
"	O
one	O
"	O
and	O
the	O
other	O
represents	O
a	O
"	O
zero	O
"	O
.	O
</s>
<s>
Such	O
data	O
storage	O
can	O
be	O
used	O
for	O
storage	O
of	O
state	B-Application
,	O
and	O
such	O
a	O
circuit	O
is	O
described	O
as	O
sequential	O
logic	O
in	O
electronics	O
.	O
</s>
<s>
When	O
used	O
in	O
a	O
finite-state	B-Architecture
machine	I-Architecture
,	O
the	O
output	O
and	O
next	O
state	B-Application
depend	O
not	O
only	O
on	O
its	O
current	O
input	O
,	O
but	O
also	O
on	O
its	O
current	O
state	B-Application
(	O
and	O
hence	O
,	O
previous	O
inputs	O
)	O
.	O
</s>
<s>
The	O
term	O
flip-flop	B-General_Concept
has	O
historically	O
referred	O
generically	O
to	O
both	O
level-triggered	O
(	O
asynchronous	O
,	O
transparent	O
,	O
or	O
opaque	O
)	O
and	O
edge-triggered	O
(	O
synchronous	O
,	O
or	O
clocked	O
)	O
circuits	O
that	O
store	O
a	O
single	O
bit	O
of	O
data	O
using	O
gates	O
.	O
</s>
<s>
Modern	O
authors	O
reserve	O
the	O
term	O
flip-flop	B-General_Concept
exclusively	O
for	O
edge-triggered	O
storage	O
elements	O
and	O
latches	B-General_Concept
for	O
level-triggered	O
ones	O
.	O
</s>
<s>
When	O
a	O
level-triggered	O
latch	B-General_Concept
is	O
enabled	O
it	O
becomes	O
transparent	O
,	O
but	O
an	O
edge-triggered	O
flip-flop	B-General_Concept
'	O
s	O
output	O
only	O
changes	O
on	O
a	O
clock	O
edge	O
(	O
either	O
positive	O
going	O
or	O
negative	O
going	O
)	O
.	O
</s>
<s>
Different	O
types	O
of	O
flip-flops	B-General_Concept
and	O
latches	B-General_Concept
are	O
available	O
as	O
integrated	O
circuits	O
,	O
usually	O
with	O
multiple	O
elements	O
per	O
chip	O
.	O
</s>
<s>
For	O
example	O
,	O
74HC75	O
is	O
a	O
quadruple	O
transparent	O
latch	B-General_Concept
in	O
the	O
7400	O
series	O
.	O
</s>
<s>
The	O
first	O
electronic	O
latch	B-General_Concept
was	O
invented	O
in	O
1918	O
by	O
the	O
British	O
physicists	O
William	O
Eccles	O
and	O
F	O
.	O
W	O
.	O
Jordan	O
.	O
</s>
<s>
The	O
design	O
was	O
used	O
in	O
the	O
1943	O
British	O
Colossus	B-Device
codebreaking	I-Device
computer	I-Device
and	O
such	O
circuits	O
and	O
their	O
transistorized	O
versions	O
were	O
common	O
in	O
computers	O
even	O
after	O
the	O
introduction	O
of	O
integrated	O
circuits	O
,	O
though	O
latches	B-General_Concept
and	O
flip-flops	B-General_Concept
made	O
from	O
logic	O
gates	O
are	O
also	O
common	O
now	O
.	O
</s>
<s>
Early	O
latches	B-General_Concept
were	O
known	O
variously	O
as	O
trigger	O
circuits	O
or	O
multivibrators	O
.	O
</s>
<s>
According	O
to	O
P	O
.	O
L	O
.	O
Lindley	O
,	O
an	O
engineer	O
at	O
the	O
US	O
Jet	O
Propulsion	O
Laboratory	O
,	O
the	O
flip-flop	B-General_Concept
types	O
detailed	O
below	O
(	O
SR	O
,	O
D	O
,	O
T	O
,	O
JK	O
)	O
were	O
first	O
discussed	O
in	O
a	O
1954	O
UCLA	O
course	O
on	O
computer	O
design	O
by	O
Montgomery	O
Phister	O
,	O
and	O
then	O
appeared	O
in	O
his	O
book	O
Logical	O
Design	O
of	O
Digital	O
Computers	O
.	O
</s>
<s>
Lindley	O
was	O
at	O
the	O
time	O
working	O
at	O
Hughes	O
Aircraft	O
under	O
Eldred	O
Nelson	O
,	O
who	O
had	O
coined	O
the	O
term	O
JK	O
for	O
a	O
flip-flop	B-General_Concept
which	O
changed	O
states	O
when	O
both	O
inputs	O
were	O
on	O
(	O
a	O
logical	O
"	O
one	O
"	O
)	O
.	O
</s>
<s>
Lindley	O
explains	O
that	O
he	O
heard	O
the	O
story	O
of	O
the	O
JK	O
flip-flop	B-General_Concept
from	O
Eldred	O
Nelson	O
,	O
who	O
is	O
responsible	O
for	O
coining	O
the	O
term	O
while	O
working	O
at	O
Hughes	O
Aircraft	O
.	O
</s>
<s>
Flip-flops	B-General_Concept
in	O
use	O
at	O
Hughes	O
at	O
the	O
time	O
were	O
all	O
of	O
the	O
type	O
that	O
came	O
to	O
be	O
known	O
as	O
J-K	O
.	O
</s>
<s>
In	O
designing	O
a	O
logical	O
system	O
,	O
Nelson	O
assigned	O
letters	O
to	O
flip-flop	B-General_Concept
inputs	O
as	O
follows	O
:	O
#1	O
:	O
A	O
&	O
B	O
,	O
#2	O
:	O
C	O
&	O
D	O
,	O
#3	O
:	O
E	O
&	O
F	O
,	O
#4	O
:	O
G	O
&	O
H	O
,	O
#5	O
:	O
J	O
&	O
K	O
.	O
Nelson	O
used	O
the	O
notations	O
"	O
j-input	O
"	O
and	O
"	O
k-input	O
"	O
in	O
a	O
patent	O
application	O
filed	O
in	O
1953	O
.	O
</s>
<s>
Transparent	O
or	O
asynchronous	O
latches	B-General_Concept
can	O
be	O
built	O
around	O
a	O
single	O
pair	O
of	O
cross-coupled	O
inverting	O
elements	O
:	O
vacuum	O
tubes	O
,	O
bipolar	O
transistors	O
,	O
field	O
effect	O
transistors	O
,	O
inverters	O
,	O
and	O
inverting	O
logic	O
gates	O
have	O
all	O
been	O
used	O
in	O
practical	O
circuits	O
.	O
</s>
<s>
Clocked	O
flip-flops	B-General_Concept
are	O
specially	O
designed	O
for	O
synchronous	B-Application
systems	I-Application
;	O
such	O
devices	O
ignore	O
their	O
inputs	O
except	O
at	O
the	O
transition	O
of	O
a	O
dedicated	O
clock	O
signal	O
(	O
known	O
as	O
clocking	O
,	O
pulsing	O
,	O
or	O
strobing	O
)	O
.	O
</s>
<s>
Clocking	O
causes	O
the	O
flip-flop	B-General_Concept
either	O
to	O
change	O
or	O
to	O
retain	O
its	O
output	O
signal	O
based	O
upon	O
the	O
values	O
of	O
the	O
input	O
signals	O
at	O
the	O
transition	O
.	O
</s>
<s>
Some	O
flip-flops	B-General_Concept
change	O
output	O
on	O
the	O
rising	O
edge	O
of	O
the	O
clock	O
,	O
others	O
on	O
the	O
falling	O
edge	O
.	O
</s>
<s>
Flip-flops	B-General_Concept
and	O
latches	B-General_Concept
can	O
be	O
divided	O
into	O
common	O
types	O
:	O
the	O
SR	O
(	O
"	O
set-reset	O
"	O
)	O
,	O
D	O
(	O
"	O
data	O
"	O
or	O
"	O
delay	O
"	O
)	O
,	O
T	O
(	O
"	O
toggle	O
"	O
)	O
,	O
and	O
JK	O
.	O
</s>
<s>
When	O
using	O
static	O
gates	O
as	O
building	O
blocks	O
,	O
the	O
most	O
fundamental	O
latch	B-General_Concept
is	O
the	O
simple	O
SR	O
latch	B-General_Concept
,	O
where	O
S	O
and	O
R	O
stand	O
for	O
set	O
and	O
reset	O
.	O
</s>
<s>
While	O
the	O
R	O
and	O
S	O
inputs	O
are	O
both	O
low	O
,	O
feedback	O
maintains	O
the	O
Q	O
and	O
outputs	O
in	O
a	O
constant	O
state	B-Application
,	O
with	O
the	O
complement	O
of	O
Q	O
.	O
</s>
<s>
The	O
R	O
=	O
S	O
=	O
1	O
combination	O
is	O
called	O
a	O
restricted	O
combination	O
or	O
a	O
forbidden	O
state	B-Application
because	O
,	O
as	O
both	O
NOR	O
gates	O
then	O
output	O
zeros	O
,	O
it	O
breaks	O
the	O
logical	O
equation	O
Q	O
=	O
not	O
.	O
</s>
<s>
The	O
output	O
would	O
lock	O
at	O
either	O
1	O
or	O
0	O
depending	O
on	O
the	O
propagation	O
time	O
relations	O
between	O
the	O
gates	O
(	O
a	O
race	B-Operating_System
condition	I-Operating_System
)	O
.	O
</s>
<s>
This	O
is	O
done	O
in	O
nearly	O
every	O
programmable	B-Architecture
logic	I-Architecture
controller	I-Architecture
.	O
</s>
<s>
The	O
result	O
is	O
the	O
JK	O
latch	B-General_Concept
.	O
</s>
<s>
The	O
characteristic	O
equation	O
for	O
the	O
SR	O
latch	B-General_Concept
is	O
:	O
</s>
<s>
The	O
circuit	O
shown	O
below	O
is	O
a	O
basic	O
NAND	O
latch	B-General_Concept
.	O
</s>
<s>
The	O
circuit	O
uses	O
feedback	O
to	O
"	O
remember	O
"	O
and	O
retain	O
its	O
logical	O
state	B-Application
even	O
after	O
the	O
controlling	O
input	O
signals	O
have	O
changed	O
.	O
</s>
<s>
When	O
the	O
S	O
and	O
R	O
inputs	O
are	O
both	O
high	O
,	O
feedback	O
maintains	O
the	O
Q	O
outputs	O
to	O
the	O
previous	O
state	B-Application
.	O
</s>
<s>
From	O
a	O
teaching	O
point	O
of	O
view	O
,	O
SR	B-General_Concept
latches	I-General_Concept
drawn	O
as	O
a	O
pair	O
of	O
cross-coupled	O
components	O
(	O
transistors	O
,	O
gates	O
,	O
tubes	O
,	O
etc	O
.	O
)	O
</s>
<s>
A	O
didactically	O
easier	O
to	O
understand	O
way	O
is	O
to	O
draw	O
the	O
latch	B-General_Concept
as	O
a	O
single	O
feedback	O
loop	O
instead	O
of	O
the	O
cross-coupling	O
.	O
</s>
<s>
The	O
following	O
is	O
an	O
SR	O
latch	B-General_Concept
built	O
with	O
an	O
AND	O
gate	O
with	O
one	O
inverted	O
input	O
and	O
an	O
OR	O
gate	O
.	O
</s>
<s>
Note	O
that	O
the	O
inverter	O
is	O
not	O
needed	O
for	O
the	O
latch	B-General_Concept
functionality	O
,	O
but	O
rather	O
to	O
make	O
both	O
inputs	O
High-active	O
.	O
</s>
<s>
Note	O
that	O
the	O
SR	O
AND-OR	O
latch	B-General_Concept
has	O
the	O
benefit	O
that	O
S	O
=	O
1	O
,	O
R	O
=	O
1	O
is	O
well	O
defined	O
.	O
</s>
<s>
In	O
above	O
version	O
of	O
the	O
SR	O
AND-OR	O
latch	B-General_Concept
it	O
gives	O
priority	O
to	O
the	O
R	O
signal	O
over	O
the	O
S	O
signal	O
.	O
</s>
<s>
The	O
SR	O
AND-OR	O
latch	B-General_Concept
is	O
easier	O
to	O
understand	O
,	O
because	O
both	O
gates	O
can	O
be	O
explained	O
in	O
isolation	O
.	O
</s>
<s>
And	O
since	O
the	O
output	O
Q	O
is	O
directly	O
connected	O
to	O
the	O
output	O
of	O
the	O
AND	O
gate	O
,	O
R	O
has	O
priority	O
over	O
S	O
.	O
Latches	B-General_Concept
drawn	O
as	O
cross-coupled	O
gates	O
may	O
look	O
less	O
intuitive	O
,	O
as	O
the	O
behaviour	O
of	O
one	O
gate	O
appears	O
to	O
be	O
intertwined	O
with	O
the	O
other	O
gate	O
.	O
</s>
<s>
Note	O
that	O
the	O
SR	O
AND-OR	O
latch	B-General_Concept
can	O
be	O
transformed	O
into	O
the	O
SR	O
NOR	O
latch	B-General_Concept
using	O
logic	O
transformations	O
:	O
inverting	O
the	O
output	O
of	O
the	O
OR	O
gate	O
and	O
also	O
the	O
2nd	O
input	O
of	O
the	O
AND	O
gate	O
and	O
connecting	O
the	O
inverted	O
Q	O
output	O
between	O
these	O
two	O
added	O
inverters	O
;	O
with	O
the	O
AND	O
gate	O
with	O
both	O
inputs	O
inverted	O
being	O
equivalent	O
to	O
a	O
NOR	O
gate	O
according	O
to	O
De	O
Morgan	O
's	O
laws	O
.	O
</s>
<s>
The	O
JK	O
latch	B-General_Concept
is	O
much	O
less	O
frequently	O
used	O
than	O
the	O
JK	O
flip-flop	B-General_Concept
.	O
</s>
<s>
The	O
JK	O
latch	B-General_Concept
follows	O
the	O
following	O
state	B-Application
table	I-Application
:	O
</s>
<s>
Hence	O
,	O
the	O
JK	O
latch	B-General_Concept
is	O
an	O
SR	O
latch	B-General_Concept
that	O
is	O
made	O
to	O
toggle	O
its	O
output	O
(	O
oscillate	O
between	O
0	O
and	O
1	O
)	O
when	O
passed	O
the	O
input	O
combination	O
of	O
11	O
.	O
</s>
<s>
Unlike	O
the	O
JK	O
flip-flop	B-General_Concept
,	O
the	O
11	O
input	O
combination	O
for	O
the	O
JK	O
latch	B-General_Concept
is	O
not	O
very	O
useful	O
because	O
there	O
is	O
no	O
clock	O
that	O
directs	O
toggling	O
.	O
</s>
<s>
Latches	B-General_Concept
are	O
designed	O
to	O
be	O
transparent	O
.	O
</s>
<s>
Additional	O
logic	O
can	O
be	O
added	O
to	O
a	O
simple	O
transparent	O
latch	B-General_Concept
to	O
make	O
it	O
non-transparent	O
or	O
opaque	O
when	O
another	O
input	O
(	O
an	O
"	O
enable	O
"	O
input	O
)	O
is	O
not	O
asserted	O
.	O
</s>
<s>
When	O
several	O
transparent	O
latches	B-General_Concept
follow	O
each	O
other	O
,	O
using	O
the	O
same	O
enable	O
signal	O
,	O
signals	O
can	O
propagate	O
through	O
all	O
of	O
them	O
at	O
once	O
.	O
</s>
<s>
However	O
,	O
following	O
a	O
transparent-high	O
latch	B-General_Concept
by	O
a	O
transparent-low	O
latch	B-General_Concept
(	O
or	O
vice-versa	O
)	O
causes	O
the	O
state	B-Application
and	O
output	O
to	O
only	O
change	O
on	O
clock	O
edges	O
,	O
forming	O
what	O
is	O
called	O
a	O
master	O
–	O
slave	O
flip-flop	B-General_Concept
.	O
</s>
<s>
A	O
gated	O
SR	O
latch	B-General_Concept
can	O
be	O
made	O
by	O
adding	O
a	O
second	O
level	O
of	O
NAND	O
gates	O
to	O
the	O
inverted	O
SR	O
latch	B-General_Concept
(	O
or	O
a	O
second	O
level	O
of	O
AND	O
gates	O
to	O
the	O
direct	O
SR	O
latch	B-General_Concept
)	O
.	O
</s>
<s>
The	O
extra	O
NAND	O
gates	O
further	O
invert	O
the	O
inputs	O
so	O
latch	B-General_Concept
becomes	O
a	O
gated	O
SR	O
latch	B-General_Concept
(	O
and	O
a	O
SR	O
latch	B-General_Concept
would	O
transform	O
into	O
a	O
gated	O
latch	B-General_Concept
with	O
inverted	O
enable	O
)	O
.	O
</s>
<s>
With	O
E	O
high	O
(	O
enable	O
true	O
)	O
,	O
the	O
signals	O
can	O
pass	O
through	O
the	O
input	O
gates	O
to	O
the	O
encapsulated	O
latch	B-General_Concept
;	O
all	O
signal	O
combinations	O
except	O
for	O
(	O
0	O
,	O
0	O
)	O
=	O
hold	O
then	O
immediately	O
reproduce	O
on	O
the	O
(	O
Q	O
,	O
)	O
output	O
,	O
i.e.	O
</s>
<s>
the	O
latch	B-General_Concept
is	O
transparent	O
.	O
</s>
<s>
With	O
E	O
low	O
(	O
enable	O
false	O
)	O
the	O
latch	B-General_Concept
is	O
closed	O
(	O
opaque	O
)	O
and	O
remains	O
in	O
the	O
state	B-Application
it	O
was	O
left	O
the	O
last	O
time	O
E	O
was	O
high	O
.	O
</s>
<s>
When	O
the	O
enable	O
input	O
is	O
a	O
clock	O
signal	O
,	O
the	O
latch	B-General_Concept
is	O
said	O
to	O
be	O
level-sensitive	O
(	O
to	O
the	O
level	O
of	O
the	O
clock	O
signal	O
)	O
,	O
as	O
opposed	O
to	O
edge-sensitive	O
like	O
flip-flops	B-General_Concept
below	O
.	O
</s>
<s>
This	O
latch	B-General_Concept
exploits	O
the	O
fact	O
that	O
,	O
in	O
the	O
two	O
active	O
input	O
combinations	O
(	O
01	O
and	O
10	O
)	O
of	O
a	O
gated	O
SR	O
latch	B-General_Concept
,	O
R	O
is	O
the	O
complement	O
of	O
S	O
.	O
The	O
input	O
NAND	O
stage	O
converts	O
the	O
two	O
D	O
input	O
states	O
(	O
0	O
and	O
1	O
)	O
to	O
these	O
two	O
input	O
combinations	O
for	O
the	O
next	O
latch	B-General_Concept
by	O
inverting	O
the	O
data	O
input	O
signal	O
.	O
</s>
<s>
The	O
low	O
state	B-Application
of	O
the	O
enable	O
signal	O
produces	O
the	O
inactive	O
"	O
11	O
"	O
combination	O
.	O
</s>
<s>
Thus	O
a	O
gated	O
D-latch	O
may	O
be	O
considered	O
as	O
a	O
one-input	O
synchronous	O
SR	O
latch	B-General_Concept
.	O
</s>
<s>
It	O
is	O
also	O
known	O
as	O
transparent	O
latch	B-General_Concept
,	O
data	O
latch	B-General_Concept
,	O
or	O
simply	O
gated	O
latch	B-General_Concept
.	O
</s>
<s>
The	O
word	O
transparent	O
comes	O
from	O
the	O
fact	O
that	O
,	O
when	O
the	O
enable	O
input	O
is	O
on	O
,	O
the	O
signal	O
propagates	O
directly	O
through	O
the	O
circuit	O
,	O
from	O
the	O
input	O
D	O
to	O
the	O
output	O
Q	O
.	O
Gated	O
D-latches	O
are	O
also	O
level-sensitive	O
with	O
respect	O
to	O
the	O
level	O
of	O
the	O
clock	O
or	O
enable	O
signal	O
.	O
</s>
<s>
Transparent	O
latches	B-General_Concept
are	O
typically	O
used	O
as	O
I/O	O
ports	O
or	O
in	O
asynchronous	O
systems	O
,	O
or	O
in	O
synchronous	O
two-phase	O
systems	O
(	O
synchronous	B-Application
systems	I-Application
that	O
use	O
a	O
two-phase	O
clock	O
)	O
,	O
where	O
two	O
latches	B-General_Concept
operating	O
on	O
different	O
clock	O
phases	O
prevent	O
data	O
transparency	O
as	O
in	O
a	O
master	O
–	O
slave	O
flip-flop	B-General_Concept
.	O
</s>
<s>
The	O
classic	O
gated	O
latch	B-General_Concept
designs	O
have	O
some	O
undesirable	O
characteristics	O
.	O
</s>
<s>
A	O
successful	O
alternative	O
is	O
the	O
Earle	O
latch	B-General_Concept
.	O
</s>
<s>
In	O
addition	O
,	O
the	O
two	O
gate	O
levels	O
of	O
the	O
Earle	O
latch	B-General_Concept
can	O
,	O
in	O
some	O
cases	O
,	O
be	O
merged	O
with	O
the	O
last	O
two	O
gate	O
levels	O
of	O
the	O
circuits	O
driving	O
the	O
latch	B-General_Concept
because	O
many	O
common	O
computational	O
circuits	O
have	O
an	O
OR	O
layer	O
followed	O
by	O
an	O
AND	O
layer	O
as	O
their	O
last	O
two	O
levels	O
.	O
</s>
<s>
Merging	O
the	O
latch	B-General_Concept
function	O
can	O
implement	O
the	O
latch	B-General_Concept
with	O
no	O
additional	O
gate	O
delays	O
.	O
</s>
<s>
The	O
merge	O
is	O
commonly	O
exploited	O
in	O
the	O
design	O
of	O
pipelined	O
computers	O
,	O
and	O
,	O
in	O
fact	O
,	O
was	O
originally	O
developed	O
by	O
John	O
G	O
.	O
Earle	O
to	O
be	O
used	O
in	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
for	O
that	O
purpose	O
.	O
</s>
<s>
The	O
Earle	O
latch	B-General_Concept
is	O
hazard	O
free	O
.	O
</s>
<s>
If	O
the	O
middle	O
NAND	O
gate	O
is	O
omitted	O
,	O
then	O
one	O
gets	O
the	O
polarity	O
hold	O
latch	B-General_Concept
,	O
which	O
is	O
commonly	O
used	O
because	O
it	O
demands	O
less	O
logic	O
.	O
</s>
<s>
The	O
D	O
flip-flop	B-General_Concept
is	O
widely	O
used	O
.	O
</s>
<s>
It	O
is	O
also	O
known	O
as	O
a	O
"	O
data	O
"	O
or	O
"	O
delay	O
"	O
flip-flop	B-General_Concept
.	O
</s>
<s>
The	O
D	O
flip-flop	B-General_Concept
captures	O
the	O
value	O
of	O
the	O
D-input	O
at	O
a	O
definite	O
portion	O
of	O
the	O
clock	O
cycle	O
(	O
such	O
as	O
the	O
rising	O
edge	O
of	O
the	O
clock	O
)	O
.	O
</s>
<s>
The	O
D	O
flip-flop	B-General_Concept
can	O
be	O
viewed	O
as	O
a	O
memory	O
cell	O
,	O
a	O
zero-order	O
hold	O
,	O
or	O
a	O
delay	O
line	O
.	O
</s>
<s>
Most	O
D-type	O
flip-flops	B-General_Concept
in	O
ICs	O
have	O
the	O
capability	O
to	O
be	O
forced	O
to	O
the	O
set	O
or	O
reset	O
state	B-Application
(	O
which	O
ignores	O
the	O
D	O
and	O
clock	O
inputs	O
)	O
,	O
much	O
like	O
an	O
SR	O
flip-flop	B-General_Concept
.	O
</s>
<s>
Usually	O
,	O
the	O
illegal	O
S	O
=	O
R	O
=	O
1	O
condition	O
is	O
resolved	O
in	O
D-type	O
flip-flops	B-General_Concept
.	O
</s>
<s>
Setting	O
S	O
=	O
R	O
=	O
0	O
makes	O
the	O
flip-flop	B-General_Concept
behave	O
as	O
described	O
above	O
.	O
</s>
<s>
These	O
flip-flops	B-General_Concept
are	O
very	O
useful	O
,	O
as	O
they	O
form	O
the	O
basis	O
for	O
shift	B-General_Concept
registers	I-General_Concept
,	O
which	O
are	O
an	O
essential	O
part	O
of	O
many	O
electronic	O
devices	O
.	O
</s>
<s>
The	O
advantage	O
of	O
the	O
D	O
flip-flop	B-General_Concept
over	O
the	O
D-type	O
"	O
transparent	O
latch	B-General_Concept
"	O
is	O
that	O
the	O
signal	O
on	O
the	O
D	O
input	O
pin	O
is	O
captured	O
the	O
moment	O
the	O
flip-flop	B-General_Concept
is	O
clocked	O
,	O
and	O
subsequent	O
changes	O
on	O
the	O
D	O
input	O
will	O
be	O
ignored	O
until	O
the	O
next	O
clock	O
event	O
.	O
</s>
<s>
An	O
exception	O
is	O
that	O
some	O
flip-flops	B-General_Concept
have	O
a	O
"	O
reset	O
"	O
signal	O
input	O
,	O
which	O
will	O
reset	O
Q	O
(	O
to	O
zero	O
)	O
,	O
and	O
may	O
be	O
either	O
asynchronous	O
or	O
synchronous	O
with	O
the	O
clock	O
.	O
</s>
<s>
This	O
circuit	O
consists	O
of	O
two	O
stages	O
implemented	O
by	O
NAND	O
latches	B-General_Concept
.	O
</s>
<s>
The	O
input	O
stage	O
(	O
the	O
two	O
latches	B-General_Concept
on	O
the	O
left	O
)	O
processes	O
the	O
clock	O
and	O
data	O
signals	O
to	O
ensure	O
correct	O
input	O
signals	O
for	O
the	O
output	O
stage	O
(	O
the	O
single	O
latch	B-General_Concept
on	O
the	O
right	O
)	O
.	O
</s>
<s>
If	O
the	O
clock	O
is	O
low	O
,	O
both	O
the	O
output	O
signals	O
of	O
the	O
input	O
stage	O
are	O
high	O
regardless	O
of	O
the	O
data	O
input	O
;	O
the	O
output	O
latch	B-General_Concept
is	O
unaffected	O
and	O
it	O
stores	O
the	O
previous	O
state	B-Application
.	O
</s>
<s>
When	O
the	O
clock	O
signal	O
changes	O
from	O
low	O
to	O
high	O
,	O
only	O
one	O
of	O
the	O
output	O
voltages	O
(	O
depending	O
on	O
the	O
data	O
signal	O
)	O
goes	O
low	O
and	O
sets/resets	O
the	O
output	O
latch	B-General_Concept
:	O
if	O
D	O
=	O
0	O
,	O
the	O
lower	O
output	O
becomes	O
low	O
;	O
if	O
D	O
=	O
1	O
,	O
the	O
upper	O
output	O
becomes	O
low	O
.	O
</s>
<s>
If	O
the	O
clock	O
signal	O
continues	O
staying	O
high	O
,	O
the	O
outputs	O
keep	O
their	O
states	O
regardless	O
of	O
the	O
data	O
input	O
and	O
force	O
the	O
output	O
latch	B-General_Concept
to	O
stay	O
in	O
the	O
corresponding	O
state	B-Application
as	O
the	O
input	O
logical	O
zero	O
(	O
of	O
the	O
output	O
stage	O
)	O
remains	O
active	O
while	O
the	O
clock	O
is	O
high	O
.	O
</s>
<s>
Hence	O
the	O
role	O
of	O
the	O
output	O
latch	B-General_Concept
is	O
to	O
store	O
the	O
data	O
only	O
while	O
the	O
clock	O
is	O
low	O
.	O
</s>
<s>
The	O
circuit	O
is	O
closely	O
related	O
to	O
the	O
gated	O
D	O
latch	B-General_Concept
as	O
both	O
the	O
circuits	O
convert	O
the	O
two	O
D	O
input	O
states	O
(	O
0	O
and	O
1	O
)	O
to	O
two	O
input	O
combinations	O
(	O
01	O
and	O
10	O
)	O
for	O
the	O
output	O
latch	B-General_Concept
by	O
inverting	O
the	O
data	O
input	O
signal	O
(	O
both	O
the	O
circuits	O
split	O
the	O
single	O
D	O
signal	O
in	O
two	O
complementary	O
and	O
signals	O
)	O
.	O
</s>
<s>
The	O
difference	O
is	O
that	O
in	O
the	O
gated	O
D	O
latch	B-General_Concept
simple	O
NAND	O
logical	O
gates	O
are	O
used	O
while	O
in	O
the	O
positive-edge-triggered	O
D	O
flip-flop	B-General_Concept
NAND	O
latches	B-General_Concept
are	O
used	O
for	O
this	O
purpose	O
.	O
</s>
<s>
The	O
role	O
of	O
these	O
latches	B-General_Concept
is	O
to	O
"	O
lock	O
"	O
the	O
active	O
output	O
producing	O
low	O
voltage	O
(	O
a	O
logical	O
zero	O
)	O
;	O
thus	O
the	O
positive-edge-triggered	O
D	O
flip-flop	B-General_Concept
can	O
also	O
be	O
thought	O
of	O
as	O
a	O
gated	O
D	O
latch	B-General_Concept
with	O
latched	O
input	O
gates	O
.	O
</s>
<s>
A	O
master	O
–	O
slave	O
D	O
flip-flop	B-General_Concept
is	O
created	O
by	O
connecting	O
two	O
gated	O
D	O
latches	B-General_Concept
in	O
series	O
,	O
and	O
inverting	O
the	O
enable	O
input	O
to	O
one	O
of	O
them	O
.	O
</s>
<s>
It	O
is	O
called	O
master	O
–	O
slave	O
because	O
the	O
master	O
latch	B-General_Concept
controls	O
the	O
slave	O
latch	B-General_Concept
's	O
output	O
value	O
Q	O
and	O
forces	O
the	O
slave	O
latch	B-General_Concept
to	O
hold	O
its	O
value	O
whenever	O
the	O
slave	O
latch	B-General_Concept
is	O
enabled	O
,	O
as	O
the	O
slave	O
latch	B-General_Concept
always	O
copies	O
its	O
new	O
value	O
from	O
the	O
master	O
latch	B-General_Concept
and	O
changes	O
its	O
value	O
only	O
in	O
response	O
to	O
a	O
change	O
in	O
the	O
value	O
of	O
the	O
master	O
latch	B-General_Concept
and	O
clock	O
signal	O
.	O
</s>
<s>
For	O
a	O
positive-edge	O
triggered	O
master	O
–	O
slave	O
D	O
flip-flop	B-General_Concept
,	O
when	O
the	O
clock	O
signal	O
is	O
low	O
(	O
logical	O
0	O
)	O
the	O
"	O
enable	O
"	O
seen	O
by	O
the	O
first	O
or	O
"	O
master	O
"	O
D	O
latch	B-General_Concept
(	O
the	O
inverted	O
clock	O
signal	O
)	O
is	O
high	O
(	O
logical	O
1	O
)	O
.	O
</s>
<s>
This	O
allows	O
the	O
"	O
master	O
"	O
latch	B-General_Concept
to	O
store	O
the	O
input	O
value	O
when	O
the	O
clock	O
signal	O
transitions	O
from	O
low	O
to	O
high	O
.	O
</s>
<s>
As	O
the	O
clock	O
signal	O
goes	O
high	O
(	O
0	O
to	O
1	O
)	O
the	O
inverted	O
"	O
enable	O
"	O
of	O
the	O
first	O
latch	B-General_Concept
goes	O
low	O
(	O
1	O
to	O
0	O
)	O
and	O
the	O
value	O
seen	O
at	O
the	O
input	O
to	O
the	O
master	O
latch	B-General_Concept
is	O
"	O
locked	O
"	O
.	O
</s>
<s>
Nearly	O
simultaneously	O
,	O
the	O
twice	O
inverted	O
"	O
enable	O
"	O
of	O
the	O
second	O
or	O
"	O
slave	O
"	O
D	O
latch	B-General_Concept
transitions	O
from	O
low	O
to	O
high	O
(	O
0	O
to	O
1	O
)	O
with	O
the	O
clock	O
signal	O
.	O
</s>
<s>
This	O
allows	O
the	O
signal	O
captured	O
at	O
the	O
rising	O
edge	O
of	O
the	O
clock	O
by	O
the	O
now	O
"	O
locked	O
"	O
master	O
latch	B-General_Concept
to	O
pass	O
through	O
the	O
"	O
slave	O
"	O
latch	B-General_Concept
.	O
</s>
<s>
When	O
the	O
clock	O
signal	O
returns	O
to	O
low	O
(	O
1	O
to	O
0	O
)	O
,	O
the	O
output	O
of	O
the	O
"	O
slave	O
"	O
latch	B-General_Concept
is	O
"	O
locked	O
"	O
,	O
and	O
the	O
value	O
seen	O
at	O
the	O
last	O
rising	O
edge	O
of	O
the	O
clock	O
is	O
held	O
while	O
the	O
"	O
master	O
"	O
latch	B-General_Concept
begins	O
to	O
accept	O
new	O
values	O
in	O
preparation	O
for	O
the	O
next	O
rising	O
clock	O
edge	O
.	O
</s>
<s>
Removing	O
the	O
leftmost	O
inverter	O
in	O
the	O
circuit	O
creates	O
a	O
D-type	O
flip-flop	B-General_Concept
that	O
strobes	O
on	O
the	O
falling	O
edge	O
of	O
a	O
clock	O
signal	O
.	O
</s>
<s>
Flip-Flops	B-General_Concept
that	O
read	O
in	O
a	O
new	O
value	O
on	O
the	O
rising	O
and	O
the	O
falling	O
edge	O
of	O
the	O
clock	O
are	O
called	O
dual-edge-triggered	O
flip-flops	B-General_Concept
.	O
</s>
<s>
Such	O
a	O
flip-flop	B-General_Concept
may	O
be	O
built	O
using	O
two	O
single-edge-triggered	O
D-type	O
flip-flops	B-General_Concept
and	O
a	O
multiplexer	O
,	O
or	O
by	O
using	O
two	O
single-edge	O
triggered	O
D-type	O
flip-flops	B-General_Concept
and	O
three	O
XOR	O
gates	O
.	O
</s>
<s>
An	O
efficient	O
functional	O
alternative	O
to	O
a	O
D	O
flip-flop	B-General_Concept
can	O
be	O
made	O
with	O
dynamic	O
circuits	O
(	O
where	O
information	O
is	O
stored	O
in	O
a	O
capacitance	O
)	O
as	O
long	O
as	O
it	O
is	O
clocked	O
often	O
enough	O
;	O
while	O
not	O
a	O
true	O
flip-flop	B-General_Concept
,	O
it	O
is	O
still	O
called	O
a	O
flip-flop	B-General_Concept
for	O
its	O
functional	O
role	O
.	O
</s>
<s>
The	O
"	O
edge-triggered	O
D	O
flip-flop	B-General_Concept
"	O
,	O
as	O
it	O
is	O
called	O
even	O
though	O
it	O
is	O
not	O
a	O
true	O
flip-flop	B-General_Concept
,	O
does	O
not	O
have	O
the	O
master	O
–	O
slave	O
properties	O
.	O
</s>
<s>
Edge-triggered	O
D	O
flip-flops	B-General_Concept
are	O
often	O
implemented	O
in	O
integrated	O
high-speed	O
operations	O
using	O
dynamic	B-General_Concept
logic	I-General_Concept
.	O
</s>
<s>
This	O
design	O
of	O
dynamic	O
flip	B-General_Concept
flops	I-General_Concept
also	O
enables	O
simple	O
resetting	O
since	O
the	O
reset	O
operation	O
can	O
be	O
performed	O
by	O
simply	O
discharging	O
one	O
or	O
more	O
internal	O
nodes	O
.	O
</s>
<s>
A	O
common	O
dynamic	O
flip-flop	B-General_Concept
variety	O
is	O
the	O
true	O
single-phase	O
clock	O
(	O
TSPC	O
)	O
type	O
which	O
performs	O
the	O
flip-flop	B-General_Concept
operation	O
with	O
little	O
power	O
and	O
at	O
high	O
speeds	O
.	O
</s>
<s>
However	O
,	O
dynamic	O
flip-flops	B-General_Concept
will	O
typically	O
not	O
work	O
at	O
static	O
or	O
low	O
clock	O
speeds	O
:	O
given	O
enough	O
time	O
,	O
leakage	O
paths	O
may	O
discharge	O
the	O
parasitic	O
capacitance	O
enough	O
to	O
cause	O
the	O
flip-flop	B-General_Concept
to	O
enter	O
invalid	B-Application
states	I-Application
.	O
</s>
<s>
If	O
the	O
T	O
input	O
is	O
high	O
,	O
the	O
T	O
flip-flop	B-General_Concept
changes	O
state	B-Application
(	O
"	O
toggles	O
"	O
)	O
whenever	O
the	O
clock	O
input	O
is	O
strobed	O
.	O
</s>
<s>
If	O
the	O
T	O
input	O
is	O
low	O
,	O
the	O
flip-flop	B-General_Concept
holds	O
the	O
previous	O
value	O
.	O
</s>
<s>
When	O
T	O
is	O
held	O
high	O
,	O
the	O
toggle	O
flip-flop	B-General_Concept
divides	O
the	O
clock	O
frequency	O
by	O
two	O
;	O
that	O
is	O
,	O
if	O
clock	O
frequency	O
is	O
4MHz	O
,	O
the	O
output	O
frequency	O
obtained	O
from	O
the	O
flip-flop	B-General_Concept
will	O
be	O
2MHz	O
.	O
</s>
<s>
A	O
T	O
flip-flop	B-General_Concept
can	O
also	O
be	O
built	O
using	O
a	O
JK	O
flip-flop	B-General_Concept
(	O
J	O
&	O
K	O
pins	O
are	O
connected	O
together	O
and	O
act	O
as	O
T	O
)	O
or	O
a	O
D	O
flip-flop	B-General_Concept
(	O
T	O
input	O
XOR	O
Qprevious	O
drives	O
the	O
D	O
input	O
)	O
.	O
</s>
<s>
The	O
JK	O
flip-flop	B-General_Concept
augments	O
the	O
behavior	O
of	O
the	O
SR	O
flip-flop	B-General_Concept
(	O
J	O
:	O
Set	O
,	O
K	O
:	O
Reset	O
)	O
by	O
interpreting	O
the	O
J	O
=	O
K	O
=	O
1	O
condition	O
as	O
a	O
"	O
flip	O
"	O
or	O
toggle	O
command	O
.	O
</s>
<s>
Specifically	O
,	O
the	O
combination	O
J	O
=	O
1	O
,	O
K	O
=	O
0	O
is	O
a	O
command	O
to	O
set	O
the	O
flip-flop	B-General_Concept
;	O
the	O
combination	O
J	O
=	O
0	O
,	O
K	O
=	O
1	O
is	O
a	O
command	O
to	O
reset	O
the	O
flip-flop	B-General_Concept
;	O
and	O
the	O
combination	O
J	O
=	O
K	O
=	O
1	O
is	O
a	O
command	O
to	O
toggle	O
the	O
flip-flop	B-General_Concept
,	O
i.e.	O
,	O
change	O
its	O
output	O
to	O
the	O
logical	O
complement	O
of	O
its	O
current	O
value	O
.	O
</s>
<s>
Setting	O
J	O
=	O
K	O
=	O
0	O
maintains	O
the	O
current	O
state	B-Application
.	O
</s>
<s>
To	O
synthesize	O
a	O
D	O
flip-flop	B-General_Concept
,	O
simply	O
set	O
K	O
equal	O
to	O
the	O
complement	O
of	O
J	O
(	O
input	O
J	O
will	O
act	O
as	O
input	O
D	O
)	O
.	O
</s>
<s>
Similarly	O
,	O
to	O
synthesize	O
a	O
T	O
flip-flop	B-General_Concept
,	O
set	O
K	O
equal	O
to	O
J	O
.	O
</s>
<s>
The	O
JK	O
flip-flop	B-General_Concept
is	O
therefore	O
a	O
universal	O
flip-flop	B-General_Concept
,	O
because	O
it	O
can	O
be	O
configured	O
to	O
work	O
as	O
an	O
SR	O
flip-flop	B-General_Concept
,	O
a	O
D	O
flip-flop	B-General_Concept
,	O
or	O
a	O
T	O
flip-flop	B-General_Concept
.	O
</s>
<s>
The	O
characteristic	O
equation	O
of	O
the	O
JK	O
flip-flop	B-General_Concept
is	O
:	O
</s>
<s>
If	O
you	O
take	O
a	O
picture	O
of	O
the	O
frog	O
as	O
it	O
jumps	O
into	O
the	O
water	O
,	O
you	O
will	O
get	O
a	O
blurry	O
picture	O
of	O
the	O
frog	O
jumping	O
into	O
the	O
it	O
's	O
not	O
clear	O
which	O
state	B-Application
the	O
frog	O
was	O
in	O
.	O
</s>
<s>
In	O
the	O
same	O
way	O
,	O
the	O
input	O
to	O
a	O
flip-flop	B-General_Concept
must	O
be	O
held	O
steady	O
during	O
the	O
aperture	O
of	O
the	O
flip-flop	B-General_Concept
.	O
</s>
<s>
Setup	B-General_Concept
time	I-General_Concept
is	O
the	O
minimum	O
amount	O
of	O
time	O
the	O
data	O
input	O
should	O
be	O
held	O
steady	O
before	O
the	O
clock	O
event	O
,	O
so	O
that	O
the	O
data	O
is	O
reliably	O
sampled	O
by	O
the	O
clock	O
.	O
</s>
<s>
The	O
recovery	O
time	O
for	O
the	O
asynchronous	O
set	O
or	O
reset	O
input	O
is	O
thereby	O
similar	O
to	O
the	O
setup	B-General_Concept
time	I-General_Concept
for	O
the	O
data	O
input	O
.	O
</s>
<s>
Short	O
impulses	O
applied	O
to	O
asynchronous	O
inputs	O
(	O
set	O
,	O
reset	O
)	O
should	O
not	O
be	O
applied	O
completely	O
within	O
the	O
recovery-removal	O
period	O
,	O
or	O
else	O
it	O
becomes	O
entirely	O
indeterminable	O
whether	O
the	O
flip-flop	B-General_Concept
will	O
transition	O
to	O
the	O
appropriate	O
state	B-Application
.	O
</s>
<s>
In	O
another	O
case	O
,	O
where	O
an	O
asynchronous	O
signal	O
simply	O
makes	O
one	O
transition	O
that	O
happens	O
to	O
fall	O
between	O
the	O
recovery/removal	O
time	O
,	O
eventually	O
the	O
flip-flop	B-General_Concept
will	O
transition	O
to	O
the	O
appropriate	O
state	B-Application
,	O
but	O
a	O
very	O
short	O
glitch	O
may	O
or	O
may	O
not	O
appear	O
on	O
the	O
output	O
,	O
dependent	O
on	O
the	O
synchronous	O
input	O
signal	O
.	O
</s>
<s>
Set	O
and	O
Reset	O
(	O
and	O
other	O
)	O
signals	O
may	O
be	O
either	O
synchronous	O
or	O
asynchronous	O
and	O
therefore	O
may	O
be	O
characterized	O
with	O
either	O
Setup/Hold	O
or	O
Recovery/Removal	O
times	O
,	O
and	O
synchronicity	O
is	O
very	O
dependent	O
on	O
the	O
design	O
of	O
the	O
flip-flop	B-General_Concept
.	O
</s>
<s>
Flip-flops	B-General_Concept
are	O
subject	O
to	O
a	O
problem	O
called	O
metastability	O
,	O
which	O
can	O
happen	O
when	O
two	O
inputs	O
,	O
such	O
as	O
data	O
and	O
clock	O
or	O
clock	O
and	O
reset	O
,	O
are	O
changing	O
at	O
about	O
the	O
same	O
time	O
.	O
</s>
<s>
When	O
the	O
order	O
is	O
not	O
clear	O
,	O
within	O
appropriate	O
timing	O
constraints	O
,	O
the	O
result	O
is	O
that	O
the	O
output	O
may	O
behave	O
unpredictably	O
,	O
taking	O
many	O
times	O
longer	O
than	O
normal	O
to	O
settle	O
to	O
one	O
state	B-Application
or	O
the	O
other	O
,	O
or	O
even	O
oscillating	O
several	O
times	O
before	O
settling	O
.	O
</s>
<s>
In	O
a	O
computer	O
system	O
,	O
this	O
metastability	O
can	O
cause	O
corruption	O
of	O
data	O
or	O
a	O
program	O
crash	O
if	O
the	O
state	B-Application
is	O
not	O
stable	O
before	O
another	O
circuit	O
uses	O
its	O
value	O
;	O
in	O
particular	O
,	O
if	O
two	O
different	O
logical	O
paths	O
use	O
the	O
output	O
of	O
a	O
flip-flop	B-General_Concept
,	O
one	O
path	O
can	O
interpret	O
it	O
as	O
a	O
0	O
and	O
the	O
other	O
as	O
a	O
1	O
when	O
it	O
has	O
not	O
resolved	O
to	O
stable	O
state	B-Application
,	O
putting	O
the	O
machine	O
into	O
an	O
inconsistent	O
state	B-Application
.	O
</s>
<s>
The	O
metastability	O
in	O
flip-flops	B-General_Concept
can	O
be	O
avoided	O
by	O
ensuring	O
that	O
the	O
data	O
and	O
control	O
inputs	O
are	O
held	O
valid	O
and	O
constant	O
for	O
specified	O
periods	O
before	O
and	O
after	O
the	O
clock	O
pulse	O
,	O
called	O
the	O
setup	B-General_Concept
time	I-General_Concept
(	O
tsu	O
)	O
and	O
the	O
hold	O
time	O
(	O
th	O
)	O
respectively	O
.	O
</s>
<s>
Depending	O
upon	O
the	O
flip-flop	B-General_Concept
'	O
s	O
internal	O
organization	O
,	O
it	O
is	O
possible	O
to	O
build	O
a	O
device	O
with	O
a	O
zero	O
(	O
or	O
even	O
negative	O
)	O
setup	O
or	O
hold	O
time	O
requirement	O
but	O
not	O
both	O
simultaneously	O
.	O
</s>
<s>
Unfortunately	O
,	O
it	O
is	O
not	O
always	O
possible	O
to	O
meet	O
the	O
setup	O
and	O
hold	O
criteria	O
,	O
because	O
the	O
flip-flop	B-General_Concept
may	O
be	O
connected	O
to	O
a	O
real-time	O
signal	O
that	O
could	O
change	O
at	O
any	O
time	O
,	O
outside	O
the	O
control	O
of	O
the	O
designer	O
.	O
</s>
<s>
One	O
technique	O
for	O
suppressing	O
metastability	O
is	O
to	O
connect	O
two	O
or	O
more	O
flip-flops	B-General_Concept
in	O
a	O
chain	O
,	O
so	O
that	O
the	O
output	O
of	O
each	O
one	O
feeds	O
the	O
data	O
input	O
of	O
the	O
next	O
,	O
and	O
all	O
devices	O
share	O
a	O
common	O
clock	O
.	O
</s>
<s>
The	O
probability	O
of	O
metastability	O
gets	O
closer	O
and	O
closer	O
to	O
zero	O
as	O
the	O
number	O
of	O
flip-flops	B-General_Concept
connected	O
in	O
series	O
is	O
increased	O
.	O
</s>
<s>
The	O
number	O
of	O
flip-flops	B-General_Concept
being	O
cascaded	O
is	O
referred	O
to	O
as	O
the	O
"	O
ranking	O
"	O
;	O
"	O
dual-ranked	O
"	O
flip	B-General_Concept
flops	I-General_Concept
(	O
two	O
flip-flops	B-General_Concept
in	O
series	O
)	O
is	O
a	O
common	O
situation	O
.	O
</s>
<s>
So-called	O
metastable-hardened	O
flip-flops	B-General_Concept
are	O
available	O
,	O
which	O
work	O
by	O
reducing	O
the	O
setup	O
and	O
hold	O
times	O
as	O
much	O
as	O
possible	O
,	O
but	O
even	O
these	O
cannot	O
eliminate	O
the	O
problem	O
entirely	O
.	O
</s>
<s>
When	O
the	O
transitions	O
in	O
the	O
clock	O
and	O
the	O
data	O
are	O
close	O
together	O
in	O
time	O
,	O
the	O
flip-flop	B-General_Concept
is	O
forced	O
to	O
decide	O
which	O
event	O
happened	O
first	O
.	O
</s>
<s>
It	O
is	O
therefore	O
logically	O
impossible	O
to	O
build	O
a	O
perfectly	O
metastable-proof	O
flip-flop	B-General_Concept
.	O
</s>
<s>
Flip-flops	B-General_Concept
are	O
sometimes	O
characterized	O
for	O
a	O
maximum	O
settling	O
time	O
(	O
the	O
maximum	O
time	O
they	O
will	O
remain	O
metastable	O
under	O
specified	O
conditions	O
)	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
dual-ranked	O
flip-flops	B-General_Concept
that	O
are	O
clocked	O
slower	O
than	O
the	O
maximum	O
allowed	O
metastability	O
time	O
will	O
provide	O
proper	O
conditioning	O
for	O
asynchronous	O
(	O
e.g.	O
,	O
external	O
)	O
signals	O
.	O
</s>
<s>
Another	O
important	O
timing	O
value	O
for	O
a	O
flip-flop	B-General_Concept
is	O
the	O
clock-to-output	O
delay	O
(	O
common	O
symbol	O
in	O
data	O
sheets	O
:	O
tCO	O
)	O
or	O
propagation	O
delay	O
(	O
tP	O
)	O
,	O
which	O
is	O
the	O
time	O
a	O
flip-flop	B-General_Concept
takes	O
to	O
change	O
its	O
output	O
after	O
the	O
clock	O
edge	O
.	O
</s>
<s>
When	O
cascading	O
flip-flops	B-General_Concept
which	O
share	O
the	O
same	O
clock	O
(	O
as	O
in	O
a	O
shift	B-General_Concept
register	I-General_Concept
)	O
,	O
it	O
is	O
important	O
to	O
ensure	O
that	O
the	O
tCO	O
of	O
a	O
preceding	O
flip-flop	B-General_Concept
is	O
longer	O
than	O
the	O
hold	O
time	O
(	O
th	O
)	O
of	O
the	O
following	O
flip-flop	B-General_Concept
,	O
so	O
data	O
present	O
at	O
the	O
input	O
of	O
the	O
succeeding	O
flip-flop	B-General_Concept
is	O
properly	O
"	O
shifted	O
in	O
"	O
following	O
the	O
active	O
edge	O
of	O
the	O
clock	O
.	O
</s>
<s>
This	O
relationship	O
between	O
tCO	O
and	O
th	O
is	O
normally	O
guaranteed	O
if	O
the	O
flip-flops	B-General_Concept
are	O
physically	O
identical	O
.	O
</s>
<s>
Flip-flops	B-General_Concept
can	O
be	O
generalized	O
in	O
at	O
least	O
two	O
ways	O
:	O
by	O
making	O
them	O
1-of-N	O
instead	O
of	O
1-of-2	O
,	O
and	O
by	O
adapting	O
them	O
to	O
logic	O
with	O
more	O
than	O
two	O
states	O
.	O
</s>
<s>
In	O
the	O
special	O
cases	O
of	O
1-of-3	O
encoding	O
,	O
or	O
multi-valued	O
ternary	B-Language
logic	I-Language
,	O
such	O
an	O
element	O
may	O
be	O
referred	O
to	O
as	O
a	O
flip-flap-flop	O
.	O
</s>
<s>
In	O
a	O
conventional	O
flip-flop	B-General_Concept
,	O
exactly	O
one	O
of	O
the	O
two	O
complementary	O
outputs	O
is	O
high	O
.	O
</s>
<s>
The	O
construction	O
is	O
similar	O
to	O
a	O
conventional	O
cross-coupled	O
flip-flop	B-General_Concept
;	O
each	O
output	O
,	O
when	O
high	O
,	O
inhibits	O
all	O
the	O
other	O
outputs	O
.	O
</s>
<s>
Alternatively	O
,	O
more	O
or	O
less	O
conventional	O
flip-flops	B-General_Concept
can	O
be	O
used	O
,	O
one	O
per	O
output	O
,	O
with	O
additional	O
circuitry	O
to	O
make	O
sure	O
only	O
one	O
at	O
a	O
time	O
can	O
be	O
true	O
.	O
</s>
<s>
Another	O
generalization	O
of	O
the	O
conventional	O
flip-flop	B-General_Concept
is	O
a	O
memory	O
element	O
for	O
multi-valued	O
logic	O
.	O
</s>
