<s>
Flash	B-Device
memory	I-Device
is	O
an	O
electronic	O
non-volatile	B-General_Concept
computer	B-General_Concept
memory	I-General_Concept
storage	B-General_Concept
medium	I-General_Concept
that	O
can	O
be	O
electrically	O
erased	O
and	O
reprogrammed	O
.	O
</s>
<s>
The	O
two	O
main	O
types	O
of	O
flash	B-Device
memory	I-Device
,	O
NOR	O
flash	O
and	O
NAND	O
flash	O
,	O
are	O
named	O
for	O
the	O
NOR	O
and	O
NAND	O
logic	O
gates	O
.	O
</s>
<s>
Both	O
use	O
the	O
same	O
cell	B-Algorithm
design	O
,	O
consisting	O
of	O
floating	B-Algorithm
gate	I-Algorithm
MOSFETs	I-Algorithm
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
,	O
a	O
type	O
of	O
floating-gate	B-Algorithm
memory	O
,	O
was	O
invented	O
at	O
Toshiba	O
in	O
1980	O
and	O
is	O
based	O
on	O
EEPROM	B-General_Concept
technology	O
.	O
</s>
<s>
Toshiba	O
began	O
marketing	O
flash	B-Device
memory	I-Device
in	O
1987	O
.	O
</s>
<s>
EPROMs	B-General_Concept
had	O
to	O
be	O
erased	O
completely	O
before	O
they	O
could	O
be	O
rewritten	O
.	O
</s>
<s>
NAND	O
flash	B-Device
memory	I-Device
,	O
however	O
,	O
may	O
be	O
erased	O
,	O
written	O
,	O
and	O
read	O
in	O
blocks	O
(	O
or	O
pages	O
)	O
,	O
which	O
generally	O
are	O
much	O
smaller	O
than	O
the	O
entire	O
device	O
.	O
</s>
<s>
NOR	O
flash	B-Device
memory	I-Device
allows	O
a	O
single	O
machine	O
word	O
to	O
be	O
written	O
to	O
an	O
erased	O
location	O
or	O
read	O
independently	O
.	O
</s>
<s>
A	O
flash	B-Device
memory	I-Device
device	O
typically	O
consists	O
of	O
one	O
or	O
more	O
flash	B-Device
memory	I-Device
chips	O
(	O
each	O
holding	O
many	O
flash	B-Device
memory	I-Device
cells	O
)	O
,	O
along	O
with	O
a	O
separate	O
flash	B-Device
memory	I-Device
controller	I-Device
chip	O
.	O
</s>
<s>
The	O
NAND	O
type	O
is	O
found	O
mainly	O
in	O
memory	B-Device
cards	I-Device
,	O
USB	B-Protocol
flash	O
drives	O
,	O
solid-state	B-Device
drives	I-Device
(	O
those	O
produced	O
since	O
2009	O
)	O
,	O
feature	B-Device
phones	I-Device
,	O
smartphones	B-Application
,	O
and	O
similar	O
products	O
,	O
for	O
general	O
storage	O
and	O
transfer	O
of	O
data	O
.	O
</s>
<s>
NAND	O
or	O
NOR	O
flash	B-Device
memory	I-Device
is	O
also	O
often	O
used	O
to	O
store	O
configuration	O
data	O
in	O
digital	O
products	O
,	O
a	O
task	O
previously	O
made	O
possible	O
by	O
EEPROM	B-General_Concept
or	O
battery-powered	O
static	B-Architecture
RAM	I-Architecture
.	O
</s>
<s>
A	O
key	O
disadvantage	O
of	O
flash	B-Device
memory	I-Device
is	O
that	O
it	O
can	O
endure	O
only	O
a	O
relatively	O
small	O
number	O
of	O
write	O
cycles	O
in	O
a	O
specific	O
block	B-General_Concept
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
is	O
used	O
in	O
computers	O
,	O
PDAs	B-Application
,	O
digital	O
audio	O
players	O
,	O
digital	B-Device
cameras	I-Device
,	O
mobile	O
phones	O
,	O
synthesizers	O
,	O
video	O
games	O
,	O
scientific	O
instrumentation	O
,	O
industrial	O
robotics	O
,	O
and	O
medical	O
electronics	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
has	O
fast	O
read	O
access	B-General_Concept
time	I-General_Concept
,	O
but	O
it	O
is	O
not	O
as	O
fast	O
as	O
static	B-Architecture
RAM	I-Architecture
or	O
ROM	B-Device
.	O
</s>
<s>
In	O
portable	B-Application
devices	I-Application
,	O
it	O
is	O
preferred	O
to	O
use	O
flash	B-Device
memory	I-Device
because	O
of	O
its	O
mechanical	O
shock	O
resistance	O
since	O
mechanical	O
drives	O
are	O
more	O
prone	O
to	O
mechanical	O
damage	O
.	O
</s>
<s>
Because	O
erase	O
cycles	O
are	O
slow	O
,	O
the	O
large	O
block	B-General_Concept
sizes	I-General_Concept
used	O
in	O
flash	B-Device
memory	I-Device
erasing	O
give	O
it	O
a	O
significant	O
speed	O
advantage	O
over	O
non-flash	O
EEPROM	O
when	O
writing	O
large	O
amounts	O
of	O
data	O
.	O
</s>
<s>
flash	B-Device
memory	I-Device
costs	O
much	O
less	O
than	O
byte-programmable	O
EEPROM	B-General_Concept
and	O
had	O
become	O
the	O
dominant	O
memory	O
type	O
wherever	O
a	O
system	O
required	O
a	O
significant	O
amount	O
of	O
non-volatile	B-General_Concept
solid-state	B-Device
storage	I-Device
.	O
</s>
<s>
EEPROMs	B-General_Concept
,	O
however	O
,	O
are	O
still	O
used	O
in	O
applications	O
that	O
require	O
only	O
small	O
amounts	O
of	O
storage	O
,	O
as	O
in	O
serial	B-General_Concept
presence	I-General_Concept
detect	I-General_Concept
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
packages	B-Algorithm
can	O
use	O
die	B-Architecture
stacking	I-Architecture
with	O
through-silicon	B-Algorithm
vias	I-Algorithm
and	O
several	O
dozen	O
layers	O
of	O
3D	O
TLC	O
NAND	O
cells	O
(	O
per	O
die	O
)	O
simultaneously	O
to	O
achieve	O
capacities	O
of	O
up	O
to	O
1	O
tebibyte	O
per	O
package	O
using	O
16	O
stacked	O
dies	O
and	O
an	O
integrated	O
flash	B-Device
controller	I-Device
as	O
a	O
separate	O
die	O
inside	O
the	O
package	O
.	O
</s>
<s>
The	O
origins	O
of	O
flash	B-Device
memory	I-Device
can	O
be	O
traced	O
back	O
to	O
the	O
development	O
of	O
the	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
(	O
FGMOS	B-Algorithm
)	O
,	O
also	O
known	O
as	O
the	O
floating-gate	B-Algorithm
transistor	I-Algorithm
.	O
</s>
<s>
The	O
original	O
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
)	O
,	O
also	O
known	O
as	O
the	O
MOS	B-Architecture
transistor	I-Architecture
,	O
was	O
invented	O
by	O
Egyptian	O
engineer	O
Mohamed	O
M	O
.	O
Atalla	O
and	O
Korean	O
engineer	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
.	O
</s>
<s>
Kahng	O
went	O
on	O
to	O
develop	O
a	O
variation	O
,	O
the	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
,	O
with	O
Taiwanese-America	O
engineer	O
Simon	O
Min	O
Sze	O
at	O
Bell	O
Labs	O
in	O
1967	O
.	O
</s>
<s>
They	O
proposed	O
that	O
it	O
could	O
be	O
used	O
as	O
floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
for	O
storing	O
a	O
form	O
of	O
programmable	B-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
(	O
PROM	B-General_Concept
)	O
that	O
is	O
both	O
non-volatile	B-General_Concept
and	O
re-programmable	O
.	O
</s>
<s>
Early	O
types	O
of	O
floating-gate	B-Algorithm
memory	O
included	O
EPROM	B-General_Concept
(	O
erasable	O
PROM	B-General_Concept
)	O
and	O
EEPROM	B-General_Concept
(	O
electrically	O
erasable	O
PROM	B-General_Concept
)	O
in	O
the	O
1970s	O
.	O
</s>
<s>
However	O
,	O
early	O
floating-gate	B-Algorithm
memory	O
required	O
engineers	O
to	O
build	O
a	O
memory	B-Algorithm
cell	I-Algorithm
for	O
each	O
bit	O
of	O
data	O
,	O
which	O
proved	O
to	O
be	O
cumbersome	O
,	O
slow	O
,	O
and	O
expensive	O
,	O
restricting	O
floating-gate	B-Algorithm
memory	O
to	O
niche	O
applications	O
in	O
the	O
1970s	O
,	O
such	O
as	O
military	O
equipment	O
and	O
the	O
earliest	O
experimental	O
mobile	O
phones	O
.	O
</s>
<s>
Fujio	O
Masuoka	O
,	O
while	O
working	O
for	O
Toshiba	O
,	O
proposed	O
a	O
new	O
type	O
of	O
floating-gate	B-Algorithm
memory	O
that	O
allowed	O
entire	O
sections	O
of	O
memory	O
to	O
be	O
erased	O
quickly	O
and	O
easily	O
,	O
by	O
applying	O
a	O
voltage	O
to	O
a	O
single	O
wire	O
connected	O
to	O
a	O
group	O
of	O
cells	O
.	O
</s>
<s>
This	O
led	O
to	O
Masuoka	O
's	O
invention	O
of	O
flash	B-Device
memory	I-Device
at	O
Toshiba	O
in	O
1980	O
.	O
</s>
<s>
Toshiba	O
commercially	O
launched	O
NAND	O
flash	B-Device
memory	I-Device
in	O
1987	O
.	O
</s>
<s>
Intel	O
Corporation	O
introduced	O
the	O
first	O
commercial	O
NOR	O
type	O
flash	B-Device
chip	I-Device
in	O
1988	O
.	O
</s>
<s>
NOR-based	O
flash	O
has	O
long	O
erase	O
and	O
write	O
times	O
,	O
but	O
provides	O
full	O
address	O
and	O
data	O
buses	O
,	O
allowing	O
random	B-General_Concept
access	I-General_Concept
to	O
any	O
memory	O
location	O
.	O
</s>
<s>
This	O
makes	O
it	O
a	O
suitable	O
replacement	O
for	O
older	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
chips	O
,	O
which	O
are	O
used	O
to	O
store	O
program	O
code	O
that	O
rarely	O
needs	O
to	O
be	O
updated	O
,	O
such	O
as	O
a	O
computer	O
's	O
BIOS	B-Operating_System
or	O
the	O
firmware	B-Application
of	O
set-top	O
boxes	O
.	O
</s>
<s>
Its	O
endurance	O
may	O
be	O
from	O
as	O
little	O
as	O
100	O
erase	O
cycles	O
for	O
an	O
on-chip	O
flash	B-Device
memory	I-Device
,	O
to	O
a	O
more	O
typical	O
10,000	O
or	O
100,000	O
erase	O
cycles	O
,	O
up	O
to	O
1,000,000	O
erase	O
cycles	O
.	O
</s>
<s>
NOR-based	O
flash	O
was	O
the	O
basis	O
of	O
early	O
flash-based	O
removable	O
media	O
;	O
CompactFlash	B-Device
was	O
originally	O
based	O
on	O
it	O
,	O
though	O
later	O
cards	O
moved	O
to	O
less	O
expensive	O
NANDflash	O
.	O
</s>
<s>
NAND	O
flash	O
has	O
reduced	O
erase	O
and	O
write	O
times	O
,	O
and	O
requires	O
less	O
chip	O
area	O
per	O
cell	B-Algorithm
,	O
thus	O
allowing	O
greater	O
storage	O
density	O
and	O
lower	O
cost	O
per	O
bit	O
than	O
NORflash	O
.	O
</s>
<s>
However	O
,	O
the	O
I/O	O
interface	O
of	O
NANDflash	O
does	O
not	O
provide	O
a	O
random-access	B-General_Concept
external	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Rather	O
,	O
data	O
must	O
be	O
read	O
on	O
a	O
block-wise	O
basis	O
,	O
with	O
typical	O
block	B-General_Concept
sizes	I-General_Concept
of	O
hundreds	O
to	O
thousands	O
of	O
bits	O
.	O
</s>
<s>
This	O
makes	O
NANDflash	O
unsuitable	O
as	O
a	O
drop-in	O
replacement	O
for	O
program	O
ROM	B-Device
,	O
since	O
most	O
microprocessors	O
and	O
microcontrollers	B-Architecture
require	O
byte-level	O
random	B-General_Concept
access	I-General_Concept
.	O
</s>
<s>
In	O
this	O
regard	O
,	O
NANDflash	O
is	O
similar	O
to	O
other	O
secondary	O
data	B-General_Concept
storage	I-General_Concept
devices	I-General_Concept
,	O
such	O
as	O
hard	B-Device
disks	I-Device
and	O
optical	B-Device
media	I-Device
,	O
and	O
is	O
thus	O
highly	O
suitable	O
for	O
use	O
in	O
mass-storage	O
devices	O
,	O
such	O
as	O
memory	B-Device
cards	I-Device
and	O
solid-state	B-Device
drives	I-Device
(	O
SSD	B-Device
)	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
cards	I-Device
and	O
SSDs	B-Device
store	O
data	O
using	O
multiple	O
NAND	O
flash	B-Device
memory	I-Device
chips	O
.	O
</s>
<s>
The	O
first	O
NAND-based	O
removable	O
memory	B-Device
card	I-Device
format	O
was	O
SmartMedia	B-Operating_System
,	O
released	O
in	O
1995	O
.	O
</s>
<s>
Many	O
others	O
followed	O
,	O
including	O
MultiMediaCard	O
,	O
Secure	B-Device
Digital	I-Device
,	O
Memory	O
Stick	O
,	O
and	O
xD-Picture	O
Card	O
.	O
</s>
<s>
A	O
new	O
generation	O
of	O
memory	B-Device
card	I-Device
formats	O
,	O
including	O
RS-MMC	O
,	O
miniSD	B-Device
and	O
microSD	O
,	O
feature	O
extremely	O
small	O
form	O
factors	O
.	O
</s>
<s>
Multi-level	B-Device
cell	I-Device
(	O
MLC	B-Device
)	O
technology	O
stores	O
more	O
than	O
one	O
bit	O
in	O
each	O
memory	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
NEC	O
demonstrated	O
multi-level	B-Device
cell	I-Device
(	O
MLC	B-Device
)	O
technology	O
in	O
1998	O
,	O
with	O
an	O
80Mb	O
flash	B-Device
memory	I-Device
chip	O
storing	O
2	O
bits	O
per	O
cell	B-Algorithm
.	O
</s>
<s>
STMicroelectronics	O
also	O
demonstrated	O
MLC	B-Device
in	O
2000	O
,	O
with	O
a	O
64MB	O
NOR	O
flash	B-Device
memory	I-Device
chip	O
.	O
</s>
<s>
In	O
2009	O
,	O
Toshiba	O
and	O
SanDisk	O
introduced	O
NAND	O
flash	B-Device
chips	I-Device
with	O
QLC	O
technology	O
storing	O
4	O
bits	O
per	O
cell	B-Algorithm
and	O
holding	O
a	O
capacity	O
of	O
64Gbit	O
.	O
</s>
<s>
Samsung	B-Application
Electronics	O
introduced	O
triple-level	O
cell	B-Algorithm
(	O
TLC	O
)	O
technology	O
storing	O
3-bits	O
per	O
cell	B-Algorithm
,	O
and	O
began	O
mass-producing	O
NAND	O
chips	O
with	O
TLC	O
technology	O
in	O
2010	O
.	O
</s>
<s>
Charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
(	O
CTF	O
)	O
technology	O
replaces	O
the	O
polysilicon	O
floating	B-Algorithm
gate	I-Algorithm
,	O
which	O
is	O
sandwiched	O
between	O
a	O
blocking	O
gate	O
oxide	O
above	O
and	O
a	O
tunneling	O
oxide	O
below	O
it	O
,	O
with	O
an	O
electrically	O
insulating	O
silicon	O
nitride	O
layer	O
;	O
the	O
silicon	O
nitride	O
layer	O
traps	O
electrons	O
.	O
</s>
<s>
Degradation	O
or	O
wear	O
of	O
the	O
oxides	O
is	O
the	O
reason	O
why	O
flash	B-Device
memory	I-Device
has	O
limited	O
endurance	O
,	O
and	O
data	O
retention	O
goes	O
down	O
(	O
the	O
potential	O
for	O
data	O
loss	O
increases	O
)	O
with	O
increasing	O
degradation	O
,	O
since	O
the	O
oxides	O
lose	O
their	O
electrically	O
insulating	O
characteristics	O
as	O
they	O
degrade	O
.	O
</s>
<s>
In	O
1991	O
,	O
NEC	O
researchers	O
including	O
N	O
.	O
Kodama	O
,	O
K	O
.	O
Oyama	O
and	O
Hiroki	O
Shirai	O
described	O
a	O
type	O
of	O
flash	B-Device
memory	I-Device
with	O
a	O
charge	O
trap	O
method	O
.	O
</s>
<s>
In	O
1998	O
,	O
Boaz	O
Eitan	O
of	O
Saifun	O
Semiconductors	O
(	O
later	O
acquired	O
by	O
Spansion	O
)	O
patented	O
a	O
flash	B-Device
memory	I-Device
technology	O
named	O
NROM	B-Algorithm
that	O
took	O
advantage	O
of	O
a	O
charge	O
trapping	O
layer	O
to	O
replace	O
the	O
conventional	O
floating	B-Algorithm
gate	I-Algorithm
used	O
in	O
conventional	O
flash	B-Device
memory	I-Device
designs	O
.	O
</s>
<s>
In	O
2000	O
,	O
an	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
research	O
team	O
led	O
by	O
Richard	O
M	O
.	O
Fastow	O
,	O
Egyptian	O
engineer	O
Khaled	O
Z	O
.	O
Ahmed	O
and	O
Jordanian	O
engineer	O
Sameer	O
Haddad	O
(	O
who	O
later	O
joined	O
Spansion	O
)	O
demonstrated	O
a	O
charge-trapping	O
mechanism	O
for	O
NOR	O
flash	B-Device
memory	I-Device
cells	O
.	O
</s>
<s>
3D	O
V-NAND	O
(	O
vertical	O
NAND	O
)	O
technology	O
stacks	O
NAND	O
flash	B-Device
memory	I-Device
cells	O
vertically	O
within	O
a	O
chip	O
using	O
3D	O
charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
(	O
CTP	O
)	O
technology	O
.	O
</s>
<s>
3D	O
V-NAND	O
technology	O
was	O
first	O
announced	O
by	O
Toshiba	O
in	O
2007	O
,	O
and	O
the	O
first	O
device	O
,	O
with	O
24	O
layers	O
,	O
was	O
first	O
commercialized	O
by	O
Samsung	B-Application
Electronics	O
in	O
2013	O
.	O
</s>
<s>
3D	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
(	O
3D	B-Architecture
IC	I-Architecture
)	O
technology	O
stacks	O
integrated	O
circuit	O
(	O
IC	O
)	O
chips	O
vertically	O
into	O
a	O
single	O
3D	B-Architecture
IC	I-Architecture
chip	B-Algorithm
package	I-Algorithm
.	O
</s>
<s>
Toshiba	O
introduced	O
3D	B-Architecture
IC	I-Architecture
technology	O
to	O
NAND	O
flash	B-Device
memory	I-Device
in	O
April	O
2007	O
,	O
when	O
they	O
debuted	O
a	O
16GB	O
eMMC	O
compliant	O
(	O
product	O
number	O
THGAM0G7D8DBAI6	O
,	O
often	O
abbreviated	O
THGAM	O
on	O
consumer	O
websites	O
)	O
embedded	B-Architecture
NAND	O
flash	B-Device
memory	I-Device
chip	O
,	O
which	O
was	O
manufactured	O
with	O
eight	O
stacked	O
2GB	O
NAND	O
flash	B-Device
chips	I-Device
.	O
</s>
<s>
In	O
September	O
2007	O
,	O
Hynix	O
Semiconductor	O
(	O
now	O
SK	O
Hynix	O
)	O
introduced	O
24-layer	O
3D	B-Architecture
IC	I-Architecture
technology	O
,	O
with	O
a	O
16GB	O
flash	B-Device
memory	I-Device
chip	O
that	O
was	O
manufactured	O
with	O
24	O
stacked	O
NAND	O
flash	B-Device
chips	I-Device
using	O
a	O
wafer	B-Architecture
bonding	O
process	O
.	O
</s>
<s>
Toshiba	O
also	O
used	O
an	O
eight-layer	O
3D	B-Architecture
IC	I-Architecture
for	O
their	O
32GB	O
THGBM	O
flash	B-Device
chip	I-Device
in	O
2008	O
.	O
</s>
<s>
In	O
2010	O
,	O
Toshiba	O
used	O
a	O
16-layer	O
3D	B-Architecture
IC	I-Architecture
for	O
their	O
128GB	O
THGBM2	O
flash	B-Device
chip	I-Device
,	O
which	O
was	O
manufactured	O
with	O
16	O
stacked	O
8GB	O
chips	O
.	O
</s>
<s>
In	O
the	O
2010s	O
,	O
3D	B-Architecture
ICs	I-Architecture
came	O
into	O
widespread	O
commercial	O
use	O
for	O
NAND	O
flash	B-Device
memory	I-Device
in	O
mobile	B-Application
devices	I-Application
.	O
</s>
<s>
As	O
of	O
August	O
2017	O
,	O
microSD	O
cards	O
with	O
a	O
capacity	O
up	O
to	O
400	O
GB	O
(	O
400	O
billion	O
bytes	B-Application
)	O
are	O
available	O
.	O
</s>
<s>
The	O
same	O
year	O
,	O
Samsung	B-Application
combined	O
3D	B-Architecture
IC	I-Architecture
chip	O
stacking	O
with	O
its	O
3D	O
V-NAND	O
and	O
TLC	O
technologies	O
to	O
manufacture	O
its	O
512GB	O
KLUFG8R1EM	O
flash	B-Device
memory	I-Device
chip	O
with	O
eight	O
stacked	O
64-layer	O
V-NAND	O
chips	O
.	O
</s>
<s>
In	O
2019	O
,	O
Samsung	B-Application
produced	O
a	O
1024GB	O
flash	B-Device
chip	I-Device
,	O
with	O
eight	O
stacked	O
96-layer	O
V-NAND	O
chips	O
and	O
with	O
QLC	O
technology	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
stores	O
information	O
in	O
an	O
array	O
of	O
memory	B-Algorithm
cells	I-Algorithm
made	O
from	O
floating-gate	B-Algorithm
transistors	I-Algorithm
.	O
</s>
<s>
In	O
single-level	O
cell	B-Algorithm
(	O
SLC	O
)	O
devices	O
,	O
each	O
cell	B-Algorithm
stores	O
only	O
one	O
bit	O
of	O
information	O
.	O
</s>
<s>
Multi-level	B-Device
cell	I-Device
(	O
MLC	B-Device
)	O
devices	O
,	O
including	O
triple-level	O
cell	B-Algorithm
(	O
TLC	O
)	O
devices	O
,	O
can	O
store	O
more	O
than	O
one	O
bit	O
per	O
cell	B-Algorithm
.	O
</s>
<s>
The	O
floating	B-Algorithm
gate	I-Algorithm
may	O
be	O
conductive	O
(	O
typically	O
polysilicon	O
in	O
most	O
kinds	O
of	O
flash	B-Device
memory	I-Device
)	O
or	O
non-conductive	O
(	O
as	O
in	O
SONOS	B-Algorithm
flash	B-Device
memory	I-Device
)	O
.	O
</s>
<s>
In	O
flash	B-Device
memory	I-Device
,	O
each	O
memory	B-Algorithm
cell	I-Algorithm
resembles	O
a	O
standard	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MOSFET	B-Architecture
)	O
except	O
that	O
the	O
transistor	O
has	O
two	O
gates	O
instead	O
of	O
one	O
.	O
</s>
<s>
The	O
cells	O
can	O
be	O
seen	O
as	O
an	O
electrical	O
switch	O
in	O
which	O
current	O
flows	O
between	O
two	O
terminals	O
(	O
source	O
and	O
drain	O
)	O
and	O
is	O
controlled	O
by	O
a	O
floating	B-Algorithm
gate	I-Algorithm
(	O
FG	O
)	O
and	O
a	O
control	O
gate	O
(	O
CG	O
)	O
.	O
</s>
<s>
The	O
CG	O
is	O
similar	O
to	O
the	O
gate	O
in	O
other	O
MOS	B-Architecture
transistors	I-Architecture
,	O
but	O
below	O
this	O
,	O
there	O
is	O
the	O
FG	O
insulated	O
all	O
around	O
by	O
an	O
oxide	O
layer	O
.	O
</s>
<s>
The	O
FG	O
is	O
interposed	O
between	O
the	O
CG	O
and	O
the	O
MOSFET	B-Architecture
channel	O
.	O
</s>
<s>
When	O
the	O
FG	O
is	O
charged	O
with	O
electrons	O
,	O
this	O
charge	O
screens	O
the	O
electric	O
field	O
from	O
the	O
CG	O
,	O
thus	O
,	O
increasing	O
the	O
threshold	O
voltage	O
(	O
VT	O
)	O
of	O
the	O
cell	B-Algorithm
.	O
</s>
<s>
This	O
means	O
that	O
the	O
VT	O
of	O
the	O
cell	B-Algorithm
can	O
be	O
changed	O
between	O
the	O
uncharged	O
FG	O
threshold	O
voltage	O
(	O
VT1	O
)	O
and	O
the	O
higher	O
charged	O
FG	O
threshold	O
voltage	O
(	O
VT2	O
)	O
by	O
changing	O
the	O
FG	O
charge	O
.	O
</s>
<s>
In	O
order	O
to	O
read	O
a	O
value	O
from	O
the	O
cell	B-Algorithm
,	O
an	O
intermediate	O
voltage	O
(	O
VI	O
)	O
between	O
VT1	O
and	O
VT2	O
is	O
applied	O
to	O
the	O
CG	O
.	O
</s>
<s>
The	O
binary	O
value	O
of	O
the	O
cell	B-Algorithm
is	O
sensed	O
by	O
determining	O
whether	O
there	O
is	O
current	O
flowing	O
through	O
the	O
transistor	O
when	O
VI	O
is	O
asserted	O
on	O
the	O
CG	O
.	O
</s>
<s>
In	O
a	O
multi-level	B-Device
cell	I-Device
device	O
,	O
which	O
stores	O
more	O
than	O
one	O
bit	O
per	O
cell	B-Algorithm
,	O
the	O
amount	O
of	O
current	O
flow	O
is	O
sensed	O
(	O
rather	O
than	O
simply	O
its	O
presence	O
or	O
absence	O
)	O
,	O
in	O
order	O
to	O
determine	O
more	O
precisely	O
the	O
level	O
of	O
charge	O
on	O
the	O
FG	O
.	O
</s>
<s>
Floating	B-Algorithm
gate	I-Algorithm
MOSFETs	I-Algorithm
are	O
so	O
named	O
because	O
there	O
is	O
an	O
electrically	O
insulating	O
tunnel	O
oxide	O
layer	O
between	O
the	O
floating	B-Algorithm
gate	I-Algorithm
and	O
the	O
silicon	O
,	O
so	O
the	O
gate	O
"	O
floats	O
"	O
above	O
the	O
silicon	O
.	O
</s>
<s>
The	O
oxide	O
keeps	O
the	O
electrons	O
confined	O
to	O
the	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
Degradation	O
or	O
wear	O
(	O
and	O
the	O
limited	O
endurance	O
of	O
floating	B-Algorithm
gate	I-Algorithm
Flash	B-Device
memory	I-Device
)	O
occurs	O
due	O
to	O
the	O
extremely	O
high	O
electric	O
field	O
(	O
10	O
million	O
volts	O
per	O
centimeter	O
)	O
experienced	O
by	O
the	O
oxide	O
.	O
</s>
<s>
Such	O
high	O
voltage	O
densities	O
can	O
break	O
atomic	O
bonds	O
over	O
time	O
in	O
the	O
relatively	O
thin	O
oxide	O
,	O
gradually	O
degrading	O
its	O
electrically	O
insulating	O
properties	O
and	O
allowing	O
electrons	O
to	O
be	O
trapped	O
in	O
and	O
pass	O
through	O
freely	O
(	O
leak	O
)	O
from	O
the	O
floating	B-Algorithm
gate	I-Algorithm
into	O
the	O
oxide	O
,	O
increasing	O
the	O
likelihood	O
of	O
data	O
loss	O
since	O
the	O
electrons	O
(	O
the	O
quantity	O
of	O
which	O
is	O
used	O
to	O
represent	O
different	O
charge	O
levels	O
,	O
each	O
assigned	O
to	O
a	O
different	O
combination	O
of	O
bits	O
in	O
MLC	B-Device
Flash	I-Device
)	O
are	O
normally	O
in	O
the	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
This	O
is	O
why	O
data	O
retention	O
goes	O
down	O
and	O
the	O
risk	O
of	O
data	O
loss	O
increases	O
with	O
increasing	O
degradation.The	O
silicon	O
oxide	O
in	O
a	O
cell	B-Algorithm
degrades	O
with	O
every	O
erase	O
operation	O
.	O
</s>
<s>
The	O
degradation	O
increases	O
the	O
amount	O
of	O
negative	O
charge	O
in	O
the	O
cell	B-Algorithm
over	O
time	O
due	O
to	O
trapped	O
electrons	O
in	O
the	O
oxide	O
and	O
negates	O
some	O
of	O
the	O
control	O
gate	O
voltage	O
,	O
this	O
over	O
time	O
also	O
makes	O
erasing	O
the	O
cell	B-Algorithm
slower	O
,	O
so	O
to	O
maintain	O
the	O
performance	O
and	O
reliability	O
of	O
the	O
NAND	O
chip	O
,	O
the	O
cell	B-Algorithm
must	O
be	O
retired	O
from	O
use	O
.	O
</s>
<s>
Endurance	O
also	O
decreases	O
with	O
the	O
number	O
of	O
bits	O
in	O
a	O
cell	B-Algorithm
.	O
</s>
<s>
With	O
more	O
bits	O
in	O
a	O
cell	B-Algorithm
,	O
the	O
number	O
of	O
possible	O
states	O
(	O
each	O
represented	O
by	O
a	O
different	O
voltage	O
level	O
)	O
in	O
a	O
cell	B-Algorithm
increases	O
and	O
is	O
more	O
sensitive	O
to	O
the	O
voltages	O
used	O
for	O
programming	O
.	O
</s>
<s>
Voltages	O
may	O
be	O
adjusted	O
to	O
compensate	O
for	O
degradation	O
of	O
the	O
silicon	O
oxide	O
,	O
and	O
as	O
the	O
number	O
of	O
bits	O
increases	O
,	O
the	O
number	O
of	O
possible	O
states	O
also	O
increases	O
and	O
thus	O
the	O
cell	B-Algorithm
is	O
less	O
tolerant	O
of	O
adjustments	O
to	O
programming	O
voltages	O
,	O
because	O
there	O
is	O
less	O
space	O
between	O
the	O
voltage	O
levels	O
that	O
define	O
each	O
state	O
in	O
a	O
cell	B-Algorithm
.	O
</s>
<s>
The	O
process	O
of	O
moving	O
electrons	O
from	O
the	O
control	O
gate	O
and	O
into	O
the	O
floating	B-Algorithm
gate	I-Algorithm
is	O
called	O
Fowler	O
–	O
Nordheim	O
tunneling	O
,	O
and	O
it	O
fundamentally	O
changes	O
the	O
characteristics	O
of	O
the	O
cell	B-Algorithm
by	O
increasing	O
the	O
MOSFET	B-Architecture
's	O
threshold	O
voltage	O
.	O
</s>
<s>
The	O
Fowler-Nordheim	O
tunneling	O
effect	O
is	O
reversible	O
,	O
so	O
electrons	O
can	O
be	O
added	O
to	O
or	O
removed	O
from	O
the	O
floating	B-Algorithm
gate	I-Algorithm
,	O
processes	O
traditionally	O
known	O
as	O
writing	O
and	O
erasing	O
.	O
</s>
<s>
Despite	O
the	O
need	O
for	O
relatively	O
high	O
programming	O
and	O
erasing	O
voltages	O
,	O
virtually	O
all	O
flash	B-Device
chips	I-Device
today	O
require	O
only	O
a	O
single	O
supply	O
voltage	O
and	O
produce	O
the	O
high	O
voltages	O
that	O
are	O
required	O
using	O
on-chip	O
charge	O
pumps	O
.	O
</s>
<s>
Over	O
half	O
the	O
energy	O
used	O
by	O
a	O
1.8V	O
NAND	O
flash	B-Device
chip	I-Device
is	O
lost	O
in	O
the	O
charge	O
pump	O
itself	O
.	O
</s>
<s>
Since	O
boost	O
converters	O
are	O
inherently	O
more	O
efficient	O
than	O
charge	O
pumps	O
,	O
researchers	O
developing	O
low-power	O
SSDs	B-Device
have	O
proposed	O
returning	O
to	O
the	O
dual	O
Vcc/Vpp	O
supply	O
voltages	O
used	O
on	O
all	O
early	O
flash	B-Device
chips	I-Device
,	O
driving	O
the	O
high	O
Vpp	O
voltage	O
for	O
all	O
flash	B-Device
chips	I-Device
in	O
an	O
SSD	B-Device
with	O
a	O
single	O
shared	O
external	O
boost	O
converter	O
.	O
</s>
<s>
In	O
spacecraft	O
and	O
other	O
high-radiation	O
environments	O
,	O
the	O
on-chip	O
charge	O
pump	O
is	O
the	O
first	O
part	O
of	O
the	O
flash	B-Device
chip	I-Device
to	O
fail	O
,	O
although	O
flash	B-Device
memories	I-Device
will	O
continue	O
to	O
work	O
in	O
read-only	O
mode	O
at	O
much	O
higher	O
radiation	O
levels	O
.	O
</s>
<s>
In	O
NOR	O
flash	O
,	O
each	O
cell	B-Algorithm
has	O
one	O
end	O
connected	O
directly	O
to	O
ground	O
,	O
and	O
the	O
other	O
end	O
connected	O
directly	O
to	O
a	O
bit	O
line	O
.	O
</s>
<s>
This	O
arrangement	O
is	O
called	O
"	O
NOR	O
flash	O
"	O
because	O
it	O
acts	O
like	O
a	O
NOR	O
gate	O
:	O
when	O
one	O
of	O
the	O
word	O
lines	O
(	O
connected	O
to	O
the	O
cell	B-Algorithm
's	O
CG	O
)	O
is	O
brought	O
high	O
,	O
the	O
corresponding	O
storage	O
transistor	O
acts	O
to	O
pull	O
the	O
output	O
bit	O
line	O
low	O
.	O
</s>
<s>
NOR	O
flash	O
continues	O
to	O
be	O
the	O
technology	O
of	O
choice	O
for	O
embedded	B-Architecture
applications	O
requiring	O
a	O
discrete	O
non-volatile	B-General_Concept
memory	I-General_Concept
device	O
.	O
</s>
<s>
The	O
low	O
read	O
latencies	O
characteristic	O
of	O
NORdevices	O
allow	O
for	O
both	O
direct	O
code	O
execution	O
and	O
data	B-General_Concept
storage	I-General_Concept
in	O
a	O
single	O
memory	O
product	O
.	O
</s>
<s>
A	O
single-level	O
NOR	O
flash	O
cell	B-Algorithm
in	O
its	O
default	O
state	O
is	O
logically	O
equivalent	O
to	O
a	O
binary	O
"	O
1	O
"	O
value	O
,	O
because	O
current	O
will	O
flow	O
through	O
the	O
channel	O
under	O
application	O
of	O
an	O
appropriate	O
voltage	O
to	O
the	O
control	O
gate	O
,	O
so	O
that	O
the	O
bitline	O
voltage	O
is	O
pulled	O
down	O
.	O
</s>
<s>
A	O
NORflash	O
cell	B-Algorithm
can	O
be	O
programmed	O
,	O
or	O
set	O
to	O
a	O
binary	O
"	O
0	O
"	O
value	O
,	O
by	O
the	O
following	O
procedure	O
:	O
</s>
<s>
To	O
erase	O
a	O
NOR	O
flash	O
cell	B-Algorithm
(	O
resetting	O
it	O
to	O
the	O
"	O
1	O
"	O
state	O
)	O
,	O
a	O
large	O
voltage	O
of	O
the	O
opposite	O
polarity	O
is	O
applied	O
between	O
the	O
CG	O
and	O
source	O
terminal	O
,	O
pulling	O
the	O
electrons	O
off	O
the	O
FG	O
through	O
quantum	O
tunneling	O
.	O
</s>
<s>
Modern	O
NORflash	O
memory	B-Architecture
chips	I-Architecture
are	O
divided	O
into	O
erase	O
segments	O
(	O
often	O
called	O
blocks	O
or	O
sectors	O
)	O
.	O
</s>
<s>
The	O
erase	O
operation	O
can	O
be	O
performed	O
only	O
on	O
a	O
block-wise	O
basis	O
;	O
all	O
the	O
cells	O
in	O
an	O
erase	O
segment	O
must	O
be	O
erased	O
together	O
.	O
</s>
<s>
Programming	O
of	O
NOR	O
cells	O
,	O
however	O
,	O
generally	O
can	O
be	O
performed	O
one	O
byte	B-Application
or	O
word	O
at	O
a	O
time	O
.	O
</s>
<s>
NAND	O
flash	O
also	O
uses	O
floating-gate	B-Algorithm
transistors	I-Algorithm
,	O
but	O
they	O
are	O
connected	O
in	O
a	O
way	O
that	O
resembles	O
a	O
NAND	O
gate	O
:	O
several	O
transistors	O
are	O
connected	O
in	O
series	O
,	O
and	O
the	O
bit	O
line	O
is	O
pulled	O
low	O
only	O
if	O
all	O
the	O
word	O
lines	O
are	O
pulled	O
high	O
(	O
above	O
the	O
transistors	O
 '	O
VT	O
)	O
.	O
</s>
<s>
Whereas	O
NORflash	O
might	O
address	B-General_Concept
memory	I-General_Concept
by	O
page	O
then	O
word	O
,	O
NANDflash	O
might	O
address	O
it	O
by	O
page	O
,	O
word	O
and	O
bit	O
.	O
</s>
<s>
Bit-level	O
addressing	O
suits	O
bit-serial	O
applications	O
(	O
such	O
as	O
hard	B-Device
disk	I-Device
emulation	O
)	O
,	O
which	O
access	O
only	O
one	O
bit	O
at	O
a	O
time	O
.	O
</s>
<s>
NANDflash	O
memory	O
forms	O
the	O
core	O
of	O
the	O
removable	O
USB	B-Protocol
storage	I-Protocol
devices	I-Protocol
known	O
as	O
USB	B-Protocol
flash	O
drives	O
,	O
as	O
well	O
as	O
most	O
memory	B-Device
card	I-Device
formats	O
and	O
solid-state	B-Device
drives	I-Device
available	O
today	O
.	O
</s>
<s>
The	O
hierarchical	O
structure	O
of	O
NAND	O
flash	O
starts	O
at	O
a	O
cell	B-Algorithm
level	O
which	O
establishes	O
strings	O
,	O
then	O
pages	O
,	O
blocks	O
,	O
planes	O
and	O
ultimately	O
a	O
die	O
.	O
</s>
<s>
A	O
string	O
is	O
a	O
series	O
of	O
connected	O
NAND	O
cells	O
in	O
which	O
the	O
source	O
of	O
one	O
cell	B-Algorithm
is	O
connected	O
to	O
the	O
drain	O
of	O
the	O
next	O
one	O
.	O
</s>
<s>
When	O
a	O
block	B-General_Concept
is	O
erased	O
,	O
all	O
the	O
cells	O
are	O
logically	O
set	O
to	O
1	O
.	O
</s>
<s>
Data	O
can	O
only	O
be	O
programmed	O
in	O
one	O
pass	O
to	O
a	O
page	B-Architecture
in	I-Architecture
a	O
block	B-General_Concept
that	O
was	O
erased	O
.	O
</s>
<s>
Any	O
cells	O
that	O
have	O
been	O
set	O
to	O
0	O
by	O
programming	O
can	O
only	O
be	O
reset	O
to	O
1	O
by	O
erasing	O
the	O
entire	O
block	B-General_Concept
.	O
</s>
<s>
If	O
no	O
erased	O
page	O
is	O
available	O
,	O
a	O
block	B-General_Concept
must	O
be	O
erased	O
before	O
copying	O
the	O
data	O
to	O
a	O
page	B-Architecture
in	I-Architecture
that	O
block	B-General_Concept
.	O
</s>
<s>
Vertical	O
NAND	O
(	O
V-NAND	O
)	O
or	O
3D	O
NAND	B-Device
memory	I-Device
stacks	O
memory	B-Algorithm
cells	I-Algorithm
vertically	O
and	O
uses	O
a	O
charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
architecture	O
.	O
</s>
<s>
V-NAND	O
was	O
first	O
commercially	O
manufactured	O
by	O
Samsung	B-Application
Electronics	O
in	O
2013	O
.	O
</s>
<s>
V-NAND	O
uses	O
a	O
charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
geometry	O
(	O
which	O
was	O
commercially	O
introduced	O
in	O
2002	O
by	O
AMD	O
and	O
Fujitsu	O
)	O
that	O
stores	O
charge	O
on	O
an	O
embedded	B-Architecture
silicon	O
nitride	O
film	O
.	O
</s>
<s>
V-NAND	O
wraps	O
a	O
planar	O
charge	O
trap	O
cell	B-Algorithm
into	O
a	O
cylindrical	O
form	O
.	O
</s>
<s>
As	O
of	O
2020	O
,	O
3D	O
NAND	O
Flash	B-Device
memories	I-Device
by	O
Micron	O
and	O
Intel	O
instead	O
use	O
floating	B-Algorithm
gates	I-Algorithm
,	O
however	O
,	O
Micron	O
128	O
layer	O
and	O
above	O
3D	O
NAND	B-Device
memories	I-Device
use	O
a	O
conventional	O
charge	O
trap	O
structure	O
,	O
due	O
to	O
the	O
dissolution	O
of	O
the	O
partnership	O
between	O
Micron	O
and	O
Intel	O
.	O
</s>
<s>
Charge	O
trap	O
3D	O
NAND	O
Flash	O
is	O
thinner	O
than	O
floating	B-Algorithm
gate	I-Algorithm
3D	O
NAND	O
.	O
</s>
<s>
In	O
floating	B-Algorithm
gate	I-Algorithm
3D	O
NAND	O
,	O
the	O
memory	B-Algorithm
cells	I-Algorithm
are	O
completely	O
separated	O
from	O
one	O
another	O
,	O
whereas	O
in	O
charge	O
trap	O
3D	O
NAND	O
,	O
vertical	O
groups	O
of	O
memory	B-Algorithm
cells	I-Algorithm
share	O
the	O
same	O
silicon	O
nitride	O
material	O
.	O
</s>
<s>
An	O
individual	O
memory	B-Algorithm
cell	I-Algorithm
is	O
made	O
up	O
of	O
one	O
planar	O
polysilicon	O
layer	O
containing	O
a	O
hole	O
filled	O
by	O
multiple	O
concentric	O
vertical	O
cylinders	O
.	O
</s>
<s>
Memory	B-Algorithm
cells	I-Algorithm
in	O
different	O
vertical	O
layers	O
do	O
not	O
interfere	O
with	O
each	O
other	O
,	O
as	O
the	O
charges	O
cannot	O
move	O
vertically	O
through	O
the	O
silicon	O
nitride	O
storage	B-General_Concept
medium	I-General_Concept
,	O
and	O
the	O
electric	O
fields	O
associated	O
with	O
the	O
gates	O
are	O
closely	O
confined	O
within	O
each	O
layer	O
.	O
</s>
<s>
In	O
practice	O
,	O
a	O
128Gibit	O
V-NAND	O
chip	O
with	O
24	O
layers	O
of	O
memory	B-Algorithm
cells	I-Algorithm
requires	O
about	O
2.9	O
billion	O
such	O
holes	O
.	O
</s>
<s>
As	O
of	O
2020	O
,	O
V-NAND	O
chips	O
with	O
160	O
layers	O
are	O
under	O
development	O
by	O
Samsung	B-Application
.	O
</s>
<s>
The	O
wafer	B-Architecture
cost	O
of	O
a	O
3D	O
NAND	O
is	O
comparable	O
with	O
scaled	O
down	O
(	O
32nm	O
or	O
less	O
)	O
planar	O
NAND	O
Flash	O
.	O
</s>
<s>
One	O
limitation	O
of	O
flash	B-Device
memory	I-Device
is	O
that	O
it	O
can	O
be	O
erased	O
only	O
a	O
block	B-General_Concept
at	O
a	O
time	O
.	O
</s>
<s>
This	O
generally	O
sets	O
all	O
bits	O
in	O
the	O
block	B-General_Concept
to	O
1	O
.	O
</s>
<s>
Starting	O
with	O
a	O
freshly	O
erased	O
block	B-General_Concept
,	O
any	O
location	O
within	O
that	O
block	B-General_Concept
can	O
be	O
programmed	O
.	O
</s>
<s>
However	O
,	O
once	O
a	O
bit	O
has	O
been	O
set	O
to	O
0	O
,	O
only	O
by	O
erasing	O
the	O
entire	O
block	B-General_Concept
can	O
it	O
be	O
changed	O
back	O
to	O
1	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
flash	B-Device
memory	I-Device
(	O
specifically	O
NORflash	O
)	O
offers	O
random-access	B-General_Concept
read	O
and	O
programming	O
operations	O
but	O
does	O
not	O
offer	O
arbitrary	O
random-access	B-General_Concept
rewrite	O
or	O
erase	O
operations	O
.	O
</s>
<s>
Some	O
file	O
systems	O
designed	O
for	O
flash	O
devices	O
make	O
use	O
of	O
this	O
rewrite	O
capability	O
,	O
for	O
example	O
Yaffs1	B-Application
,	O
to	O
represent	O
sector	O
metadata	O
.	O
</s>
<s>
Other	O
flash	O
file	O
systems	O
,	O
such	O
as	O
YAFFS2	B-Application
,	O
never	O
make	O
use	O
of	O
this	O
"	O
rewrite	O
"	O
capability	O
—	O
they	O
do	O
a	O
lot	O
of	O
extra	O
work	O
to	O
meet	O
a	O
"	O
write	O
once	O
rule	O
"	O
.	O
</s>
<s>
Although	O
data	O
structures	O
in	O
flash	B-Device
memory	I-Device
cannot	O
be	O
updated	O
in	O
completely	O
general	O
ways	O
,	O
this	O
allows	O
members	O
to	O
be	O
"	O
removed	O
"	O
by	O
marking	O
them	O
as	O
invalid	O
.	O
</s>
<s>
This	O
technique	O
may	O
need	O
to	O
be	O
modified	O
for	O
multi-level	B-Device
cell	I-Device
devices	O
,	O
where	O
one	O
memory	B-Algorithm
cell	I-Algorithm
holds	O
more	O
than	O
one	O
bit	O
.	O
</s>
<s>
Common	O
flash	O
devices	O
such	O
as	O
USB	B-Protocol
flash	O
drives	O
and	O
memory	B-Device
cards	I-Device
provide	O
only	O
a	O
block-level	O
interface	O
,	O
or	O
flash	O
translation	O
layer	O
(	O
FTL	O
)	O
,	O
which	O
writes	O
to	O
a	O
different	O
cell	B-Algorithm
each	O
time	O
to	O
wear-level	O
the	O
device	O
.	O
</s>
<s>
This	O
prevents	O
incremental	O
writing	O
within	O
a	O
block	B-General_Concept
;	O
however	O
,	O
it	O
does	O
help	O
the	O
device	O
from	O
being	O
prematurely	O
worn	O
out	O
by	O
intensive	O
write	O
patterns	O
.	O
</s>
<s>
Another	O
limitation	O
is	O
that	O
flash	B-Device
memory	I-Device
has	O
a	O
finite	O
number	O
of	O
program	O
erase	O
cycles	O
(	O
typically	O
written	O
as	O
P/Ecycles	O
)	O
.	O
</s>
<s>
Micron	O
Technology	O
and	O
Sun	O
Microsystems	O
announced	O
an	O
SLCNAND	O
flash	B-Device
memory	I-Device
chip	O
rated	O
for	O
1,000,000	O
P/Ecycles	O
on	O
17	O
December	O
2008	O
.	O
</s>
<s>
Longer	O
P/E	O
cycles	O
of	O
Industrial	O
SSDs	B-Device
speak	O
for	O
their	O
endurance	O
level	O
and	O
make	O
them	O
more	O
reliable	O
for	O
Industrial	O
usage	O
.	O
</s>
<s>
The	O
guaranteed	O
cycle	O
count	O
may	O
apply	O
only	O
to	O
block	B-General_Concept
zero	O
(	O
as	O
is	O
the	O
case	O
with	O
TSOPNAND	O
devices	O
)	O
,	O
or	O
to	O
all	O
blocks	O
(	O
as	O
in	O
NOR	O
)	O
.	O
</s>
<s>
This	O
effect	O
is	O
mitigated	O
in	O
some	O
chip	O
firmware	B-Application
or	O
file	O
system	O
drivers	O
by	O
counting	O
the	O
writes	O
and	O
dynamically	O
remapping	O
blocks	O
in	O
order	O
to	O
spread	O
write	O
operations	O
between	O
sectors	O
;	O
this	O
technique	O
is	O
called	O
wear	B-Application
leveling	I-Application
.	O
</s>
<s>
Another	O
approach	O
is	O
to	O
perform	O
write	O
verification	O
and	O
remapping	O
to	O
spare	O
sectors	O
in	O
case	O
of	O
write	O
failure	O
,	O
a	O
technique	O
called	O
bad	B-Device
block	I-Device
management	O
(	O
BBM	O
)	O
.	O
</s>
<s>
For	O
portable	O
consumer	O
devices	O
,	O
these	O
wear	O
out	O
management	O
techniques	O
typically	O
extend	O
the	O
life	O
of	O
the	O
flash	B-Device
memory	I-Device
beyond	O
the	O
life	O
of	O
the	O
device	O
itself	O
,	O
and	O
some	O
data	O
loss	O
may	O
be	O
acceptable	O
in	O
these	O
applications	O
.	O
</s>
<s>
For	O
high-reliability	O
data	B-General_Concept
storage	I-General_Concept
,	O
however	O
,	O
it	O
is	O
not	O
advisable	O
to	O
use	O
flash	B-Device
memory	I-Device
that	O
would	O
have	O
to	O
go	O
through	O
a	O
large	O
number	O
of	O
programming	O
cycles	O
.	O
</s>
<s>
This	O
limitation	O
is	O
meaningless	O
for	O
'	O
read-only	O
'	O
applications	O
such	O
as	O
thin	B-Device
clients	I-Device
and	O
routers	B-Algorithm
,	O
which	O
are	O
programmed	O
only	O
once	O
or	O
at	O
most	O
a	O
few	O
times	O
during	O
their	O
lifetimes	O
.	O
</s>
<s>
In	O
December	O
2012	O
,	O
Taiwanese	O
engineers	O
from	O
Macronix	O
revealed	O
their	O
intention	O
to	O
announce	O
at	O
the	O
2012	O
IEEE	O
International	O
Electron	O
Devices	O
Meeting	O
that	O
they	O
had	O
figured	O
out	O
how	O
to	O
improve	O
NANDflash	O
storage	O
read/write	O
cycles	O
from	O
10,000	O
to	O
100	O
million	O
cycles	O
using	O
a	O
"	O
self-healing	O
"	O
process	O
that	O
used	O
a	O
flash	B-Device
chip	I-Device
with	O
"	O
onboard	O
heaters	O
that	O
could	O
anneal	O
small	O
groups	O
of	O
memory	O
cells.	O
"	O
</s>
<s>
The	O
method	O
used	O
to	O
read	O
NANDflash	O
memory	O
can	O
cause	O
nearby	O
cells	O
in	O
the	O
same	O
memory	O
block	B-General_Concept
to	O
change	O
over	O
time	O
(	O
become	O
programmed	O
)	O
.	O
</s>
<s>
If	O
reading	O
continually	O
from	O
one	O
cell	B-Algorithm
,	O
that	O
cell	B-Algorithm
will	O
not	O
fail	O
but	O
rather	O
one	O
of	O
the	O
surrounding	O
cells	O
on	O
a	O
subsequent	O
read	O
.	O
</s>
<s>
To	O
avoid	O
the	O
read	O
disturb	O
problem	O
the	O
flash	B-Device
controller	I-Device
will	O
typically	O
count	O
the	O
total	O
number	O
of	O
reads	O
to	O
a	O
block	B-General_Concept
since	O
the	O
last	O
erase	O
.	O
</s>
<s>
When	O
the	O
count	O
exceeds	O
a	O
target	O
limit	O
,	O
the	O
affected	O
block	B-General_Concept
is	O
copied	O
over	O
to	O
a	O
new	O
block	B-General_Concept
,	O
erased	O
,	O
then	O
released	O
to	O
the	O
block	B-General_Concept
pool	O
.	O
</s>
<s>
The	O
original	O
block	B-General_Concept
is	O
as	O
good	O
as	O
new	O
after	O
the	O
erase	O
.	O
</s>
<s>
If	O
the	O
flash	B-Device
controller	I-Device
does	O
not	O
intervene	O
in	O
time	O
,	O
however	O
,	O
a	O
read	O
disturb	O
error	O
will	O
occur	O
with	O
possible	O
data	O
loss	O
if	O
the	O
errors	O
are	O
too	O
numerous	O
to	O
correct	O
with	O
an	O
error-correcting	B-Error_Name
code	I-Error_Name
.	O
</s>
<s>
Most	O
flash	O
ICs	O
come	O
in	O
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	B-Algorithm
)	O
packages	B-Algorithm
,	O
and	O
even	O
the	O
ones	O
that	O
do	O
not	O
are	O
often	O
mounted	O
on	O
a	O
PCB	O
next	O
to	O
other	O
BGA	B-Algorithm
packages	B-Algorithm
.	O
</s>
<s>
After	O
PCB	O
Assembly	O
,	O
boards	O
with	O
BGA	B-Algorithm
packages	B-Algorithm
are	O
often	O
X-rayed	O
to	O
see	O
if	O
the	O
balls	O
are	O
making	O
proper	O
connections	O
to	O
the	O
proper	O
pad	O
,	O
or	O
if	O
the	O
BGA	B-Algorithm
needs	O
rework	O
.	O
</s>
<s>
These	O
X-rays	O
can	O
erase	O
programmed	O
bits	O
in	O
a	O
flash	B-Device
chip	I-Device
(	O
convert	O
programmed	O
"	O
0	O
"	O
bits	O
into	O
erased	O
"	O
1	O
"	O
bits	O
)	O
.	O
</s>
<s>
Some	O
manufacturers	O
are	O
now	O
making	O
X-ray	O
proof	O
SD	O
and	O
USB	B-Protocol
memory	B-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
The	O
low-level	O
interface	O
to	O
flash	B-Device
memory	I-Device
chips	O
differs	O
from	O
those	O
of	O
other	O
memory	O
types	O
such	O
as	O
DRAM	O
,	O
ROM	B-Device
,	O
and	O
EEPROM	B-General_Concept
,	O
which	O
support	O
bit-alterability	O
(	O
both	O
zero	O
to	O
one	O
and	O
one	O
to	O
zero	O
)	O
and	O
random	B-General_Concept
access	I-General_Concept
via	O
externally	O
accessible	O
address	O
buses	O
.	O
</s>
<s>
NOR	O
memory	O
has	O
an	O
external	O
address	B-Architecture
bus	I-Architecture
for	O
reading	O
and	O
programming	O
.	O
</s>
<s>
For	O
NOR	O
memory	O
,	O
reading	O
and	O
programming	O
are	O
random-access	B-General_Concept
,	O
and	O
unlocking	O
and	O
erasing	O
are	O
block-wise	O
.	O
</s>
<s>
For	O
NAND	B-Device
memory	I-Device
,	O
reading	O
and	O
programming	O
are	O
page-wise	O
,	O
and	O
unlocking	O
and	O
erasing	O
are	O
block-wise	O
.	O
</s>
<s>
Reading	O
from	O
NOR	O
flash	O
is	O
similar	O
to	O
reading	O
from	O
random-access	B-General_Concept
memory	O
,	O
provided	O
the	O
address	O
and	O
data	O
bus	O
are	O
mapped	O
correctly	O
.	O
</s>
<s>
Because	O
of	O
this	O
,	O
most	O
microprocessors	O
can	O
use	O
NORflash	O
memory	O
as	O
execute	B-Application
in	I-Application
place	I-Application
(	O
XIP	B-Application
)	O
memory	O
,	O
meaning	O
that	O
programs	O
stored	O
in	O
NORflash	O
can	O
be	O
executed	O
directly	O
from	O
the	O
NORflash	O
without	O
needing	O
to	O
be	O
copied	O
into	O
RAM	O
first	O
.	O
</s>
<s>
NORflash	O
may	O
be	O
programmed	O
in	O
a	O
random-access	B-General_Concept
manner	O
similar	O
to	O
reading	O
.	O
</s>
<s>
Erasure	O
must	O
happen	O
a	O
block	B-General_Concept
at	O
a	O
time	O
,	O
and	O
resets	O
all	O
the	O
bits	O
in	O
the	O
erased	O
block	B-General_Concept
back	O
to	O
one	O
.	O
</s>
<s>
Typical	O
block	B-General_Concept
sizes	I-General_Concept
are	O
64	O
,	O
128	O
,	O
or	O
256KiB	O
.	O
</s>
<s>
Bad	B-Device
block	I-Device
management	O
is	O
a	O
relatively	O
new	O
feature	O
in	O
NORchips	O
.	O
</s>
<s>
In	O
older	O
NOR	O
devices	O
not	O
supporting	O
bad	B-Device
block	I-Device
management	O
,	O
the	O
software	O
or	O
device	B-Application
driver	I-Application
controlling	O
the	O
memory	B-Architecture
chip	I-Architecture
must	O
correct	O
for	O
blocks	O
that	O
wear	O
out	O
,	O
or	O
the	O
device	O
will	O
cease	O
to	O
work	O
reliably	O
.	O
</s>
<s>
To	O
avoid	O
needing	O
unique	O
driver	B-Application
software	I-Application
for	O
every	O
device	O
made	O
,	O
special	O
Common	B-General_Concept
Flash	I-General_Concept
Memory	I-General_Concept
Interface	I-General_Concept
(	O
CFI	O
)	O
commands	O
allow	O
the	O
device	O
to	O
identify	O
itself	O
and	O
its	O
critical	O
operating	O
parameters	O
.	O
</s>
<s>
Besides	O
its	O
use	O
as	O
random-access	B-General_Concept
ROM	B-Device
,	O
NORflash	O
can	O
also	O
be	O
used	O
as	O
a	O
storage	O
device	O
,	O
by	O
taking	O
advantage	O
of	O
random-access	B-General_Concept
programming	O
.	O
</s>
<s>
Typical	O
NOR	O
flash	O
does	O
not	O
need	O
an	O
error	B-Error_Name
correcting	I-Error_Name
code	I-Error_Name
.	O
</s>
<s>
These	O
memories	O
are	O
accessed	O
much	O
like	O
block	B-General_Concept
devices	I-General_Concept
,	O
such	O
as	O
hard	B-Device
disks	I-Device
.	O
</s>
<s>
Each	O
block	B-General_Concept
consists	O
of	O
a	O
number	O
of	O
pages	O
.	O
</s>
<s>
The	O
pages	O
are	O
typically	O
512	O
,	O
2,048	O
or	O
4,096	O
bytes	B-Application
in	O
size	O
.	O
</s>
<s>
Associated	O
with	O
each	O
page	O
are	O
a	O
few	O
bytes	B-Application
(	O
typically	O
1/32	O
of	O
the	O
data	O
size	O
)	O
that	O
can	O
be	O
used	O
for	O
storage	O
of	O
an	O
error	B-Error_Name
correcting	I-Error_Name
code	I-Error_Name
(	O
ECC	O
)	O
checksum	B-Algorithm
.	O
</s>
<s>
Typical	O
block	B-General_Concept
sizes	I-General_Concept
include	O
:	O
</s>
<s>
128	O
pages	O
of	O
4,096	O
+128	O
bytes	B-Application
each	O
for	O
a	O
block	B-General_Concept
size	I-General_Concept
of	O
512KiB	O
.	O
</s>
<s>
While	O
reading	O
and	O
programming	O
is	O
performed	O
on	O
a	O
page	O
basis	O
,	O
erasure	O
can	O
only	O
be	O
performed	O
on	O
a	O
block	B-General_Concept
basis	O
.	O
</s>
<s>
NAND	O
devices	O
also	O
require	O
bad	B-Device
block	I-Device
management	O
by	O
the	O
device	B-Application
driver	I-Application
software	O
or	O
by	O
a	O
separate	O
controller	B-Device
chip	O
.	O
</s>
<s>
Some	O
SDcards	B-Device
,	O
for	O
example	O
,	O
include	O
controller	B-Device
circuitry	O
to	O
perform	O
bad	B-Device
block	I-Device
management	O
and	O
wear	B-Application
leveling	I-Application
.	O
</s>
<s>
When	O
a	O
logical	O
block	B-General_Concept
is	O
accessed	O
by	O
high-level	O
software	O
,	O
it	O
is	O
mapped	O
to	O
a	O
physical	O
block	B-General_Concept
by	O
the	O
device	B-Application
driver	I-Application
or	O
controller	B-Device
.	O
</s>
<s>
A	O
number	O
of	O
blocks	O
on	O
the	O
flash	B-Device
chip	I-Device
may	O
be	O
set	O
aside	O
for	O
storing	O
mapping	O
tables	O
to	O
deal	O
with	O
bad	B-Device
blocks	I-Device
,	O
or	O
the	O
system	O
may	O
simply	O
check	O
each	O
block	B-General_Concept
at	O
power-up	O
to	O
create	O
a	O
bad	B-Device
block	I-Device
map	O
in	O
RAM	O
.	O
</s>
<s>
The	O
data	O
is	O
then	O
written	O
to	O
a	O
different	O
,	O
good	O
block	B-General_Concept
,	O
and	O
the	O
bad	B-Device
block	I-Device
map	O
is	O
updated	O
.	O
</s>
<s>
Hamming	B-Error_Name
codes	I-Error_Name
are	O
the	O
most	O
commonly	O
used	O
ECC	O
for	O
SLCNAND	O
flash	O
.	O
</s>
<s>
Reed-Solomon	B-Error_Name
codes	I-Error_Name
and	O
BCH	O
codes	O
(	O
Bose-Chaudhuri-Hocquenghem	O
codes	O
)	O
are	O
commonly	O
used	O
ECC	O
for	O
MLCNAND	O
flash	O
.	O
</s>
<s>
Some	O
MLCNAND	O
flash	B-Device
chips	I-Device
internally	O
generate	O
the	O
appropriate	O
BCHerror	O
correction	O
codes	O
.	O
</s>
<s>
Most	O
NAND	O
devices	O
are	O
shipped	O
from	O
the	O
factory	O
with	O
some	O
bad	B-Device
blocks	I-Device
.	O
</s>
<s>
These	O
are	O
typically	O
marked	O
according	O
to	O
a	O
specified	O
bad	B-Device
block	I-Device
marking	O
strategy	O
.	O
</s>
<s>
By	O
allowing	O
some	O
bad	B-Device
blocks	I-Device
,	O
manufacturers	O
achieve	O
far	O
higher	O
yields	O
than	O
would	O
be	O
possible	O
if	O
all	O
blocks	O
had	O
to	O
be	O
verified	O
to	O
be	O
good	O
.	O
</s>
<s>
When	O
executing	O
software	O
from	O
NAND	B-Device
memories	I-Device
,	O
virtual	B-Architecture
memory	I-Architecture
strategies	O
are	O
often	O
used	O
:	O
memory	O
contents	O
must	O
first	O
be	O
paged	B-Architecture
or	O
copied	O
into	O
memory-mapped	O
RAM	O
and	O
executed	O
there	O
(	O
leading	O
to	O
the	O
common	O
combination	O
of	O
NAND	O
+	O
RAM	O
)	O
.	O
</s>
<s>
A	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
in	O
the	O
system	O
is	O
helpful	O
,	O
but	O
this	O
can	O
also	O
be	O
accomplished	O
with	O
overlays	B-General_Concept
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
some	O
systems	O
will	O
use	O
a	O
combination	O
of	O
NOR	O
and	O
NAND	B-Device
memories	I-Device
,	O
where	O
a	O
smaller	O
NOR	O
memory	O
is	O
used	O
as	O
software	O
ROM	B-Device
and	O
a	O
larger	O
NAND	B-Device
memory	I-Device
is	O
partitioned	O
with	O
a	O
file	O
system	O
for	O
use	O
as	O
a	O
non-volatile	B-General_Concept
data	B-General_Concept
storage	I-General_Concept
area	O
.	O
</s>
<s>
NAND	O
sacrifices	O
the	O
random-access	B-General_Concept
and	O
execute-in-place	B-Application
advantages	O
of	O
NOR	O
.	O
</s>
<s>
NAND	O
is	O
best	O
suited	O
to	O
systems	O
requiring	O
high	O
capacity	O
data	B-General_Concept
storage	I-General_Concept
.	O
</s>
<s>
A	O
group	O
called	O
the	O
Open	B-General_Concept
NAND	I-General_Concept
Flash	I-General_Concept
Interface	I-General_Concept
Working	I-General_Concept
Group	I-General_Concept
(	O
ONFI	B-General_Concept
)	O
has	O
developed	O
a	O
standardized	O
low-level	O
interface	O
for	O
NANDflash	O
chips	O
.	O
</s>
<s>
The	O
ONFI	B-General_Concept
specification	I-General_Concept
version	O
1.0	O
was	O
released	O
on	O
28	O
December	O
2006	O
.	O
</s>
<s>
The	O
ONFI	B-General_Concept
group	O
is	O
supported	O
by	O
major	O
NAND	O
flash	O
manufacturers	O
,	O
including	O
Hynix	O
,	O
Intel	O
,	O
Micron	O
Technology	O
,	O
and	O
Numonyx	O
,	O
as	O
well	O
as	O
by	O
major	O
manufacturers	O
of	O
devices	O
incorporating	O
NANDflash	O
chips	O
.	O
</s>
<s>
Two	O
major	O
flash	O
device	O
manufacturers	O
,	O
Toshiba	O
and	O
Samsung	B-Application
,	O
have	O
chosen	O
to	O
use	O
an	O
interface	O
of	O
their	O
own	O
design	O
known	O
as	O
Toggle	O
Mode	O
(	O
and	O
now	O
Toggle	O
)	O
.	O
</s>
<s>
This	O
interface	O
is	O
n't	O
pin-to-pin	O
compatible	O
with	O
the	O
ONFI	B-General_Concept
specification	I-General_Concept
.	O
</s>
<s>
A	O
group	O
of	O
vendors	O
,	O
including	O
Intel	O
,	O
Dell	O
,	O
and	O
Microsoft	O
,	O
formed	O
a	O
Non-Volatile	B-Application
Memory	I-Application
Host	I-Application
Controller	I-Application
Interface	I-Application
(	O
NVMHCI	B-Application
)	O
Working	O
Group	O
.	O
</s>
<s>
The	O
goal	O
of	O
the	O
group	O
is	O
to	O
provide	O
standard	O
software	O
and	O
hardware	O
programming	O
interfaces	O
for	O
nonvolatile	B-General_Concept
memory	I-General_Concept
subsystems	O
,	O
including	O
the	O
"	O
flash	O
cache	B-General_Concept
"	O
device	O
connected	O
to	O
the	O
PCI	O
Express	O
bus	O
.	O
</s>
<s>
The	O
connections	O
of	O
the	O
individual	O
memory	B-Algorithm
cells	I-Algorithm
are	O
different	O
.	O
</s>
<s>
The	O
interface	O
provided	O
for	O
reading	O
and	O
writing	O
the	O
memory	O
is	O
different	O
;	O
NOR	O
allows	O
random	B-General_Concept
access	I-General_Concept
,	O
while	O
NAND	O
allows	O
only	O
page	O
access	O
.	O
</s>
<s>
NOR	O
and	O
NAND	O
flash	O
get	O
their	O
names	O
from	O
the	O
structure	O
of	O
the	O
interconnections	O
between	O
memory	B-Algorithm
cells	I-Algorithm
.	O
</s>
<s>
The	O
parallel	O
connection	O
of	O
cells	O
resembles	O
the	O
parallel	O
connection	O
of	O
transistors	O
in	O
a	O
CMOS	B-Device
NOR	O
gate	O
.	O
</s>
<s>
In	O
NANDflash	O
,	O
cells	O
are	O
connected	O
in	O
series	O
,	O
resembling	O
a	O
CMOS	B-Device
NAND	O
gate	O
.	O
</s>
<s>
Each	O
NOR	O
flash	O
cell	B-Algorithm
is	O
larger	O
than	O
a	O
NANDflash	O
cell	B-Algorithm
10F2	O
vs	O
4F2	O
even	O
when	O
using	O
exactly	O
the	O
same	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
and	O
so	O
each	O
transistor	O
,	O
contact	O
,	O
etc	O
.	O
</s>
<s>
is	O
exactly	O
the	O
same	O
size	O
because	O
NORflash	O
cells	O
require	O
a	O
separate	O
metal	O
contact	O
for	O
each	O
cell	B-Algorithm
.	O
</s>
<s>
Because	O
of	O
the	O
series	O
connection	O
and	O
removal	O
of	O
wordline	O
contacts	O
,	O
a	O
large	O
grid	O
of	O
NANDflash	O
memory	B-Algorithm
cells	I-Algorithm
will	O
occupy	O
perhaps	O
only	O
60%	O
of	O
the	O
area	O
of	O
equivalent	O
NOR	O
cells	O
(	O
assuming	O
the	O
same	O
CMOS	B-Device
process	O
resolution	O
,	O
for	O
example	O
,	O
130nm	O
,	O
90nm	O
,	O
or	O
65nm	O
)	O
.	O
</s>
<s>
This	O
design	O
choice	O
made	O
random-access	B-General_Concept
of	O
NANDflash	O
memory	O
impossible	O
,	O
but	O
the	O
goal	O
of	O
NANDflash	O
was	O
to	O
replace	O
mechanical	O
hard	B-Device
disks	I-Device
,	O
not	O
to	O
replace	O
ROMs	O
.	O
</s>
<s>
The	O
write	O
endurance	O
of	O
SLC	O
floating-gate	B-Algorithm
NOR	O
flash	O
is	O
typically	O
equal	O
to	O
or	O
greater	O
than	O
that	O
of	O
NANDflash	O
,	O
while	O
MLCNOR	O
and	O
NANDflash	O
have	O
similar	O
endurance	O
capabilities	O
.	O
</s>
<s>
Examples	O
of	O
endurance	O
cycle	O
ratings	O
listed	O
in	O
datasheets	O
for	O
NAND	O
and	O
NORflash	O
,	O
as	O
well	O
as	O
in	O
storage	O
devices	O
using	O
flash	B-Device
memory	I-Device
,	O
are	O
provided	O
.	O
</s>
<s>
Type	O
of	O
flashmemory	O
Endurance	O
rating(erases per block )	O
Example(s )	O
of	O
flash	B-Device
memory	I-Device
or	O
storage	O
device	O
SLC	O
NAND	O
100,000	O
Samsung	B-Application
OneNAND	O
KFW4G16Q2M	O
,	O
Toshiba	O
SLC	O
NAND	O
Flash	B-Device
chips	I-Device
,	O
Transcend	O
SD500	O
,	O
Fujitsu	O
S26361-F3298	O
MLC	B-Device
NAND	O
5,000	O
–	O
10,000	O
formedium-capacity	O
;	O
1,000	O
to	O
3,000	O
forhigh-capacity	O
Samsung	B-Application
K9G8G08U0M	O
(	O
Example	O
for	O
medium-capacity	O
applications	O
)	O
,	O
Memblaze	O
PBlaze4	O
,	O
ADATA	O
SU900	O
,	O
Mushkin	O
Reactor	O
TLC	O
NAND	O
1,000	O
Samsung	B-Application
SSD	B-Device
840	O
QLC	O
NAND	O
unknown	O
SanDisk	O
X4	O
NAND	O
flash	B-Device
SD	I-Device
cards	I-Device
3D	O
SLC	O
NAND	O
100,000	O
Samsung	B-Application
Z-NAND	O
6,000	O
–	O
40,000	O
Samsung	B-Application
SSD	B-Device
850	O
PRO	O
,	O
Samsung	B-Application
SSD	B-Device
845DC	O
PRO	O
,	O
Samsung	B-Application
860	O
PRO	O
3D	O
TLC	O
NAND	O
1,000	O
–	O
3,000	O
Samsung	B-Application
SSD	B-Device
850	O
EVO	O
,	O
Samsung	B-Application
SSD	B-Device
845DC	O
EVO	O
,	O
Crucial	O
MX300，Memblaze	O
PBlaze5	O
900	O
,	O
Memblaze	O
PBlaze5	O
700	O
,	O
Memblaze	O
PBlaze5	O
910/916	O
,	O
Memblaze	O
PBlaze5	O
510/516	O
,	O
ADATA	O
SX	O
8200	O
PRO	O
(	O
also	O
being	O
sold	O
under	O
"	O
XPG	O
Gammix	O
"	O
branding	O
,	O
model	O
S11	O
PRO	O
)	O
3D	O
QLC	O
NAND	O
100	O
–	O
1,000	O
Samsung	B-Application
SSD	B-Device
860	O
QVO	O
SATA	O
,	O
Intel	O
SSD	B-Device
660p	O
,	O
Samsung	B-Application
SSD	B-Device
980	O
QVO	O
NVMe	B-Application
,	O
Micron	O
5210	O
ION	O
,	O
Samsung	B-Application
SSD	B-Device
BM991	O
NVMe	B-Application
3D	O
PLC	O
NAND	O
unknown	O
In	O
development	O
by	O
SK	O
Hynix	O
(	O
formerly	O
Intel	O
)	O
and	O
Kioxia	O
(	O
formerly	O
Toshiba	O
Memory	O
)	O
.	O
</s>
<s>
However	O
,	O
by	O
applying	O
certain	O
algorithms	O
and	O
design	O
paradigms	O
such	O
as	O
wear	B-Application
leveling	I-Application
and	O
memory	O
over-provisioning	O
,	O
the	O
endurance	O
of	O
a	O
storage	O
system	O
can	O
be	O
tuned	O
to	O
serve	O
specific	O
requirements	O
.	O
</s>
<s>
In	O
order	O
to	O
compute	O
the	O
longevity	O
of	O
the	O
NANDflash	O
,	O
one	O
must	O
account	O
for	O
the	O
size	O
of	O
the	O
memory	B-Architecture
chip	I-Architecture
,	O
the	O
type	O
of	O
memory	O
(	O
e.g.	O
</s>
<s>
SLC/MLC/TLC	O
)	O
,	O
and	O
use	O
pattern	O
.	O
</s>
<s>
As	O
the	O
number	O
of	O
bits	O
per	O
cell	B-Algorithm
increases	O
,	O
the	O
performance	O
of	O
NAND	O
flash	O
may	O
degrade	O
,	O
increasing	O
random	B-General_Concept
read	I-General_Concept
times	O
to	O
100μs	O
for	O
TLC	O
NAND	O
which	O
is	O
4	O
times	O
the	O
time	O
required	O
in	O
SLC	O
NAND	O
,	O
and	O
twice	O
the	O
time	O
required	O
in	O
MLC	B-Device
NAND	O
,	O
for	O
random	B-General_Concept
reads	I-General_Concept
.	O
</s>
<s>
Because	O
of	O
the	O
particular	O
characteristics	O
of	O
flash	B-Device
memory	I-Device
,	O
it	O
is	O
best	O
used	O
with	O
either	O
a	O
controller	B-Device
to	O
perform	O
wear	B-Application
leveling	I-Application
and	O
error	B-Error_Name
correction	I-Error_Name
or	O
specifically	O
designed	O
flash	O
file	O
systems	O
,	O
which	O
spread	O
writes	O
over	O
the	O
media	O
and	O
deal	O
with	O
the	O
long	O
erase	O
times	O
of	O
NORflash	O
blocks	O
.	O
</s>
<s>
The	O
basic	O
concept	O
behind	O
flash	O
file	O
systems	O
is	O
the	O
following	O
:	O
when	O
the	O
flash	O
store	O
is	O
to	O
be	O
updated	O
,	O
the	O
file	O
system	O
will	O
write	O
a	O
new	O
copy	O
of	O
the	O
changed	O
data	O
to	O
a	O
fresh	O
block	B-General_Concept
,	O
remap	O
the	O
file	O
pointers	O
,	O
then	O
erase	O
the	O
old	O
block	B-General_Concept
later	O
when	O
it	O
has	O
time	O
.	O
</s>
<s>
In	O
practice	O
,	O
flash	O
file	O
systems	O
are	O
used	O
only	O
for	O
memory	B-Application
technology	I-Application
devices	I-Application
(	O
MTDs	O
)	O
,	O
which	O
are	O
embedded	B-Architecture
flash	B-Device
memories	I-Device
that	O
do	O
not	O
have	O
a	O
controller	B-Device
.	O
</s>
<s>
Removable	O
flash	B-Device
memory	I-Device
cards	I-Device
,	O
SSDs	B-Device
,	O
eMMC/eUFS	O
chips	O
and	O
USB	B-Protocol
flash	O
drives	O
have	O
built-in	O
controllers	O
to	O
perform	O
wear	B-Application
leveling	I-Application
and	O
error	B-Error_Name
correction	I-Error_Name
so	O
use	O
of	O
a	O
specific	O
flash	O
file	O
system	O
may	O
not	O
add	O
benefit	O
.	O
</s>
<s>
The	O
capacity	O
scaling	O
(	O
increase	O
)	O
of	O
flash	B-Device
chips	I-Device
used	O
to	O
follow	O
Moore	O
's	O
law	O
because	O
they	O
are	O
manufactured	O
with	O
many	O
of	O
the	O
same	O
integrated	O
circuits	O
techniques	O
and	O
equipment	O
.	O
</s>
<s>
Consumer	O
flash	B-Device
storage	I-Device
devices	O
typically	O
are	O
advertised	O
with	O
usable	O
sizes	O
expressed	O
as	O
a	O
small	O
integer	O
power	O
of	O
two	O
(	O
2	O
,	O
4	O
,	O
8	O
,	O
etc	O
.	O
)	O
</s>
<s>
This	O
includes	O
SSDs	B-Device
marketed	O
as	O
hard	B-Device
drive	I-Device
replacements	O
,	O
in	O
accordance	O
with	O
traditional	O
hard	B-Device
drives	I-Device
,	O
which	O
use	O
decimal	O
prefixes	O
.	O
</s>
<s>
Thus	O
,	O
an	O
SSD	B-Device
marked	O
as	O
"	O
64GB	O
"	O
is	O
at	O
least	O
bytes	B-Application
(	O
64GB	O
)	O
.	O
</s>
<s>
Most	O
users	O
will	O
have	O
slightly	O
less	O
capacity	O
than	O
this	O
available	O
for	O
their	O
files	O
,	O
due	O
to	O
the	O
space	O
taken	O
by	O
file	O
system	O
metadata	O
and	O
because	O
some	O
operating	O
systems	O
report	O
SSD	B-Device
capacity	O
using	O
binary	O
prefixes	O
which	O
are	O
somewhat	O
larger	O
than	O
conventional	O
prefixes	O
.	O
</s>
<s>
The	O
flash	B-Device
memory	I-Device
chips	O
inside	O
them	O
are	O
sized	O
in	O
strict	O
binary	O
multiples	O
,	O
but	O
the	O
actual	O
total	O
capacity	O
of	O
the	O
chips	O
is	O
not	O
usable	O
at	O
the	O
drive	O
interface	O
.	O
</s>
<s>
It	O
is	O
considerably	O
larger	O
than	O
the	O
advertised	O
capacity	O
in	O
order	O
to	O
allow	O
for	O
distribution	O
of	O
writes	O
(	O
wear	B-Application
leveling	I-Application
)	O
,	O
for	O
sparing	O
,	O
for	O
error	B-Error_Name
correction	I-Error_Name
codes	I-Error_Name
,	O
and	O
for	O
other	O
metadata	O
needed	O
by	O
the	O
device	O
's	O
internal	O
firmware	B-Application
.	O
</s>
<s>
In	O
2005	O
,	O
Toshiba	O
and	O
SanDisk	O
developed	O
a	O
NANDflash	O
chip	O
capable	O
of	O
storing	O
1GB	O
of	O
data	O
using	O
multi-level	B-Device
cell	I-Device
(	O
MLC	B-Device
)	O
technology	O
,	O
capable	O
of	O
storing	O
two	O
bits	O
of	O
data	O
per	O
cell	B-Algorithm
.	O
</s>
<s>
In	O
September	O
2005	O
,	O
Samsung	B-Application
Electronics	O
announced	O
that	O
it	O
had	O
developed	O
the	O
world	O
's	O
first	O
2GB	O
chip	O
.	O
</s>
<s>
In	O
March	O
2006	O
,	O
Samsung	B-Application
announced	O
flash	O
hard	B-Device
drives	I-Device
with	O
a	O
capacity	O
of	O
4GB	O
,	O
essentially	O
the	O
same	O
order	O
of	O
magnitude	O
as	O
smaller	O
laptop	B-Device
hard	I-Device
drives	I-Device
,	O
and	O
in	O
September	O
2006	O
,	O
Samsung	B-Application
announced	O
an	O
8GB	O
chip	O
produced	O
using	O
a	O
40nm	O
manufacturing	O
process	O
.	O
</s>
<s>
A	O
joint	O
development	O
at	O
Intel	O
and	O
Micron	O
will	O
allow	O
the	O
production	O
of	O
32-layer	O
3.5	O
terabyte	O
(	O
TB	O
)	O
NANDflash	O
sticks	O
and	O
10TB	O
standard-sized	O
SSDs	B-Device
.	O
</s>
<s>
The	O
device	O
includes	O
5	O
packages	B-Algorithm
of	O
16	O
×	O
48GBTLC	O
dies	O
,	O
using	O
a	O
floating	B-Algorithm
gate	I-Algorithm
cell	B-Algorithm
design	O
.	O
</s>
<s>
Flash	B-Device
chips	I-Device
continue	O
to	O
be	O
manufactured	O
with	O
capacities	O
under	O
or	O
around	O
1MB	O
(	O
e.g.	O
</s>
<s>
for	O
BIOS-ROMs	O
and	O
embedded	B-Architecture
applications	O
)	O
.	O
</s>
<s>
In	O
July	O
2016	O
,	O
Samsung	B-Application
announced	O
the	O
4	O
TB	O
Samsung	B-Application
850	O
EVO	O
which	O
utilizes	O
their	O
256Gbit	O
48-layer	O
TLC	O
3D	O
V-NAND	O
.	O
</s>
<s>
In	O
August	O
2016	O
,	O
Samsung	B-Application
announced	O
a	O
32TB	O
2.5-inch	O
SASSSD	O
based	O
on	O
their	O
512Gbit	O
64-layer	O
TLC	O
3DV-NAND	O
.	O
</s>
<s>
Further	O
,	O
Samsung	B-Application
expects	O
to	O
unveil	O
SSDs	B-Device
with	O
up	O
to	O
100TB	O
of	O
storage	O
by	O
2020	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
devices	O
are	O
typically	O
much	O
faster	O
at	O
reading	O
than	O
writing	O
.	O
</s>
<s>
Even	O
when	O
the	O
only	O
change	O
to	O
manufacturing	O
is	O
die-shrink	O
,	O
the	O
absence	O
of	O
an	O
appropriate	O
controller	B-Device
can	O
result	O
in	O
degraded	O
speeds	O
.	O
</s>
<s>
Serial	O
flash	O
is	O
a	O
small	O
,	O
low-power	O
flash	B-Device
memory	I-Device
that	O
provides	O
only	O
serial	O
access	O
to	O
the	O
data	O
-	O
rather	O
than	O
addressing	O
individual	O
bytes	B-Application
,	O
the	O
user	O
reads	O
or	O
writes	O
large	O
contiguous	O
groups	O
of	O
bytes	B-Application
in	O
the	O
address	O
space	O
serially	O
.	O
</s>
<s>
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
Bus	I-Architecture
(	O
SPI	O
)	O
is	O
a	O
typical	O
protocol	O
for	O
accessing	O
the	O
device	O
.	O
</s>
<s>
When	O
incorporated	O
into	O
an	O
embedded	B-Architecture
system	I-Architecture
,	O
serial	O
flash	O
requires	O
fewer	O
wires	O
on	O
the	O
PCB	O
than	O
parallel	O
flash	B-Device
memories	I-Device
,	O
since	O
it	O
transmits	O
and	O
receives	O
data	O
one	O
bit	O
at	O
a	O
time	O
.	O
</s>
<s>
Many	O
ASICs	O
are	O
pad-limited	O
,	O
meaning	O
that	O
the	O
size	O
of	O
the	O
die	O
is	O
constrained	O
by	O
the	O
number	O
of	O
wire	B-Algorithm
bond	I-Algorithm
pads	O
,	O
rather	O
than	O
the	O
complexity	O
and	O
number	O
of	O
gates	O
used	O
for	O
the	O
device	O
logic	O
.	O
</s>
<s>
Eliminating	O
bond	O
pads	O
thus	O
permits	O
a	O
more	O
compact	O
integrated	O
circuit	O
,	O
on	O
a	O
smaller	O
die	O
;	O
this	O
increases	O
the	O
number	O
of	O
dies	O
that	O
may	O
be	O
fabricated	O
on	O
a	O
wafer	B-Architecture
,	O
and	O
thus	O
reduces	O
the	O
cost	O
per	O
die	O
.	O
</s>
<s>
Reducing	O
the	O
number	O
of	O
external	O
pins	O
also	O
reduces	O
assembly	O
and	O
packaging	B-Algorithm
costs	O
.	O
</s>
<s>
Smaller	O
and	O
lower	O
pin-count	O
packages	B-Algorithm
occupy	O
less	O
PCB	O
area	O
.	O
</s>
<s>
Lower	O
pin-count	O
devices	O
simplify	O
PCB	B-Algorithm
routing	I-Algorithm
.	O
</s>
<s>
The	O
first	O
type	O
is	O
characterized	O
by	O
small	O
pages	O
and	O
one	O
or	O
more	O
internal	O
SRAM	B-Architecture
page	O
buffers	O
allowing	O
a	O
complete	O
page	O
to	O
be	O
read	O
to	O
the	O
buffer	O
,	O
partially	O
modified	O
,	O
and	O
then	O
written	O
back	O
(	O
for	O
example	O
,	O
the	O
Atmel	O
AT45	B-General_Concept
DataFlash	B-General_Concept
or	O
the	O
Micron	O
Technology	O
Page	O
Erase	O
NORFlash	O
)	O
.	O
</s>
<s>
Since	O
this	O
type	O
of	O
SPI	O
flash	O
lacks	O
an	O
internal	O
SRAM	B-Architecture
buffer	O
,	O
the	O
complete	O
page	O
must	O
be	O
read	O
out	O
and	O
modified	O
before	O
being	O
written	O
back	O
,	O
making	O
it	O
slow	O
to	O
manage	O
.	O
</s>
<s>
The	O
two	O
types	O
are	O
not	O
easily	O
exchangeable	O
,	O
since	O
they	O
do	O
not	O
have	O
the	O
same	O
pinout	B-Application
,	O
and	O
the	O
command	O
sets	O
are	O
incompatible	O
.	O
</s>
<s>
Most	O
FPGAs	B-Architecture
are	O
based	O
on	O
SRAM	B-Architecture
configuration	O
cells	O
and	O
require	O
an	O
external	O
configuration	O
device	O
,	O
often	O
a	O
serial	O
flash	B-Device
chip	I-Device
,	O
to	O
reload	O
the	O
configuration	O
bitstream	O
every	O
power	O
cycle	O
.	O
</s>
<s>
Conversely	O
,	O
modern	O
SRAM	B-Architecture
offers	O
access	B-General_Concept
times	I-General_Concept
below	O
10ns	O
,	O
while	O
DDR2	O
SDRAM	O
offers	O
access	B-General_Concept
times	I-General_Concept
below	O
20ns	O
.	O
</s>
<s>
Because	O
of	O
this	O
,	O
it	O
is	O
often	O
desirable	O
to	O
shadow	B-General_Concept
code	O
stored	O
in	O
flash	O
into	O
RAM	O
;	O
that	O
is	O
,	O
the	O
code	O
is	O
copied	O
from	O
flash	O
into	O
RAM	O
before	O
execution	O
,	O
so	O
that	O
the	O
CPU	O
may	O
access	O
it	O
at	O
full	O
speed	O
.	O
</s>
<s>
Device	O
firmware	B-Application
may	O
be	O
stored	O
in	O
a	O
serial	O
flash	B-Device
chip	I-Device
,	O
and	O
then	O
copied	O
into	O
SDRAM	O
or	O
SRAM	B-Architecture
when	O
the	O
device	O
is	O
powered-up	O
.	O
</s>
<s>
Once	O
it	O
is	O
decided	O
to	O
read	O
the	O
firmware	B-Application
in	O
as	O
one	O
big	O
block	B-General_Concept
it	O
is	O
common	O
to	O
add	O
compression	O
to	O
allow	O
a	O
smaller	O
flash	B-Device
chip	I-Device
to	O
be	O
used	O
.	O
</s>
<s>
Since	O
2005	O
,	O
many	O
devices	O
use	O
serial	O
NOR	O
flash	O
to	O
deprecate	O
parallel	O
NOR	O
flash	O
for	O
firmware	B-Application
storage	O
.	O
</s>
<s>
Typical	O
applications	O
for	O
serial	O
flash	O
include	O
storing	O
firmware	B-Application
for	O
hard	B-Device
drives	I-Device
,	O
Ethernet	O
network	O
interface	O
adapters	O
,	O
DSL	B-Device
modems	I-Device
,	O
etc	O
.	O
</s>
<s>
One	O
more	O
recent	O
application	O
for	O
flash	B-Device
memory	I-Device
is	O
as	O
a	O
replacement	O
for	O
hard	B-Device
disks	I-Device
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
does	O
not	O
have	O
the	O
mechanical	O
limitations	O
and	O
latencies	O
of	O
hard	B-Device
drives	I-Device
,	O
so	O
a	O
solid-state	B-Device
drive	I-Device
(	O
SSD	B-Device
)	O
is	O
attractive	O
when	O
considering	O
speed	O
,	O
noise	O
,	O
power	O
consumption	O
,	O
and	O
reliability	O
.	O
</s>
<s>
Flash	O
drives	O
are	O
gaining	O
traction	O
as	O
mobile	B-Application
device	I-Application
secondary	O
storage	O
devices	O
;	O
they	O
are	O
also	O
used	O
as	O
substitutes	O
for	O
hard	B-Device
drives	I-Device
in	O
high-performance	O
desktop	O
computers	O
and	O
some	O
servers	O
with	O
RAID	B-Architecture
and	O
SAN	O
architectures	O
.	O
</s>
<s>
There	O
remain	O
some	O
aspects	O
of	O
flash-based	O
SSDs	B-Device
that	O
make	O
them	O
unattractive	O
.	O
</s>
<s>
The	O
cost	O
per	O
gigabyte	O
of	O
flash	B-Device
memory	I-Device
remains	O
significantly	O
higher	O
than	O
that	O
of	O
hard	B-Device
disks	I-Device
.	O
</s>
<s>
Also	O
flash	B-Device
memory	I-Device
has	O
a	O
finite	O
number	O
of	O
P/E	O
(	O
program/erase	O
)	O
cycles	O
,	O
but	O
this	O
seems	O
to	O
be	O
currently	O
under	O
control	O
since	O
warranties	O
on	O
flash-based	O
SSDs	B-Device
are	O
approaching	O
those	O
of	O
current	O
hard	B-Device
drives	I-Device
.	O
</s>
<s>
In	O
addition	O
,	O
deleted	O
files	O
on	O
SSDs	B-Device
can	O
remain	O
for	O
an	O
indefinite	O
period	O
of	O
time	O
before	O
being	O
overwritten	O
by	O
fresh	O
data	O
;	O
erasure	O
or	O
shred	O
techniques	O
or	O
software	O
that	O
work	O
well	O
on	O
magnetic	O
hard	B-Device
disk	I-Device
drives	I-Device
have	O
no	O
effect	O
on	O
SSDs	B-Device
,	O
compromising	O
security	O
and	O
forensic	O
examination	O
.	O
</s>
<s>
However	O
,	O
due	O
to	O
the	O
so-called	O
TRIM	O
command	O
employed	O
by	O
most	O
solid	B-Device
state	I-Device
drives	I-Device
,	O
which	O
marks	O
the	O
logical	O
block	B-General_Concept
addresses	O
occupied	O
by	O
the	O
deleted	O
file	O
as	O
unused	O
to	O
enable	O
garbage	B-General_Concept
collection	I-General_Concept
,	O
data	O
recovery	O
software	O
is	O
not	O
able	O
to	O
restore	O
files	O
deleted	O
from	O
such	O
.	O
</s>
<s>
For	O
relational	O
databases	O
or	O
other	O
systems	O
that	O
require	O
ACID	O
transactions	O
,	O
even	O
a	O
modest	O
amount	O
of	O
flash	B-Device
storage	I-Device
can	O
offer	O
vast	O
speedups	O
over	O
arrays	O
of	O
disk	B-General_Concept
drives	I-General_Concept
.	O
</s>
<s>
In	O
May	O
2006	O
,	O
Samsung	B-Application
Electronics	O
announced	O
two	O
flash-memory	O
based	O
PCs	O
,	O
the	O
Q1-SSD	O
and	O
Q30-SSD	O
were	O
expected	O
to	O
become	O
available	O
in	O
June	O
2006	O
,	O
both	O
of	O
which	O
used	O
32GB	O
SSDs	B-Device
,	O
and	O
were	O
at	O
least	O
initially	O
available	O
only	O
in	O
South	O
Korea	O
.	O
</s>
<s>
The	O
Q1-SSD	O
and	O
Q30-SSD	O
launch	O
was	O
delayed	O
and	O
finally	O
was	O
shipped	O
in	O
late	O
August	O
2006	O
.	O
</s>
<s>
The	O
first	O
flash-memory	O
based	O
PC	O
to	O
become	O
available	O
was	O
the	O
Sony	O
Vaio	O
UX90	O
,	O
announced	O
for	O
pre-order	O
on	O
27	O
June	O
2006	O
and	O
began	O
to	O
be	O
shipped	O
in	O
Japan	O
on	O
3	O
July	O
2006	O
with	O
a	O
16Gb	O
flash	B-Device
memory	I-Device
hard	B-Device
drive	I-Device
.	O
</s>
<s>
A	O
solid-state	B-Device
drive	I-Device
was	O
offered	O
as	O
an	O
option	O
with	O
the	O
first	O
MacBook	B-Device
Air	I-Device
introduced	O
in	O
2008	O
,	O
and	O
from	O
2010	O
onwards	O
,	O
all	O
models	O
were	O
shipped	O
with	O
an	O
SSD	B-Device
.	O
</s>
<s>
Starting	O
in	O
late	O
2011	O
,	O
as	O
part	O
of	O
Intel	O
's	O
Ultrabook	B-Device
initiative	O
,	O
an	O
increasing	O
number	O
of	O
ultra-thin	O
laptops	O
are	O
being	O
shipped	O
with	O
SSDs	B-Device
standard	O
.	O
</s>
<s>
There	O
are	O
also	O
hybrid	O
techniques	O
such	O
as	O
hybrid	B-Device
drive	I-Device
and	O
ReadyBoost	O
that	O
attempt	O
to	O
combine	O
the	O
advantages	O
of	O
both	O
technologies	O
,	O
using	O
flash	O
as	O
a	O
high-speed	O
non-volatile	B-General_Concept
cache	B-General_Concept
for	O
files	O
on	O
the	O
disk	O
that	O
are	O
often	O
referenced	O
,	O
but	O
rarely	O
modified	O
,	O
such	O
as	O
application	O
and	O
operating	O
system	O
executable	B-Application
files	I-Application
.	O
</s>
<s>
there	O
are	O
attempts	O
to	O
use	O
flash	B-Device
memory	I-Device
as	O
the	O
main	O
computer	B-General_Concept
memory	I-General_Concept
,	O
DRAM	O
.	O
</s>
<s>
Floating-gate	B-Algorithm
transistors	I-Algorithm
in	O
the	O
flash	B-Device
storage	I-Device
device	O
hold	O
charge	O
which	O
represents	O
data	O
.	O
</s>
<s>
It	O
is	O
unclear	O
how	O
long	O
data	O
on	O
flash	B-Device
memory	I-Device
will	O
persist	O
under	O
archival	O
conditions	O
(	O
i.e.	O
,	O
benign	O
temperature	O
and	O
humidity	O
with	O
infrequent	O
access	O
with	O
or	O
without	O
prophylactic	O
rewrite	O
)	O
.	O
</s>
<s>
Datasheets	O
of	O
Atmel	O
's	O
flash-based	O
"	O
ATmega	O
"	O
microcontrollers	B-Architecture
typically	O
promise	O
retention	O
times	O
of	O
20	O
years	O
at	O
85°C	O
(	O
185°F	O
)	O
and	O
100	O
years	O
at	O
25°C	O
(	O
77°F	O
)	O
.	O
</s>
<s>
The	O
retention	O
span	O
varies	O
among	O
types	O
and	O
models	O
of	O
flash	B-Device
storage	I-Device
.	O
</s>
<s>
When	O
supplied	O
with	O
power	O
and	O
idle	O
,	O
the	O
charge	O
of	O
the	O
transistors	O
holding	O
the	O
data	O
is	O
routinely	O
refreshed	O
by	O
the	O
firmware	B-Application
of	O
the	O
flash	B-Device
storage	I-Device
.	O
</s>
<s>
The	O
ability	O
to	O
retain	O
data	O
varies	O
among	O
flash	B-Device
storage	I-Device
devices	O
due	O
to	O
differences	O
in	O
firmware	B-Application
,	O
data	B-Application
redundancy	I-Application
,	O
and	O
error	B-Error_Name
correction	I-Error_Name
algorithms	O
.	O
</s>
<s>
Some	O
FPGAs	B-Architecture
are	O
based	O
on	O
flash	O
configuration	O
cells	O
that	O
are	O
used	O
directly	O
as	O
(	O
programmable	O
)	O
switches	O
to	O
connect	O
internal	O
elements	O
together	O
,	O
using	O
the	O
same	O
kind	O
of	O
floating-gate	B-Algorithm
transistor	I-Algorithm
as	O
the	O
flash	O
data	B-General_Concept
storage	I-General_Concept
cells	O
in	O
data	B-General_Concept
storage	I-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
One	O
source	O
states	O
that	O
,	O
in	O
2008	O
,	O
the	O
flash	B-Device
memory	I-Device
industry	O
includes	O
about	O
US	O
$9.1	O
billion	O
in	O
production	O
and	O
sales	O
.	O
</s>
<s>
Other	O
sources	O
put	O
the	O
flash	B-Device
memory	I-Device
market	O
at	O
a	O
size	O
of	O
more	O
than	O
US$20	O
billion	O
in	O
2006	O
,	O
accounting	O
for	O
more	O
than	O
eight	O
percent	O
of	O
the	O
overall	O
semiconductor	O
market	O
and	O
more	O
than	O
34	O
percent	O
of	O
the	O
total	O
semiconductor	B-Architecture
memory	I-Architecture
market	O
.	O
</s>
<s>
It	O
can	O
take	O
up	O
to	O
10	O
weeks	O
to	O
produce	O
a	O
flash	B-Device
memory	I-Device
chip	O
.	O
</s>
<s>
The	O
following	O
were	O
the	O
largest	O
NAND	O
flash	B-Device
memory	I-Device
manufacturers	O
,	O
as	O
of	O
the	O
first	O
quarter	O
of	O
2019	O
.	O
</s>
<s>
Samsung	B-Application
remains	O
the	O
largest	O
NAND	O
flash	B-Device
memory	I-Device
manufacturer	O
as	O
of	O
first	O
quarter	O
2022	O
.	O
</s>
<s>
In	O
addition	O
to	O
individual	O
flash	B-Device
memory	I-Device
chips	O
,	O
flash	B-Device
memory	I-Device
is	O
also	O
embedded	B-Architecture
in	O
microcontroller	B-Architecture
(	O
MCU	O
)	O
chips	O
and	O
system-on-chip	B-Architecture
(	O
SoC	O
)	O
devices	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
is	O
embedded	B-Architecture
in	O
ARM	B-Architecture
chips	I-Architecture
,	O
which	O
have	O
sold	O
150billion	O
units	O
worldwide	O
,	O
and	O
in	O
programmable	B-Application
system-on-chip	I-Application
(	O
PSoC	B-Application
)	O
devices	O
,	O
which	O
have	O
sold	O
1.1billion	O
units	O
.	O
</s>
<s>
This	O
adds	O
up	O
to	O
at	O
least	O
151.1billion	O
MCU	O
and	O
SoC	O
chips	O
with	O
embedded	B-Architecture
flash	B-Device
memory	I-Device
,	O
in	O
addition	O
to	O
the	O
45.4billion	O
known	O
individual	O
flash	B-Device
chip	I-Device
sales	O
,	O
totalling	O
at	O
least	O
196.5billion	O
chips	O
containing	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Due	O
to	O
its	O
relatively	O
simple	O
structure	O
and	O
high	O
demand	O
for	O
higher	O
capacity	O
,	O
NANDflash	O
memory	O
is	O
the	O
most	O
aggressively	O
scaled	B-Algorithm
technology	I-Algorithm
among	O
electronic	O
devices	O
.	O
</s>
<s>
The	O
heavy	O
competition	O
among	O
the	O
top	O
few	O
manufacturers	O
only	O
adds	O
to	O
the	O
aggressiveness	O
in	O
shrinking	O
the	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
design	O
rule	O
or	O
process	O
technology	O
node	O
.	O
</s>
<s>
As	O
the	O
MOSFET	B-Architecture
feature	O
size	O
of	O
flash	B-Device
memory	I-Device
cells	O
reaches	O
the	O
15	O
–	O
16nm	O
minimum	O
limit	O
,	O
further	O
flash	O
density	O
increases	O
will	O
be	O
driven	O
by	O
TLC	O
(	O
3bits/cell	O
)	O
combined	O
with	O
vertical	O
stacking	O
of	O
NAND	B-Device
memory	I-Device
planes	O
.	O
</s>
<s>
The	O
decrease	O
in	O
endurance	O
and	O
increase	O
in	O
uncorrectable	O
bit	O
error	O
rates	O
that	O
accompany	O
feature	O
size	O
shrinking	O
can	O
be	O
compensated	O
by	O
improved	O
error	B-Error_Name
correction	I-Error_Name
mechanisms	O
.	O
</s>
<s>
Many	O
promising	O
new	O
technologies	O
(	O
such	O
as	O
FeRAM	O
,	O
MRAM	B-General_Concept
,	O
PMC	B-General_Concept
,	O
PCM	B-Device
,	O
ReRAM	B-General_Concept
,	O
and	O
others	O
)	O
are	O
under	O
investigation	O
and	O
development	O
as	O
possible	O
more	O
scalable	O
replacements	O
for	O
flash	O
.	O
</s>
<s>
Date	O
of	O
introduction	O
Chip	O
name	O
Memory	O
Package	O
CapacityMegabits	O
(	O
Mb	O
)	O
,	O
Gigabits	O
(	O
Gb	O
)	O
,	O
Terabits	O
(	O
Tb	O
)	O
Flash	O
type	O
Cell	B-Algorithm
type	O
Layers	O
orStacks	O
of	O
Layers	O
Manufacturer(s )	O
Process	O
Area	O
Ref	O
1984	O
?	O
</s>
<s>
32	O
Mb	O
NAND	O
SLC	O
1	O
Hitachi	O
,	O
Samsung	B-Application
,	O
Toshiba	O
?	O
</s>
<s>
QLC	O
1	O
NEC	O
128	O
Mb	O
NAND	O
SLC	O
1	O
Samsung	B-Application
,	O
Hitachi	O
?	O
</s>
<s>
MLC	B-Device
1	O
Hitachi	O
1	O
2000	O
?	O
</s>
<s>
512	O
Mb	O
NAND	O
MLC	B-Device
1	O
Hitachi	O
?	O
</s>
<s>
1	O
Gibit	O
NAND	O
MLC	B-Device
1	O
Samsung	B-Application
1	O
Toshiba	O
,	O
SanDisk	O
160	O
nm	O
?	O
</s>
<s>
512	O
Mb	O
NROM	B-Algorithm
MLC	B-Device
1	O
Saifun	O
170	O
nm	O
?	O
</s>
<s>
2	O
Gb	O
NAND	O
SLC	O
1	O
Samsung	B-Application
,	O
Toshiba	O
?	O
</s>
<s>
128	O
Mb	O
NOR	O
MLC	B-Device
1	O
Intel	O
130	O
nm	O
?	O
</s>
<s>
1	O
Gb	O
NAND	O
MLC	B-Device
1	O
Hitachi	O
2004	O
?	O
</s>
<s>
8	O
Gb	O
NAND	O
SLC	O
1	O
Samsung	B-Application
60	O
nm	O
?	O
</s>
<s>
16	O
Gb	O
NAND	O
SLC	O
1	O
Samsung	B-Application
50	O
nm	O
?	O
</s>
<s>
32	O
Gb	O
NAND	O
SLC	O
1	O
Samsung	B-Application
40	O
nm	O
Apr-07	O
THGAM	O
128	O
Gb	O
Stacked	O
NAND	O
SLC	O
Toshiba	O
56	O
nm	O
252	O
mm²	O
Sep-07	O
?	O
</s>
<s>
TLC	O
Samsung	B-Application
20	O
nm	O
?	O
</s>
<s>
THGBM2	O
1	O
Tb	O
Stacked	O
NAND	O
QLC	O
Toshiba	O
32	O
nm	O
374	O
mm²	O
2011	O
KLMCG8GE4A	O
512	O
Gb	O
Stacked	O
NAND	O
MLC	B-Device
Samsung	B-Application
?	O
</s>
<s>
128	O
Gb	O
V-NAND	O
TLC	O
Samsung	B-Application
10	O
nm	O
?	O
</s>
<s>
256	O
Gb	O
V-NAND	O
TLC	O
Samsung	B-Application
?	O
</s>
<s>
2017	O
eUFS	B-Device
2.1	O
512	O
Gb	O
V-NAND	O
TLC	O
8	O
of	O
64	O
Samsung	B-Application
?	O
</s>
<s>
KLUFG8R1EM	O
4	O
Tb	O
Stacked	O
V-NAND	O
TLC	O
Samsung	B-Application
?	O
</s>
<s>
1	O
Tb	O
V-NAND	O
QLC	O
Samsung	B-Application
?	O
</s>
<s>
512	O
Gb	O
V-NAND	O
QLC	O
Samsung	B-Application
?	O
</s>
<s>
eUFS	B-Device
2.1	O
1	O
Tb	O
Stacked	O
V-NAND	O
QLC	O
16	O
of	O
64	O
Samsung	B-Application
?	O
</s>
