<s>
A	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
is	O
an	O
integrated	O
circuit	O
designed	O
to	O
be	O
configured	O
by	O
a	O
customer	O
or	O
a	O
designer	O
after	O
manufacturinghence	O
the	O
term	O
field-programmable	O
.	O
</s>
<s>
The	O
FPGA	B-Architecture
configuration	B-General_Concept
is	O
generally	O
specified	O
using	O
a	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
,	O
similar	O
to	O
that	O
used	O
for	O
an	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
.	O
</s>
<s>
Circuit	B-Application
diagrams	I-Application
were	O
previously	O
used	O
to	O
specify	O
the	O
configuration	B-General_Concept
,	O
but	O
this	O
is	O
increasingly	O
rare	O
due	O
to	O
the	O
advent	O
of	O
electronic	O
design	B-General_Concept
automation	O
tools	O
.	O
</s>
<s>
FPGAs	B-Architecture
contain	O
an	O
array	O
of	O
programmable	O
logic	O
blocks	O
,	O
and	O
a	O
hierarchy	O
of	O
reconfigurable	O
interconnects	B-General_Concept
allowing	O
blocks	O
to	O
be	O
wired	O
together	O
.	O
</s>
<s>
In	O
most	O
FPGAs	B-Architecture
,	O
logic	O
blocks	O
also	O
include	O
memory	B-Algorithm
elements	I-Algorithm
,	O
which	O
may	O
be	O
simple	O
flip-flops	B-General_Concept
or	O
more	O
complete	O
blocks	O
of	O
memory	B-General_Concept
.	O
</s>
<s>
Many	O
FPGAs	B-Architecture
can	O
be	O
reprogrammed	O
to	O
implement	O
different	O
logic	O
functions	O
,	O
allowing	O
flexible	O
reconfigurable	B-Architecture
computing	I-Architecture
as	O
performed	O
in	O
computer	O
software	O
.	O
</s>
<s>
FPGAs	B-Architecture
have	O
a	O
remarkable	O
role	O
in	O
embedded	B-Architecture
system	I-Architecture
development	O
due	O
to	O
their	O
capability	O
to	O
start	O
system	O
software	O
development	O
simultaneously	O
with	O
hardware	O
,	O
enable	O
system	O
performance	O
simulations	O
at	O
a	O
very	O
early	O
phase	O
of	O
the	O
development	O
,	O
and	O
allow	O
various	O
system	O
trials	O
and	O
design	B-General_Concept
iterations	O
before	O
finalizing	O
the	O
system	O
architecture	O
.	O
</s>
<s>
The	O
FPGA	B-Architecture
industry	O
sprouted	O
from	O
programmable	B-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
(	O
PROM	B-General_Concept
)	O
and	O
programmable	O
logic	O
devices	O
(	O
PLDs	O
)	O
.	O
</s>
<s>
Altera	O
was	O
founded	O
in	O
1983	O
and	O
delivered	O
the	O
industry	O
's	O
first	O
reprogrammable	O
logic	O
device	O
in	O
1984	O
–	O
the	O
EP300	O
–	O
which	O
featured	O
a	O
quartz	O
window	O
in	O
the	O
package	O
that	O
allowed	O
users	O
to	O
shine	O
an	O
ultra-violet	O
lamp	O
on	O
the	O
die	O
to	O
erase	O
the	O
EPROM	B-General_Concept
cells	O
that	O
held	O
the	O
device	O
configuration	B-General_Concept
.	O
</s>
<s>
Xilinx	O
produced	O
the	O
first	O
commercially	O
viable	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
in	O
1985the	O
XC2064	O
.	O
</s>
<s>
The	O
XC2064	O
had	O
programmable	O
gates	O
and	O
programmable	O
interconnects	B-General_Concept
between	O
gates	O
,	O
the	O
beginnings	O
of	O
a	O
new	O
technology	O
and	O
market	O
.	O
</s>
<s>
The	O
XC2064	O
had	O
64	O
configurable	B-General_Concept
logic	O
blocks	O
(	O
CLBs	O
)	O
,	O
with	O
two	O
three-input	O
lookup	B-Data_Structure
tables	I-Data_Structure
(	O
LUTs	O
)	O
.	O
</s>
<s>
The	O
1990s	O
were	O
a	O
period	O
of	O
rapid	O
growth	O
for	O
FPGAs	B-Architecture
,	O
both	O
in	O
circuit	O
sophistication	O
and	O
the	O
volume	O
of	O
production	O
.	O
</s>
<s>
In	O
the	O
early	O
1990s	O
,	O
FPGAs	B-Architecture
were	O
primarily	O
used	O
in	O
telecommunications	O
and	O
networking	B-Architecture
.	O
</s>
<s>
By	O
the	O
end	O
of	O
the	O
decade	O
,	O
FPGAs	B-Architecture
found	O
their	O
way	O
into	O
consumer	O
,	O
automotive	O
,	O
and	O
industrial	O
applications	O
.	O
</s>
<s>
By	O
2013	O
,	O
Altera	O
(	O
31	O
percent	O
)	O
,	O
Actel	O
(	O
10	O
percent	O
)	O
and	O
Xilinx	O
(	O
36	O
percent	O
)	O
together	O
represented	O
approximately	O
77	O
percent	O
of	O
the	O
FPGA	B-Architecture
market	O
.	O
</s>
<s>
Companies	O
like	O
Microsoft	O
have	O
started	O
to	O
use	O
FPGAs	B-Architecture
to	O
accelerate	B-General_Concept
high-performance	O
,	O
computationally	O
intensive	O
systems	O
(	O
like	O
the	O
data	B-Operating_System
centers	I-Operating_System
that	O
operate	O
their	O
Bing	B-Application
search	I-Application
engine	I-Application
)	O
,	O
due	O
to	O
the	O
performance	O
per	O
watt	O
advantage	O
FPGAs	B-Architecture
deliver	O
.	O
</s>
<s>
Microsoft	O
began	O
using	O
FPGAs	B-Architecture
to	O
accelerate	B-General_Concept
Bing	B-Application
in	O
2014	O
,	O
and	O
in	O
2018	O
began	O
deploying	O
FPGAs	B-Architecture
across	O
other	O
data	B-Operating_System
center	I-Operating_System
workloads	O
for	O
their	O
Azure	B-Application
cloud	B-Architecture
computing	I-Architecture
platform	I-Architecture
.	O
</s>
<s>
The	O
following	O
timelines	O
indicate	O
progress	O
in	O
different	O
aspects	O
of	O
FPGA	B-Architecture
design	B-General_Concept
.	O
</s>
<s>
A	O
design	B-General_Concept
start	O
is	O
a	O
new	O
custom	O
design	B-General_Concept
for	O
implementation	O
on	O
an	O
FPGA	B-Architecture
.	O
</s>
<s>
Contemporary	O
FPGAs	B-Architecture
have	O
ample	O
logic	O
gates	O
and	O
RAM	O
blocks	O
to	O
implement	O
complex	O
digital	O
computations	O
.	O
</s>
<s>
FPGAs	B-Architecture
can	O
be	O
used	O
to	O
implement	O
any	O
logical	O
function	O
that	O
an	O
ASIC	O
can	O
perform	O
.	O
</s>
<s>
The	O
ability	O
to	O
update	O
the	O
functionality	O
after	O
shipping	O
,	O
partial	O
re-configuration	O
of	O
a	O
portion	O
of	O
the	O
design	B-General_Concept
and	O
the	O
low	O
non-recurring	O
engineering	O
costs	O
relative	O
to	O
an	O
ASIC	O
design	B-General_Concept
(	O
notwithstanding	O
the	O
generally	O
higher	O
unit	O
cost	O
)	O
,	O
offer	O
advantages	O
for	O
many	O
applications	O
.	O
</s>
<s>
As	O
FPGA	B-Architecture
designs	O
employ	O
very	O
fast	O
I/O	O
rates	O
and	O
bidirectional	O
data	B-General_Concept
buses	I-General_Concept
,	O
it	O
becomes	O
a	O
challenge	O
to	O
verify	O
correct	O
timing	O
of	O
valid	O
data	O
within	O
setup	B-General_Concept
time	I-General_Concept
and	O
hold	O
time	O
.	O
</s>
<s>
Floor	O
planning	O
helps	O
resource	O
allocation	O
within	O
FPGAs	B-Architecture
to	O
meet	O
these	O
timing	O
constraints	O
.	O
</s>
<s>
Some	O
FPGAs	B-Architecture
have	O
analog	O
features	O
in	O
addition	O
to	O
digital	O
functions	O
.	O
</s>
<s>
Also	O
common	O
are	O
quartz-crystal	O
oscillator	O
driver	O
circuitry	O
,	O
on-chip	O
resistance-capacitance	O
oscillators	O
,	O
and	O
phase-locked	O
loops	O
with	O
embedded	B-Architecture
voltage-controlled	O
oscillators	O
used	O
for	O
clock	O
generation	O
and	O
management	O
as	O
well	O
as	O
for	O
high-speed	O
serializer-deserializer	O
(	O
SERDES	O
)	O
transmit	O
clocks	O
and	O
receiver	O
clock	O
recovery	O
.	O
</s>
<s>
A	O
few	O
mixed	O
signal	O
FPGAs	B-Architecture
have	O
integrated	O
peripheral	O
analog-to-digital	O
converters	O
(	O
ADCs	O
)	O
and	O
digital-to-analog	O
converters	O
(	O
DACs	O
)	O
with	O
analog	O
signal	O
conditioning	O
blocks	O
allowing	O
them	O
to	O
operate	O
as	O
a	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
.	O
</s>
<s>
Such	O
devices	O
blur	O
the	O
line	O
between	O
an	O
FPGA	B-Architecture
,	O
which	O
carries	O
digital	O
ones	O
and	O
zeros	O
on	O
its	O
internal	O
programmable	O
interconnect	B-General_Concept
fabric	O
,	O
and	O
field-programmable	O
analog	O
array	O
(	O
FPAA	O
)	O
,	O
which	O
carries	O
analog	O
values	O
on	O
its	O
internal	O
programmable	O
interconnect	B-General_Concept
fabric	O
.	O
</s>
<s>
The	O
most	O
common	O
FPGA	B-Architecture
architecture	O
consists	O
of	O
an	O
array	O
of	O
logic	O
blocks	O
called	O
configurable	B-General_Concept
logic	O
blocks	O
(	O
CLBs	O
)	O
,	O
or	O
logic	O
array	O
blocks	O
(	O
LABs	O
)	O
,	O
depending	O
on	O
vendor	O
,	O
I/O	B-Architecture
pads	I-Architecture
,	O
and	O
routing	B-Algorithm
channels	O
.	O
</s>
<s>
Generally	O
,	O
all	O
the	O
routing	B-Algorithm
channels	O
have	O
the	O
same	O
width	O
(	O
number	O
of	O
signals	O
)	O
.	O
</s>
<s>
Multiple	O
I/O	B-Architecture
pads	I-Architecture
may	O
fit	O
into	O
the	O
height	O
of	O
one	O
row	O
or	O
the	O
width	O
of	O
one	O
column	O
in	O
the	O
array	O
.	O
</s>
<s>
"	O
An	O
application	O
circuit	O
must	O
be	O
mapped	O
into	O
an	O
FPGA	B-Architecture
with	O
adequate	O
resources	O
.	O
</s>
<s>
While	O
the	O
number	O
of	O
logic	O
blocks	O
and	O
I/Os	O
required	O
is	O
easily	O
determined	O
from	O
the	O
design	B-General_Concept
,	O
the	O
number	O
of	O
routing	B-Algorithm
channels	O
needed	O
may	O
vary	O
considerably	O
even	O
among	O
designs	O
with	O
the	O
same	O
amount	O
of	O
logic	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
crossbar	O
switch	O
requires	O
much	O
more	O
routing	B-Algorithm
than	O
a	O
systolic	B-Architecture
array	I-Architecture
with	O
the	O
same	O
gate	O
count	O
.	O
</s>
<s>
Since	O
unused	O
routing	B-Algorithm
channels	O
increase	O
the	O
cost	O
(	O
and	O
decrease	O
the	O
performance	O
)	O
of	O
the	O
FPGA	B-Architecture
without	O
providing	O
any	O
benefit	O
,	O
FPGA	B-Architecture
manufacturers	O
try	O
to	O
provide	O
just	O
enough	O
channels	O
so	O
that	O
most	O
designs	O
that	O
will	O
fit	O
in	O
terms	O
of	O
lookup	B-Data_Structure
tables	I-Data_Structure
(	O
LUTs	O
)	O
and	O
I/Os	O
can	O
be	O
routed	B-Algorithm
.	O
</s>
<s>
A	O
typical	O
cell	O
consists	O
of	O
a	O
4-input	O
LUT	O
,	O
a	O
full	O
adder	O
(	O
FA	O
)	O
and	O
a	O
D-type	O
flip-flop	B-General_Concept
.	O
</s>
<s>
In	O
normal	O
mode	O
those	O
are	O
combined	O
into	O
a	O
4-input	O
LUT	O
through	O
the	O
first	O
multiplexer	B-Protocol
(	O
mux	O
)	O
.	O
</s>
<s>
The	O
output	O
can	O
be	O
either	O
synchronous	B-Application
or	O
asynchronous	B-Application
,	O
depending	O
on	O
the	O
programming	O
of	O
the	O
third	O
mux	O
.	O
</s>
<s>
Modern	O
FPGA	B-Architecture
families	O
expand	O
upon	O
the	O
above	O
capabilities	O
to	O
include	O
higher	O
level	O
functionality	O
fixed	O
in	O
silicon	O
.	O
</s>
<s>
Having	O
these	O
common	O
functions	O
embedded	B-Architecture
in	O
the	O
circuit	O
reduces	O
the	O
area	O
required	O
and	O
gives	O
those	O
functions	O
increased	O
speed	O
compared	O
to	O
building	O
them	O
from	O
logical	O
primitives	O
.	O
</s>
<s>
Examples	O
of	O
these	O
include	O
multipliers	O
,	O
generic	O
DSP	B-General_Concept
blocks	I-General_Concept
,	O
embedded	B-Architecture
processors	I-Architecture
,	O
high-speed	O
I/O	O
logic	O
and	O
embedded	B-Architecture
memories	B-General_Concept
.	O
</s>
<s>
Higher-end	O
FPGAs	B-Architecture
can	O
contain	O
high	O
speed	O
multi-gigabit	O
transceivers	O
and	O
hard	O
IP	B-Architecture
cores	I-Architecture
such	O
as	O
processor	O
cores	O
,	O
Ethernet	O
medium	B-Protocol
access	I-Protocol
control	I-Protocol
units	I-Protocol
,	O
PCI/PCI	O
Express	O
controllers	O
,	O
and	O
external	O
memory	B-General_Concept
controllers	O
.	O
</s>
<s>
These	O
cores	O
exist	O
alongside	O
the	O
programmable	O
fabric	O
,	O
but	O
they	O
are	O
built	O
out	O
of	O
transistors	B-Application
instead	O
of	O
LUTs	O
so	O
they	O
have	O
ASIC-level	O
performance	O
and	O
power	O
consumption	O
without	O
consuming	O
a	O
significant	O
amount	O
of	O
fabric	O
resources	O
,	O
leaving	O
more	O
of	O
the	O
fabric	O
free	O
for	O
the	O
application-specific	O
logic	O
.	O
</s>
<s>
The	O
multi-gigabit	O
transceivers	O
also	O
contain	O
high	O
performance	O
analog	O
input	O
and	O
output	O
circuitry	O
along	O
with	O
high-speed	O
serializers	B-Protocol
and	O
deserializers	O
,	O
components	O
which	O
cannot	O
be	O
built	O
out	O
of	O
LUTs	O
.	O
</s>
<s>
Higher-level	O
physical	O
layer	O
(	O
PHY	O
)	O
functionality	O
such	O
as	O
line	B-Protocol
coding	I-Protocol
may	O
or	O
may	O
not	O
be	O
implemented	O
alongside	O
the	O
serializers	B-Protocol
and	O
deserializers	O
in	O
hard	O
logic	O
,	O
depending	O
on	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
An	O
alternate	O
approach	O
to	O
using	O
hard-macro	O
processors	O
is	O
to	O
make	O
use	O
of	O
soft	B-Device
processor	I-Device
IP	B-Architecture
cores	I-Architecture
that	O
are	O
implemented	O
within	O
the	O
FPGA	B-Architecture
logic	O
.	O
</s>
<s>
Nios	B-Device
II	I-Device
,	O
MicroBlaze	B-Device
and	O
Mico32	B-Device
are	O
examples	O
of	O
popular	O
softcore	B-Device
processors	I-Device
.	O
</s>
<s>
Many	O
modern	O
FPGAs	B-Architecture
are	O
programmed	O
at	O
"	O
run	O
time	O
"	O
,	O
which	O
has	O
led	O
to	O
the	O
idea	O
of	O
reconfigurable	B-Architecture
computing	I-Architecture
or	O
reconfigurable	B-Architecture
systems	I-Architecture
–	O
CPUs	B-General_Concept
that	O
reconfigure	O
themselves	O
to	O
suit	O
the	O
task	O
at	O
hand	O
.	O
</s>
<s>
Additionally	O
,	O
new	O
,	O
non-FPGA	O
architectures	O
are	O
beginning	O
to	O
emerge	O
.	O
</s>
<s>
Software-configurable	O
microprocessors	B-Architecture
such	O
as	O
the	O
Stretch	O
S5000	O
adopt	O
a	O
hybrid	O
approach	O
by	O
providing	O
an	O
array	O
of	O
processor	O
cores	O
and	O
FPGA-like	O
programmable	O
cores	O
on	O
the	O
same	O
chip	O
.	O
</s>
<s>
In	O
2012	O
the	O
coarse-grained	O
architectural	B-General_Concept
approach	O
was	O
taken	O
a	O
step	O
further	O
by	O
combining	O
the	O
logic	O
blocks	O
and	O
interconnects	B-General_Concept
of	O
traditional	O
FPGAs	B-Architecture
with	O
embedded	B-Architecture
microprocessors	I-Architecture
and	O
related	O
peripherals	O
to	O
form	O
a	O
complete	O
"	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
programmable	I-Architecture
chip	I-Architecture
"	O
.	O
</s>
<s>
This	O
work	O
mirrors	O
the	O
architecture	O
created	O
by	O
Ron	O
Perloff	O
and	O
Hanan	O
Potash	O
of	O
Burroughs	O
Advanced	O
Systems	O
Group	O
in	O
1982	O
which	O
combined	O
a	O
reconfigurable	O
CPU	B-General_Concept
architecture	I-General_Concept
on	O
a	O
single	O
chip	O
called	O
the	O
SB24	O
.	O
</s>
<s>
Examples	O
of	O
such	O
hybrid	O
technologies	O
can	O
be	O
found	O
in	O
the	O
Xilinx	O
Zynq-7000	O
all	O
Programmable	B-Application
SoC	I-Application
,	O
which	O
includes	O
a	O
1.0GHz	O
dual-core	B-Architecture
ARM	B-Application
Cortex-A9	I-Application
MPCore	I-Application
processor	O
embedded	B-Architecture
within	O
the	O
FPGA	B-Architecture
's	O
logic	O
fabric	O
or	O
in	O
the	O
Altera	O
Arria	O
V	O
FPGA	B-Architecture
,	O
which	O
includes	O
an	O
800MHz	O
dual-core	B-Architecture
ARM	B-Application
Cortex-A9	I-Application
MPCore	I-Application
.	O
</s>
<s>
The	O
Atmel	O
FPSLIC	O
is	O
another	O
such	O
device	O
,	O
which	O
uses	O
an	O
AVR	B-Architecture
processor	O
in	O
combination	O
with	O
Atmel	O
's	O
programmable	O
logic	O
architecture	O
.	O
</s>
<s>
The	O
Microsemi	O
SmartFusion	O
devices	O
incorporate	O
an	O
ARM	O
Cortex-M3	O
hard	O
processor	O
core	O
(	O
with	O
up	O
to	O
512kB	O
of	O
flash	B-Device
and	O
64kB	O
of	O
RAM	O
)	O
and	O
analog	O
peripherals	O
such	O
as	O
a	O
multi-channel	O
analog-to-digital	O
converters	O
and	O
digital-to-analog	O
converters	O
to	O
their	O
flash	B-Device
memory-based	O
FPGA	B-Architecture
fabric	O
.	O
</s>
<s>
Most	O
of	O
the	O
circuitry	O
built	O
inside	O
of	O
an	O
FPGA	B-Architecture
is	O
synchronous	B-Application
circuitry	O
that	O
requires	O
a	O
clock	O
signal	O
.	O
</s>
<s>
FPGAs	B-Architecture
contain	O
dedicated	O
global	O
and	O
regional	O
routing	B-Algorithm
networks	O
for	O
clock	O
and	O
reset	B-General_Concept
,	O
typically	O
as	O
an	O
incarnation	O
of	O
an	O
H	B-Algorithm
tree	I-Algorithm
,	O
so	O
they	O
can	O
be	O
delivered	O
with	O
minimal	O
skew	O
.	O
</s>
<s>
Also	O
,	O
FPGAs	B-Architecture
generally	O
contain	O
analog	O
phase-locked	O
loop	O
and/or	O
delay-locked	O
loop	O
components	O
to	O
synthesize	O
new	O
clock	O
frequencies	O
as	O
well	O
as	O
attenuate	O
jitter	O
.	O
</s>
<s>
FPGAs	B-Architecture
generally	O
contain	O
blocks	O
of	O
RAMs	O
that	O
are	O
capable	O
of	O
working	O
as	O
dual	B-General_Concept
port	I-General_Concept
RAMs	I-General_Concept
with	O
different	O
clocks	O
,	O
aiding	O
in	O
the	O
construction	O
of	O
building	O
FIFOs	B-Operating_System
and	O
dual	O
port	O
buffers	O
that	O
connect	O
differing	O
clock	O
domains	O
.	O
</s>
<s>
To	O
shrink	O
the	O
size	O
and	O
power	O
consumption	O
of	O
FPGAs	B-Architecture
,	O
vendors	O
such	O
as	O
Tabula	O
and	O
Xilinx	O
have	O
introduced	O
3D	B-Architecture
or	I-Architecture
stacked	I-Architecture
architectures	I-Architecture
.	O
</s>
<s>
Following	O
the	O
introduction	O
of	O
its	O
28	O
nm	O
7-series	O
FPGAs	B-Architecture
,	O
Xilinx	O
said	O
that	O
several	O
of	O
the	O
highest-density	O
parts	O
in	O
those	O
FPGA	B-Architecture
product	O
lines	O
will	O
be	O
constructed	O
using	O
multiple	O
dies	O
in	O
one	O
package	O
,	O
employing	O
technology	O
developed	O
for	O
3D	O
construction	O
and	O
stacked-die	O
assemblies	O
.	O
</s>
<s>
Xilinx	O
's	O
approach	O
stacks	O
several	O
(	O
three	O
or	O
four	O
)	O
active	O
FPGA	B-Architecture
dies	O
side	O
by	O
side	O
on	O
a	O
silicon	O
interposer	O
–	O
a	O
single	O
piece	O
of	O
silicon	O
that	O
carries	O
passive	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
multi-die	O
construction	O
also	O
allows	O
different	O
parts	O
of	O
the	O
FPGA	B-Architecture
to	O
be	O
created	O
with	O
different	O
process	O
technologies	O
,	O
as	O
the	O
process	O
requirements	O
are	O
different	O
between	O
the	O
FPGA	B-Architecture
fabric	O
itself	O
and	O
the	O
very	O
high	O
speed	O
28	O
Gbit/s	O
serial	O
transceivers	O
.	O
</s>
<s>
An	O
FPGA	B-Architecture
built	O
in	O
this	O
way	O
is	O
called	O
a	O
heterogeneous	O
FPGA	B-Architecture
.	O
</s>
<s>
Altera	O
's	O
heterogeneous	O
approach	O
involves	O
using	O
a	O
single	O
monolithic	O
FPGA	B-Architecture
die	O
and	O
connecting	O
other	O
die/technologies	O
to	O
the	O
FPGA	B-Architecture
using	O
Intel	O
's	O
embedded	B-Architecture
multi_die	O
interconnect	B-General_Concept
bridge	O
(	O
EMIB	O
)	O
technology	O
.	O
</s>
<s>
To	O
define	O
the	O
behavior	O
of	O
the	O
FPGA	B-Architecture
,	O
the	O
user	O
provides	O
a	O
design	B-General_Concept
in	O
a	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
or	O
as	O
a	O
schematic	B-Application
design	B-General_Concept
.	O
</s>
<s>
However	O
,	O
schematic	B-Application
entry	O
can	O
allow	O
for	O
easier	O
visualization	O
of	O
a	O
design	B-General_Concept
and	O
its	O
component	O
modules	B-Architecture
.	O
</s>
<s>
Using	O
an	O
electronic	O
design	B-General_Concept
automation	O
tool	O
,	O
a	O
technology-mapped	O
netlist	O
is	O
generated	O
.	O
</s>
<s>
The	O
netlist	O
can	O
then	O
be	O
fit	O
to	O
the	O
actual	O
FPGA	B-Architecture
architecture	O
using	O
a	O
process	O
called	O
place-and-route	O
,	O
usually	O
performed	O
by	O
the	O
FPGA	B-Architecture
company	O
's	O
proprietary	B-Application
place-and-route	O
software	O
.	O
</s>
<s>
The	O
user	O
will	O
validate	O
the	O
map	O
,	O
place	O
and	O
route	O
results	O
via	O
timing	B-Application
analysis	I-Application
,	O
simulation	O
,	O
and	O
other	O
verification	B-Application
and	I-Application
validation	I-Application
methodologies	O
.	O
</s>
<s>
Once	O
the	O
design	B-General_Concept
and	O
validation	O
process	O
is	O
complete	O
,	O
the	O
binary	O
file	O
generated	O
,	O
typically	O
using	O
the	O
FPGA	B-Architecture
vendor	O
's	O
proprietary	B-Application
software	I-Application
,	O
is	O
used	O
to	O
(	O
re	O
-	O
)	O
configure	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
This	O
file	O
is	O
transferred	O
to	O
the	O
FPGA/CPLD	O
via	O
a	O
serial	B-Protocol
interface	I-Protocol
(	O
JTAG	O
)	O
or	O
to	O
an	O
external	O
memory	B-General_Concept
device	I-General_Concept
like	O
an	O
EEPROM	B-General_Concept
.	O
</s>
<s>
The	O
most	O
common	O
HDLs	O
are	O
VHDL	B-Language
and	O
Verilog	B-Language
as	O
well	O
as	O
extensions	O
such	O
as	O
SystemVerilog	B-Language
.	O
</s>
<s>
However	O
,	O
in	O
an	O
attempt	O
to	O
reduce	O
the	O
complexity	O
of	O
designing	O
in	O
HDLs	O
,	O
which	O
have	O
been	O
compared	O
to	O
the	O
equivalent	O
of	O
assembly	B-Language
languages	I-Language
,	O
there	O
are	O
moves	O
to	O
raise	O
the	O
abstraction	B-Architecture
level	I-Architecture
through	O
the	O
introduction	O
of	O
alternative	O
languages	O
.	O
</s>
<s>
National	O
Instruments	O
 '	O
LabVIEW	B-Application
graphical	O
programming	O
language	O
(	O
sometimes	O
referred	O
to	O
as	O
"	O
G	O
"	O
)	O
has	O
an	O
FPGA	B-Architecture
add-in	O
module	B-Architecture
available	O
to	O
target	O
and	O
program	O
FPGA	B-Architecture
hardware	O
.	O
</s>
<s>
Verilog	B-Language
was	O
created	O
to	O
simplify	O
the	O
process	O
making	O
HDL	O
more	O
robust	O
and	O
flexible	O
.	O
</s>
<s>
Verilog	B-Language
is	O
currently	O
the	O
most	O
popular	O
.	O
</s>
<s>
Verilog	B-Language
creates	O
a	O
level	O
of	O
abstraction	O
to	O
hide	O
away	O
the	O
details	O
of	O
its	O
implementation	O
.	O
</s>
<s>
Verilog	B-Language
has	O
a	O
C-like	O
syntax	O
,	O
unlike	O
VHDL	B-Language
.	O
</s>
<s>
To	O
simplify	O
the	O
design	B-General_Concept
of	O
complex	O
systems	O
in	O
FPGAs	B-Architecture
,	O
there	O
exist	O
libraries	O
of	O
predefined	O
complex	O
functions	O
and	O
circuits	O
that	O
have	O
been	O
tested	O
and	O
optimized	O
to	O
speed	O
up	O
the	O
design	B-General_Concept
process	O
.	O
</s>
<s>
These	O
predefined	O
circuits	O
are	O
commonly	O
called	O
intellectual	O
property	O
(	O
IP	O
)	O
cores	O
,	O
and	O
are	O
available	O
from	O
FPGA	B-Architecture
vendors	O
and	O
third-party	O
IP	O
suppliers	O
.	O
</s>
<s>
They	O
are	O
rarely	O
free	O
,	O
and	O
typically	O
released	O
under	O
proprietary	B-Application
licenses	I-Application
.	O
</s>
<s>
Other	O
predefined	O
circuits	O
are	O
available	O
from	O
developer	O
communities	O
such	O
as	O
OpenCores	O
(	O
typically	O
released	O
under	O
free	B-License
and	I-License
open	I-License
source	I-License
licenses	O
such	O
as	O
the	O
GPL	B-License
,	O
BSD	B-Operating_System
or	O
similar	O
license	O
)	O
,	O
and	O
other	O
sources	O
.	O
</s>
<s>
In	O
a	O
typical	O
design	B-General_Concept
flow	O
,	O
an	O
FPGA	B-Architecture
application	O
developer	O
will	O
simulate	O
the	O
design	B-General_Concept
at	O
multiple	O
stages	O
throughout	O
the	O
design	B-General_Concept
process	O
.	O
</s>
<s>
Initially	O
the	O
RTL	O
description	O
in	O
VHDL	B-Language
or	O
Verilog	B-Language
is	O
simulated	O
by	O
creating	O
test	O
benches	O
to	O
simulate	O
the	O
system	O
and	O
observe	O
results	O
.	O
</s>
<s>
Then	O
,	O
after	O
the	O
synthesis	O
engine	O
has	O
mapped	O
the	O
design	B-General_Concept
to	O
a	O
netlist	O
,	O
the	O
netlist	O
is	O
translated	O
to	O
a	O
gate-level	O
description	O
where	O
simulation	O
is	O
repeated	O
to	O
confirm	O
the	O
synthesis	O
proceeded	O
without	O
errors	O
.	O
</s>
<s>
Finally	O
the	O
design	B-General_Concept
is	O
laid	O
out	O
in	O
the	O
FPGA	B-Architecture
at	O
which	O
point	O
propagation	O
delays	O
can	O
be	O
added	O
and	O
the	O
simulation	O
run	O
again	O
with	O
these	O
values	O
back-annotated	O
onto	O
the	O
netlist	O
.	O
</s>
<s>
More	O
recently	O
,	O
OpenCL	B-Application
(	O
Open	B-Application
Computing	I-Application
Language	I-Application
)	O
is	O
being	O
used	O
by	O
programmers	O
to	O
take	O
advantage	O
of	O
the	O
performance	O
and	O
power	O
efficiencies	O
that	O
FPGAs	B-Architecture
provide	O
.	O
</s>
<s>
OpenCL	B-Application
allows	O
programmers	O
to	O
develop	O
code	O
in	O
the	O
C	O
programming	O
language	O
and	O
target	O
FPGA	B-Architecture
functions	O
as	O
OpenCL	B-Application
kernels	O
using	O
OpenCL	B-Application
constructs	O
.	O
</s>
<s>
For	O
further	O
information	O
,	O
see	O
high-level	B-General_Concept
synthesis	I-General_Concept
and	O
C	B-Application
to	I-Application
HDL	I-Application
.	O
</s>
<s>
Most	O
FPGAs	B-Architecture
rely	O
on	O
an	O
SRAM-based	O
approach	O
to	O
be	O
programmed	O
.	O
</s>
<s>
These	O
FPGAs	B-Architecture
are	O
in-system	O
programmable	O
and	O
re-programmable	O
,	O
but	O
require	O
external	O
boot	B-Operating_System
devices	O
.	O
</s>
<s>
For	O
example	O
,	O
flash	B-Device
memory	I-Device
or	O
EEPROM	B-General_Concept
devices	O
may	O
often	O
load	O
contents	O
into	O
internal	O
SRAM	B-Architecture
that	O
controls	O
routing	B-Algorithm
and	O
logic	O
.	O
</s>
<s>
The	O
SRAM	B-Architecture
approach	O
is	O
based	O
on	O
CMOS	B-Device
.	O
</s>
<s>
Rarer	O
alternatives	O
to	O
the	O
SRAM	B-Architecture
approach	O
include	O
:	O
</s>
<s>
Fuse	O
:	O
one-time	B-General_Concept
programmable	I-General_Concept
.	O
</s>
<s>
Antifuse	O
:	O
one-time	B-General_Concept
programmable	I-General_Concept
.	O
</s>
<s>
CMOS	B-Device
.	O
</s>
<s>
PROM	B-General_Concept
:	O
programmable	B-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
technology	O
.	O
</s>
<s>
One-time	B-General_Concept
programmable	I-General_Concept
because	O
of	O
plastic	O
packaging	O
.	O
</s>
<s>
EPROM	B-General_Concept
:	O
erasable	B-General_Concept
programmable	I-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
technology	O
.	O
</s>
<s>
One-time	B-General_Concept
programmable	I-General_Concept
but	O
with	O
window	O
,	O
can	O
be	O
erased	O
with	O
ultraviolet	O
(	O
UV	O
)	O
light	O
.	O
</s>
<s>
CMOS	B-Device
.	O
</s>
<s>
EEPROM	B-General_Concept
:	O
electrically	B-General_Concept
erasable	I-General_Concept
programmable	I-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
technology	O
.	O
</s>
<s>
Some	O
but	O
not	O
all	O
EEPROM	B-General_Concept
devices	O
can	O
be	O
in-system	O
programmed	O
.	O
</s>
<s>
CMOS	B-Device
.	O
</s>
<s>
Flash	B-Device
:	O
flash-erase	O
EPROM	B-General_Concept
technology	O
.	O
</s>
<s>
Some	O
but	O
not	O
all	O
flash	B-Device
devices	O
can	O
be	O
in-system	O
programmed	O
.	O
</s>
<s>
Usually	O
,	O
a	O
flash	B-Device
cell	O
is	O
smaller	O
than	O
an	O
equivalent	O
EEPROM	B-General_Concept
cell	O
and	O
is	O
therefore	O
less	O
expensive	O
to	O
manufacture	O
.	O
</s>
<s>
CMOS	B-Device
.	O
</s>
<s>
In	O
2016	O
,	O
long-time	O
industry	O
rivals	O
Xilinx	O
(	O
now	O
part	O
of	O
AMD	O
)	O
and	O
Altera	O
(	O
now	O
an	O
Intel	O
subsidiary	O
)	O
were	O
the	O
FPGA	B-Architecture
market	O
leaders	O
.	O
</s>
<s>
Both	O
Xilinx	O
(	O
now	O
AMD	O
)	O
and	O
Altera	O
(	O
now	O
Intel	O
)	O
provide	O
proprietary	B-Application
electronic	O
design	B-General_Concept
automation	O
software	O
for	O
Windows	B-Application
and	O
Linux	B-Application
(	O
ISE/Vivado	O
and	O
Quartus	B-Language
)	O
which	O
enables	O
engineers	O
to	O
design	B-General_Concept
,	O
analyze	O
,	O
simulate	O
,	O
and	O
synthesize	O
(	O
compile	B-Language
)	O
their	O
designs	O
.	O
</s>
<s>
In	O
March	O
2010	O
,	O
Tabula	O
announced	O
their	O
FPGA	B-Architecture
technology	O
that	O
uses	O
time-multiplexed	B-Protocol
logic	O
and	O
interconnect	B-General_Concept
that	O
claims	O
potential	O
cost	O
savings	O
for	O
high-density	O
applications	O
.	O
</s>
<s>
Altium	B-Algorithm
,	O
provides	O
system-on-FPGA	O
hardware-software	O
design	B-General_Concept
environment	O
.	O
</s>
<s>
Efinix	O
offers	O
small	O
to	O
medium-sized	O
FPGAs	B-Architecture
.	O
</s>
<s>
They	O
combine	O
logic	O
and	O
routing	B-Algorithm
interconnects	B-General_Concept
into	O
a	O
configurable	B-General_Concept
XLR	O
cell	O
.	O
</s>
<s>
GOWIN	O
Semiconductors	O
,	O
manufacturing	O
small	O
and	O
medium-sized	O
SRAM	B-Architecture
and	O
Flash-based	O
FPGAs	B-Architecture
.	O
</s>
<s>
An	O
FPGA	B-Architecture
can	O
be	O
used	O
to	O
solve	O
any	O
problem	O
which	O
is	O
computable	O
.	O
</s>
<s>
This	O
is	O
trivially	O
proven	O
by	O
the	O
fact	O
that	O
FPGAs	B-Architecture
can	O
be	O
used	O
to	O
implement	O
a	O
soft	B-Device
microprocessor	I-Device
,	O
such	O
as	O
the	O
Xilinx	O
MicroBlaze	B-Device
or	O
Altera	O
Nios	B-Device
II	I-Device
.	O
</s>
<s>
Their	O
advantage	O
lies	O
in	O
that	O
they	O
are	O
significantly	O
faster	O
for	O
some	O
applications	O
because	O
of	O
their	O
parallel	B-Operating_System
nature	I-Operating_System
and	O
optimality	O
in	O
terms	O
of	O
the	O
number	O
of	O
gates	O
used	O
for	O
certain	O
processes	O
.	O
</s>
<s>
FPGAs	B-Architecture
originally	O
began	O
as	O
competitors	O
to	O
CPLDs	B-General_Concept
to	O
implement	O
glue	O
logic	O
for	O
printed	O
circuit	O
boards	O
.	O
</s>
<s>
As	O
their	O
size	O
,	O
capabilities	O
,	O
and	O
speed	O
increased	O
,	O
FPGAs	B-Architecture
took	O
over	O
additional	O
functions	O
to	O
the	O
point	O
where	O
some	O
are	O
now	O
marketed	O
as	O
full	O
systems	B-Architecture
on	I-Architecture
chips	I-Architecture
(	O
SoCs	O
)	O
.	O
</s>
<s>
Particularly	O
with	O
the	O
introduction	O
of	O
dedicated	O
multipliers	O
into	O
FPGA	B-Architecture
architectures	O
in	O
the	O
late	O
1990s	O
,	O
applications	O
which	O
had	O
traditionally	O
been	O
the	O
sole	O
reserve	O
of	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
hardware	I-Architecture
(	O
DSPs	O
)	O
began	O
to	O
incorporate	O
FPGAs	B-Architecture
instead	O
.	O
</s>
<s>
The	O
evolution	O
of	O
FPGAs	B-Architecture
has	O
motivated	O
an	O
increase	O
in	O
the	O
use	O
of	O
these	O
devices	O
,	O
whose	O
architecture	O
allows	O
the	O
development	O
of	O
hardware	O
solutions	O
optimized	O
for	O
complex	O
tasks	O
,	O
such	O
as	O
3D	O
MRI	O
image	O
segmentation	O
,	O
3D	O
discrete	O
wavelet	O
transform	O
,	O
tomographic	O
image	O
reconstruction	O
,	O
or	O
PET/MRI	O
systems	O
.	O
</s>
<s>
The	O
developed	O
solutions	O
can	O
perform	O
intensive	O
computation	O
tasks	O
with	O
parallel	B-Operating_System
processing	I-Operating_System
,	O
are	O
dynamically	O
reprogrammable	O
,	O
and	O
have	O
a	O
low	O
cost	O
,	O
all	O
while	O
meeting	O
the	O
hard	O
real-time	O
requirements	O
associated	O
with	O
medical	O
imaging	O
.	O
</s>
<s>
Another	O
trend	O
in	O
the	O
use	O
of	O
FPGAs	B-Architecture
is	O
hardware	B-General_Concept
acceleration	I-General_Concept
,	O
where	O
one	O
can	O
use	O
the	O
FPGA	B-Architecture
to	O
accelerate	B-General_Concept
certain	O
parts	O
of	O
an	O
algorithm	O
and	O
share	O
part	O
of	O
the	O
computation	O
between	O
the	O
FPGA	B-Architecture
and	O
a	O
generic	O
processor	O
.	O
</s>
<s>
The	O
search	O
engine	O
Bing	B-Application
is	O
noted	O
for	O
adopting	O
FPGA	B-Architecture
acceleration	O
for	O
its	O
search	O
algorithm	O
in	O
2014	O
.	O
,	O
FPGAs	B-Architecture
are	O
seeing	O
increased	O
use	O
as	O
AI	B-General_Concept
accelerators	I-General_Concept
including	O
Microsoft	O
's	O
so-termed	O
"	O
Project	O
Catapult	O
"	O
and	O
for	O
accelerating	O
artificial	B-Architecture
neural	I-Architecture
networks	I-Architecture
for	O
machine	O
learning	O
applications	O
.	O
</s>
<s>
Traditionally	O
,	O
FPGAs	B-Architecture
have	O
been	O
reserved	O
for	O
specific	O
vertical	B-Application
applications	I-Application
where	O
the	O
volume	O
of	O
production	O
is	O
small	O
.	O
</s>
<s>
The	O
company	O
Gigabyte	O
Technology	O
created	O
an	O
i-RAM	O
card	O
which	O
used	O
a	O
Xilinx	O
FPGA	B-Architecture
although	O
a	O
custom	O
made	O
chip	O
would	O
be	O
cheaper	O
if	O
made	O
in	O
large	O
quantities	O
.	O
</s>
<s>
The	O
FPGA	B-Architecture
was	O
chosen	O
to	O
bring	O
it	O
quickly	O
to	O
market	O
and	O
the	O
initial	O
run	O
was	O
only	O
to	O
be	O
1000	O
units	O
making	O
an	O
FPGA	B-Architecture
the	O
best	O
choice	O
.	O
</s>
<s>
Other	O
uses	O
for	O
FPGAs	B-Architecture
include	O
:	O
</s>
<s>
FPGAs	B-Architecture
have	O
both	O
advantages	O
and	O
disadvantages	O
as	O
compared	O
to	O
ASICs	O
or	O
secure	O
microprocessors	B-Architecture
,	O
concerning	O
hardware	O
security	O
.	O
</s>
<s>
FPGAs	B-Architecture
 '	O
flexibility	O
makes	O
malicious	O
modifications	O
during	O
fabrication	B-Architecture
a	O
lower	O
risk	O
.	O
</s>
<s>
Previously	O
,	O
for	O
many	O
FPGAs	B-Architecture
,	O
the	O
design	B-General_Concept
bitstream	O
was	O
exposed	O
while	O
the	O
FPGA	B-Architecture
loads	O
it	O
from	O
external	O
memory	B-General_Concept
(	O
typically	O
on	O
every	O
power-on	O
)	O
.	O
</s>
<s>
All	O
major	O
FPGA	B-Architecture
vendors	O
now	O
offer	O
a	O
spectrum	O
of	O
security	O
solutions	O
to	O
designers	O
such	O
as	O
bitstream	O
encryption	O
and	O
authentication	O
.	O
</s>
<s>
For	O
example	O
,	O
Altera	O
and	O
Xilinx	O
offer	O
AES	B-Algorithm
encryption	I-Algorithm
(	O
up	O
to	O
256-bit	O
)	O
for	O
bitstreams	O
stored	O
in	O
an	O
external	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Physical	O
Unclonable	O
Functions	O
(	O
PUFs	O
)	O
are	O
integrated	O
circuits	O
that	O
have	O
their	O
own	O
unique	O
signatures	O
,	O
due	O
to	O
processing	O
,	O
and	O
can	O
also	O
be	O
used	O
to	O
secure	O
FPGAs	B-Architecture
while	O
taking	O
up	O
very	O
little	O
hardware	O
space	O
.	O
</s>
<s>
FPGAs	B-Architecture
that	O
store	O
their	O
configuration	B-General_Concept
internally	O
in	O
nonvolatile	B-General_Concept
flash	B-Device
memory	I-Device
,	O
such	O
as	O
Microsemi	O
's	O
ProAsic	O
3	O
or	O
Lattice	O
's	O
XP2	O
programmable	O
devices	O
,	O
do	O
not	O
expose	O
the	O
bitstream	O
and	O
do	O
not	O
need	O
encryption	O
.	O
</s>
<s>
In	O
addition	O
,	O
flash	B-Device
memory	I-Device
for	O
a	O
lookup	B-Data_Structure
table	I-Data_Structure
provides	O
single	O
event	O
upset	O
protection	O
for	O
space	O
applications	O
.	O
</s>
<s>
Customers	O
wanting	O
a	O
higher	O
guarantee	O
of	O
tamper	O
resistance	O
can	O
use	O
write-once	O
,	O
antifuse	O
FPGAs	B-Architecture
from	O
vendors	O
such	O
as	O
Microsemi	O
.	O
</s>
<s>
With	O
its	O
Stratix	B-Device
10	O
FPGAs	B-Architecture
and	O
SoCs	O
,	O
Altera	O
introduced	O
a	O
Secure	O
Device	O
Manager	O
and	O
physical	O
unclonable	O
functions	O
to	O
provide	O
high	O
levels	O
of	O
protection	O
against	O
physical	O
attacks	O
.	O
</s>
<s>
In	O
2012	O
researchers	O
Sergei	O
Skorobogatov	O
and	O
Christopher	O
Woods	O
demonstrated	O
that	O
some	O
FPGAs	B-Architecture
can	O
be	O
vulnerable	O
to	O
hostile	O
intent	O
.	O
</s>
<s>
They	O
discovered	O
a	O
critical	O
backdoor	O
vulnerability	O
had	O
been	O
manufactured	O
in	O
silicon	O
as	O
part	O
of	O
the	O
Actel/Microsemi	O
ProAsic	O
3	O
making	O
it	O
vulnerable	O
on	O
many	O
levels	O
such	O
as	O
reprogramming	O
crypto	O
and	O
access	B-Device
keys	I-Device
,	O
accessing	O
unencrypted	O
bitstream	O
,	O
modifying	O
low-level	O
silicon	O
features	O
,	O
and	O
extracting	O
configuration	B-General_Concept
data	O
.	O
</s>
<s>
In	O
2020	O
a	O
critical	O
vulnerability	O
(	O
named	O
"	O
Starbleed	O
"	O
)	O
was	O
discovered	O
in	O
all	O
Xilinx	O
7series	O
FPGAs	B-Architecture
that	O
rendered	O
bitstream	O
encryption	O
useless	O
.	O
</s>
<s>
Historically	O
,	O
FPGAs	B-Architecture
have	O
been	O
slower	O
,	O
less	O
energy	O
efficient	O
and	O
generally	O
achieved	O
less	O
functionality	O
than	O
their	O
fixed	O
ASIC	O
counterparts	O
.	O
</s>
<s>
A	O
study	O
from	O
2006	O
showed	O
that	O
designs	O
implemented	O
on	O
FPGAs	B-Architecture
need	O
on	O
average	O
40	O
times	O
as	O
much	O
area	O
,	O
draw	O
12	O
times	O
as	O
much	O
dynamic	O
power	O
,	O
and	O
run	O
at	O
one	O
third	O
the	O
speed	O
of	O
corresponding	O
ASIC	O
implementations	O
.	O
</s>
<s>
More	O
recently	O
,	O
FPGAs	B-Architecture
such	O
as	O
the	O
Xilinx	O
Virtex-7	O
or	O
the	O
Altera	O
Stratix	B-Device
5	O
have	O
come	O
to	O
rival	O
corresponding	O
ASIC	O
and	O
ASSP	O
(	O
"	O
Application-specific	O
standard	O
part	O
"	O
,	O
such	O
as	O
a	O
standalone	O
USB	O
interface	O
chip	O
)	O
solutions	O
by	O
providing	O
significantly	O
reduced	O
power	O
usage	O
,	O
increased	O
speed	O
,	O
lower	O
materials	O
cost	O
,	O
minimal	O
implementation	O
real-estate	O
,	O
and	O
increased	O
possibilities	O
for	O
re-configuration	O
'	O
on-the-fly	O
'	O
.	O
</s>
<s>
A	O
design	B-General_Concept
that	O
included	O
6	O
to	O
10	O
ASICs	O
can	O
now	O
be	O
achieved	O
using	O
only	O
one	O
FPGA	B-Architecture
.	O
</s>
<s>
Advantages	O
of	O
FPGAs	B-Architecture
include	O
the	O
ability	O
to	O
re-program	O
when	O
already	O
deployed	O
(	O
i.e.	O
</s>
<s>
"	O
in	O
the	O
field	O
"	O
)	O
to	O
fix	O
bugs	B-Error_Name
,	O
and	O
often	O
include	O
shorter	O
time	O
to	O
market	O
and	O
lower	O
non-recurring	O
engineering	O
costs	O
.	O
</s>
<s>
Vendors	O
can	O
also	O
take	O
a	O
middle	O
road	O
via	O
FPGA	B-Architecture
prototyping	O
:	O
developing	O
their	O
prototype	O
hardware	O
on	O
FPGAs	B-Architecture
,	O
but	O
manufacture	O
their	O
final	O
version	O
as	O
an	O
ASIC	O
so	O
that	O
it	O
can	O
no	O
longer	O
be	O
modified	O
after	O
the	O
design	B-General_Concept
has	O
been	O
committed	O
.	O
</s>
<s>
This	O
is	O
often	O
also	O
the	O
case	O
with	O
new	O
processor	B-General_Concept
designs	I-General_Concept
.	O
</s>
<s>
Some	O
FPGAs	B-Architecture
have	O
the	O
capability	O
of	O
partial	O
re-configuration	O
that	O
lets	O
one	O
portion	O
of	O
the	O
device	O
be	O
re-programmed	O
while	O
other	O
portions	O
continue	O
running	O
.	O
</s>
<s>
The	O
primary	O
differences	O
between	O
complex	B-General_Concept
programmable	I-General_Concept
logic	I-General_Concept
devices	I-General_Concept
(	O
CPLDs	B-General_Concept
)	O
and	O
FPGAs	B-Architecture
are	O
architectural	B-General_Concept
.	O
</s>
<s>
A	O
CPLD	B-General_Concept
has	O
a	O
comparatively	O
restrictive	O
structure	O
consisting	O
of	O
one	O
or	O
more	O
programmable	O
sum-of-products	O
logic	O
arrays	O
feeding	O
a	O
relatively	O
small	O
number	O
of	O
clocked	O
registers	B-General_Concept
.	O
</s>
<s>
As	O
a	O
result	O
,	O
CPLDs	B-General_Concept
are	O
less	O
flexible	O
,	O
but	O
have	O
the	O
advantage	O
of	O
more	O
predictable	O
timing	O
delays	O
and	O
FPGA	B-Architecture
architectures	O
,	O
on	O
the	O
other	O
hand	O
,	O
are	O
dominated	O
by	O
interconnect	B-General_Concept
.	O
</s>
<s>
This	O
makes	O
them	O
far	O
more	O
flexible	O
(	O
in	O
terms	O
of	O
the	O
range	O
of	O
designs	O
that	O
are	O
practical	O
for	O
implementation	O
on	O
them	O
)	O
but	O
also	O
far	O
more	O
complex	O
to	O
design	B-General_Concept
for	O
,	O
or	O
at	O
least	O
requiring	O
more	O
complex	O
electronic	O
design	B-General_Concept
automation	O
(	O
EDA	O
)	O
software	O
.	O
</s>
<s>
In	O
practice	O
,	O
the	O
distinction	O
between	O
FPGAs	B-Architecture
and	O
CPLDs	B-General_Concept
is	O
often	O
one	O
of	O
size	O
as	O
FPGAs	B-Architecture
are	O
usually	O
much	O
larger	O
in	O
terms	O
of	O
resources	O
than	O
CPLDs	B-General_Concept
.	O
</s>
<s>
Typically	O
only	O
FPGAs	B-Architecture
contain	O
more	O
complex	O
embedded	B-General_Concept
functions	I-General_Concept
such	O
as	O
adders	O
,	O
multipliers	O
,	O
memory	B-General_Concept
,	O
and	O
serializer/deserializers	O
.	O
</s>
<s>
Another	O
common	O
distinction	O
is	O
that	O
CPLDs	B-General_Concept
contain	O
embedded	B-Architecture
flash	B-Device
memory	I-Device
to	O
store	O
their	O
configuration	B-General_Concept
while	O
FPGAs	B-Architecture
usually	O
require	O
external	O
non-volatile	B-General_Concept
memory	I-General_Concept
(	O
but	O
not	O
always	O
)	O
.	O
</s>
<s>
When	O
a	O
design	B-General_Concept
requires	O
simple	O
instant-on	B-Protocol
(	O
logic	O
is	O
already	O
configured	O
at	O
power-up	O
)	O
CPLDs	B-General_Concept
are	O
generally	O
preferred	O
.	O
</s>
<s>
For	O
most	O
other	O
applications	O
FPGAs	B-Architecture
are	O
generally	O
preferred	O
.	O
</s>
<s>
Sometimes	O
both	O
CPLDs	B-General_Concept
and	O
FPGAs	B-Architecture
are	O
used	O
in	O
a	O
single	O
system	O
design	B-General_Concept
.	O
</s>
<s>
In	O
those	O
designs	O
,	O
CPLDs	B-General_Concept
generally	O
perform	O
glue	O
logic	O
functions	O
,	O
and	O
are	O
responsible	O
for	O
"	O
booting	B-Operating_System
"	O
the	O
FPGA	B-Architecture
as	O
well	O
as	O
controlling	O
reset	B-General_Concept
and	O
boot	B-Operating_System
sequence	I-Operating_System
of	O
the	O
complete	O
circuit	O
board	O
.	O
</s>
<s>
Therefore	O
,	O
depending	O
on	O
the	O
application	O
it	O
may	O
be	O
judicious	O
to	O
use	O
both	O
FPGAs	B-Architecture
and	O
CPLDs	B-General_Concept
in	O
a	O
single	O
design	B-General_Concept
.	O
</s>
