<s>
The	O
Ferranti	B-General_Concept
F100-L	I-General_Concept
was	O
a	O
16-bit	B-Device
microprocessor	B-Architecture
family	O
announced	O
by	O
Ferranti	O
in	O
1976	O
which	O
entered	O
production	O
in	O
1977	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
microprocessor	B-Architecture
designed	O
in	O
Europe	O
,	O
and	O
among	O
the	O
first	O
16-bit	B-Device
single-chip	O
CPUs	O
.	O
</s>
<s>
To	O
deliver	O
these	O
capabilities	O
,	O
the	O
F100	O
was	O
implemented	O
using	O
bipolar	O
junction	O
transistors	B-Application
,	O
as	O
opposed	O
to	O
the	O
metal	B-Architecture
oxide	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
process	O
used	O
by	O
most	O
other	O
processors	O
of	O
the	O
era	O
.	O
</s>
<s>
It	O
was	O
very	O
cost	O
competitive	O
in	O
the	O
industrial	O
and	O
military	O
markets	O
,	O
but	O
less	O
so	O
in	O
the	O
commercial	O
market	O
where	O
processors	O
like	O
the	O
MOS	B-General_Concept
6502	I-General_Concept
were	O
about	O
$11	O
in	O
the	O
same	O
100	O
unit	O
quantity	O
.	O
</s>
<s>
This	O
was	O
software	O
compatible	O
with	O
the	O
F100	O
,	O
but	O
included	O
the	O
maths	O
processor	O
on	O
the	O
same	O
die	O
,	O
expanded	O
addressing	O
to	O
128kB	O
,	O
and	O
allowed	O
up	O
to	O
1MB	O
of	O
memory	O
when	O
paired	O
with	O
the	O
new	O
F220	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Ferranti	O
was	O
among	O
the	O
first	O
companies	O
to	O
introduce	O
a	O
commercial	O
computer	O
,	O
the	O
Ferranti	B-Device
Mark	I-Device
1	I-Device
of	O
1951	O
.	O
</s>
<s>
They	O
followed	O
this	O
with	O
several	O
other	O
commercial	O
designs	O
,	O
most	O
notably	O
the	O
Ferranti	B-Device
Atlas	I-Device
of	O
1962	O
,	O
for	O
a	O
time	O
the	O
fastest	O
computer	O
in	O
the	O
world	O
.	O
</s>
<s>
In	O
1963	O
they	O
used	O
the	O
Ferranti-Packard	B-Device
6000	I-Device
,	O
developed	O
independently	O
at	O
their	O
Canadian	O
division	O
,	O
as	O
the	O
"	O
golden	O
brick	O
"	O
in	O
the	O
sale	O
of	O
their	O
entire	O
commercial	O
computing	O
line	O
to	O
International	O
Computers	O
and	O
Tabulators	O
(	O
ICT	O
)	O
.	O
</s>
<s>
This	O
left	O
them	O
with	O
two	O
existing	O
architectures	O
that	O
had	O
been	O
developed	O
for	O
military	O
uses	O
,	O
the	O
small	O
Ferranti	B-Device
Argus	I-Device
that	O
had	O
already	O
become	O
a	O
success	O
in	O
the	O
industrial	O
controller	O
market	O
,	O
and	O
the	O
FM	O
1600	O
,	O
a	O
larger	O
machine	O
used	O
for	O
realtime	O
data	O
handling	O
,	O
weapons	O
control	O
and	O
simulation	O
.	O
</s>
<s>
Both	O
were	O
built	O
of	O
individual	O
transistors	B-Application
and	O
small	O
scale	O
integration	O
integrated	O
circuits	O
using	O
Ferranti	O
's	O
MicroNor	O
bipolar	O
transistor	B-Application
process	O
.	O
</s>
<s>
A	O
significant	O
problem	O
with	O
the	O
MicroNor	O
process	O
was	O
that	O
a	O
logic	O
gate	O
implemented	O
using	O
bipolar	O
layout	O
was	O
significantly	O
larger	O
than	O
one	O
using	O
the	O
contemporary	O
MOSFET	B-Architecture
process	O
,	O
about	O
six	O
times	O
.	O
</s>
<s>
Ferranti	O
invested	O
heavily	O
in	O
the	O
CDI	O
process	O
,	O
working	O
to	O
raise	O
the	O
operating	O
voltage	O
from	O
3	O
to	O
5V	O
for	O
compatibility	O
with	O
their	O
existing	O
transistor-transistor	B-General_Concept
logic	I-General_Concept
(	O
TTL	B-General_Concept
)	O
devices	O
that	O
were	O
already	O
widely	O
used	O
in	O
military	O
applications	O
.	O
</s>
<s>
The	O
introduction	O
of	O
the	O
first	O
microprocessors	B-Architecture
in	O
the	O
early	O
1970s	O
cut	O
into	O
Ferranti	O
's	O
military	O
computing	O
business	O
.	O
</s>
<s>
Convinced	O
that	O
the	O
microprocessor	B-Architecture
represented	O
a	O
strategic	O
change	O
in	O
military	O
applications	O
,	O
in	O
1974	O
the	O
UK	O
Ministry	O
of	O
Defence	O
agreed	O
to	O
sponsor	O
an	O
effort	O
by	O
Ferranti	O
to	O
produce	O
a	O
military-grade	O
microprocessor	B-Architecture
design	O
using	O
the	O
CDI	O
process	O
,	O
whose	O
high	O
power-handling	O
allowed	O
them	O
to	O
operate	O
in	O
electrically	O
noisy	O
environments	O
.	O
</s>
<s>
An	O
internal	O
survey	O
within	O
the	O
company	O
suggested	O
that	O
an	O
8-bit	O
part	O
would	O
not	O
have	O
the	O
capability	O
needed	O
by	O
the	O
various	O
divisions	O
,	O
and	O
the	O
decision	O
was	O
made	O
to	O
produce	O
a	O
16-bit	B-Device
part	O
.	O
</s>
<s>
To	O
produce	O
a	O
16-bit	B-Device
design	O
with	O
this	O
limited	O
gate	O
count	O
,	O
the	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
,	O
or	O
ALU	O
,	O
had	O
to	O
operate	O
in	O
a	O
bit-serial	O
fashion	O
.	O
</s>
<s>
With	O
16-bit	B-Device
data	O
and	O
15-bit	O
addresses	O
,	O
normally	O
31	O
pins	O
would	O
be	O
required	O
to	O
interface	O
the	O
design	O
to	O
the	O
computer	O
as	O
a	O
whole	O
.	O
</s>
<s>
Desiring	O
a	O
low-cost	O
solution	O
,	O
it	O
had	O
to	O
fit	O
into	O
a	O
conventional	O
40-pin	O
dual	B-Algorithm
in-line	I-Algorithm
package	I-Algorithm
(	O
DIP	B-Algorithm
)	O
.	O
</s>
<s>
For	O
comparison	O
,	O
the	O
Texas	B-General_Concept
Instruments	I-General_Concept
TMS9900	I-General_Concept
,	O
another	O
16-bit	B-Device
design	O
introduced	O
the	O
same	O
year	O
,	O
had	O
double	O
the	O
gate	O
count	O
and	O
was	O
packaged	O
in	O
an	O
expensive	O
custom	O
64-pin	O
DIP	B-Algorithm
.	O
</s>
<s>
The	O
timing	O
of	O
the	O
design	O
effort	O
also	O
produced	O
one	O
advantage	O
;	O
the	O
F100	O
was	O
beginning	O
to	O
be	O
readied	O
for	O
production	O
just	O
as	O
the	O
Micralign	B-Algorithm
system	O
was	O
coming	O
to	O
market	O
,	O
and	O
Ferranti	O
adopted	O
this	O
projection	O
alignment	O
system	O
for	O
production	O
,	O
thereby	O
greatly	O
improving	O
yields	O
.	O
</s>
<s>
As	O
was	O
common	O
at	O
the	O
time	O
,	O
the	O
F100	O
was	O
introduced	O
along	O
with	O
a	O
family	O
of	O
support	O
chips	O
,	O
including	O
memory	O
bus	O
interfaces	O
,	O
interrupt	O
controller	O
,	O
a	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
controller	O
and	O
a	O
basic	O
serial	O
bus	O
controller	O
.	O
</s>
<s>
Programming	O
tools	O
were	O
initially	O
written	O
in	O
FORTRAN	B-Application
,	O
but	O
most	O
projects	O
were	O
written	O
in	O
CORAL	B-Language
once	O
a	O
compiler	O
for	O
that	O
language	O
became	O
available	O
.	O
</s>
<s>
A	O
set	O
containing	O
an	O
F100	O
along	O
with	O
the	O
F111-L	O
control	O
interface	O
and	O
two	O
F112-L	O
DMA	B-General_Concept
controllers	I-General_Concept
was	O
available	O
for	O
an	O
additional	O
£18	O
.	O
</s>
<s>
While	O
this	O
made	O
it	O
uncompetitive	O
with	O
MOS-based	O
commercial	O
processors	O
like	O
the	O
$25	O
Zilog	B-General_Concept
Z80	I-General_Concept
or	O
$11	O
MOS	B-General_Concept
6502	I-General_Concept
in	O
the	O
same	O
100-unit	O
lots	O
,	O
it	O
was	O
very	O
competitive	O
with	O
other	O
military-spec	O
designs	O
like	O
the	O
Z80	B-General_Concept
's	O
military-rated	O
unit	O
at	O
$165	O
.	O
</s>
<s>
It	O
was	O
also	O
used	O
in	O
the	O
civilian	O
field	O
in	O
engine	O
management	O
systems	O
from	O
Ultra	O
Electronic	O
Controls	O
,	O
a	O
propeller	O
speed	O
limiter	O
from	O
Dowty	O
Group	O
,	O
and	O
even	O
control	O
of	O
nuclear	O
test	O
equipment	O
using	O
the	O
CAMAC	B-Architecture
protocol	O
.	O
</s>
<s>
The	O
new	O
F220-L	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
,	O
launched	O
at	O
the	O
same	O
time	O
,	O
provided	O
address	O
lookup	O
within	O
a	O
1MW	O
(	O
2MB	O
)	O
memory	O
space	O
.	O
</s>
<s>
Most	O
microprocessors	B-Architecture
of	O
the	O
1970s	O
used	O
internal	O
8-bit	O
wide	O
processor	B-General_Concept
registers	I-General_Concept
,	O
an	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
and	O
a	O
16-bit	B-Device
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
F100	O
used	O
16-bit	B-Device
registers	O
but	O
only	O
15-bits	O
in	O
the	O
address	B-Architecture
bus	I-Architecture
,	O
but	O
these	O
addresses	O
represented	O
16-bit	B-Device
words	O
so	O
the	O
total	O
addressable	O
memory	O
was	O
64kB	O
,	O
as	O
was	O
the	O
case	O
with	O
most	O
8-bit	O
processors	O
with	O
16-bit	B-Device
addressing	O
.	O
</s>
<s>
At	O
the	O
time	O
the	O
F100	O
was	O
designed	O
,	O
memory	O
was	O
extremely	O
expensive	O
and	O
typical	O
machines	O
of	O
the	O
era	O
generally	O
featured	O
only	O
4kB	O
of	O
SRAM	B-Architecture
,	O
so	O
the	O
missing	O
16th	O
bit	O
in	O
the	O
address	O
was	O
not	O
an	O
important	O
consideration	O
.	O
</s>
<s>
The	O
16-bit	B-Device
ACC	O
(	O
accumulator	B-General_Concept
)	O
and	O
OR	O
(	O
operand	O
register	O
)	O
are	O
used	O
to	O
hold	O
values	O
being	O
manipulated	O
by	O
the	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
during	O
calculations	O
and	O
comparisons	O
.	O
</s>
<s>
Two	O
additional	O
registers	O
are	O
used	O
internally	O
;	O
the	O
15-bit	O
PC	O
(	O
program	B-General_Concept
counter	I-General_Concept
)	O
holds	O
the	O
address	O
of	O
the	O
currently	O
executing	O
instruction	O
and	O
has	O
an	O
auto-increment	O
feature	O
,	O
while	O
the	O
16-bit	B-Device
IR	O
(	O
instruction	O
register	O
)	O
is	O
used	O
to	O
hold	O
the	O
actual	O
instruction	O
itself	O
.	O
</s>
<s>
If	O
the	O
instruction	O
operates	O
on	O
a	O
memory	O
address	O
,	O
the	O
value	O
in	O
the	O
IR	O
is	O
moved	O
to	O
internal	O
latches	B-General_Concept
and	O
the	O
IR	O
is	O
then	O
loaded	O
with	O
the	O
address	O
value	O
.	O
</s>
<s>
The	O
F100	O
had	O
a	O
total	O
of	O
four	O
addressing	B-Language
modes	I-Language
;	O
direct	O
,	O
immediate	O
,	O
pointer	O
and	O
immediate	O
indirect	O
.	O
</s>
<s>
For	O
instance	O
,	O
AND	O
0x444	O
would	O
perform	O
a	O
bitwise	O
AND	O
operation	O
between	O
the	O
current	O
value	O
in	O
the	O
ACC	O
and	O
the	O
16-bit	B-Device
constant	O
0x444	O
.	O
</s>
<s>
Immediate	O
mode	O
was	O
similar	O
to	O
direct	O
,	O
but	O
the	O
value	O
to	O
be	O
accessed	O
is	O
placed	O
in	O
the	O
16-bits	B-Device
following	O
the	O
instruction	O
in	O
order	O
to	O
allow	O
larger	O
constants	O
.	O
</s>
<s>
As	O
was	O
common	O
at	O
the	O
time	O
,	O
the	O
F100	O
featured	O
a	O
form	O
of	O
zero	B-General_Concept
page	I-General_Concept
addressing	O
they	O
referred	O
to	O
as	O
Pointer	O
Indirect	B-Language
Addressing	I-Language
,	O
or	O
simply	O
pointer	O
.	O
</s>
<s>
Address	O
zero	O
,	O
a	O
16-bit	B-Device
word	O
,	O
was	O
used	O
as	O
the	O
stack	O
pointer	O
,	O
which	O
lacked	O
its	O
own	O
register	O
.	O
</s>
<s>
Pointer	O
addressing	O
used	O
the	O
lower	O
8	O
bits	O
of	O
the	O
instruction	O
to	O
indicate	O
one	O
of	O
the	O
zero	B-General_Concept
page	I-General_Concept
addresses	O
,	O
whose	O
value	O
would	O
be	O
read	O
as	O
an	O
address	O
,	O
and	O
then	O
the	O
value	O
at	O
that	O
address	O
would	O
be	O
loaded	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
F100	O
had	O
alternate	O
forms	O
of	O
the	O
pointer	O
addressing	O
instructions	O
that	O
performed	O
a	O
pre-increment	O
or	O
post-decrement	O
of	O
the	O
value	O
in	O
the	O
pointer	O
in	O
the	O
zero	B-General_Concept
page	I-General_Concept
.	O
</s>
<s>
Finally	O
,	O
indirect	B-Language
addressing	I-Language
was	O
similar	O
to	O
pointer	O
addressing	O
but	O
allows	O
any	O
value	O
in	O
memory	O
to	O
hold	O
the	O
pointer	O
,	O
rather	O
than	O
just	O
the	O
zero	B-General_Concept
page	I-General_Concept
.	O
</s>
<s>
This	O
is	O
more	O
flexible	O
,	O
but	O
as	O
the	O
address	O
is	O
stored	O
in	O
the	O
16	B-Device
bits	I-Device
following	O
the	O
instruction	O
,	O
using	O
this	O
method	O
is	O
slower	O
than	O
zero	B-General_Concept
page	I-General_Concept
because	O
two	O
memory	O
addresses	O
have	O
to	O
be	O
read	O
instead	O
of	O
one	O
.	O
</s>
<s>
Some	O
of	O
the	O
indirect	B-Language
addressing	I-Language
mode	O
instructions	O
also	O
took	O
a	O
third	O
value	O
,	O
indicating	O
another	O
location	O
in	O
memory	O
.	O
</s>
<s>
The	O
first	O
was	O
the	O
stack	O
pointer	O
in	O
location	O
zero	O
,	O
next	O
was	O
the	O
remaining	O
255	O
locations	O
of	O
the	O
zero	B-General_Concept
page	I-General_Concept
,	O
then	O
the	O
maximum	O
2048	O
locations	O
of	O
the	O
direct	O
mode	O
(	O
which	O
included	O
the	O
zero	B-General_Concept
page	I-General_Concept
)	O
,	O
and	O
finally	O
the	O
remaining	O
memory	O
which	O
could	O
be	O
accessed	O
by	O
the	O
15-bit	O
addresses	O
.	O
</s>
<s>
The	O
F100	O
had	O
a	O
total	O
of	O
29	O
instructions	O
,	O
which	O
combined	O
using	O
the	O
various	O
addressing	B-Language
modes	I-Language
results	O
in	O
153	O
opcodes	O
.	O
</s>
<s>
The	O
rest	O
of	O
the	O
bits	O
varied	O
depending	O
on	O
the	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
For	O
instance	O
,	O
if	O
direct	B-Language
addressing	I-Language
was	O
being	O
used	O
,	O
bit	O
11	O
was	O
set	O
to	O
0	O
,	O
10	O
and	O
9	O
to	O
1	O
,	O
and	O
the	O
remaining	O
11	O
bits	O
encoded	O
the	O
address	O
of	O
the	O
operand	O
.	O
</s>
<s>
If	O
the	O
11	O
bits	O
were	O
all	O
set	O
to	O
zero	O
,	O
it	O
instead	O
read	O
the	O
operand	O
from	O
the	O
next	O
16	B-Device
bits	I-Device
in	O
memory	O
.	O
</s>
