<s>
Fermi	B-General_Concept
is	O
the	O
codename	O
for	O
a	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
microarchitecture	B-General_Concept
developed	O
by	O
Nvidia	O
,	O
first	O
released	O
to	O
retail	O
in	O
April	O
2010	O
,	O
as	O
the	O
successor	O
to	O
the	O
Tesla	B-Operating_System
microarchitecture	I-Operating_System
.	O
</s>
<s>
It	O
was	O
the	O
primary	O
microarchitecture	B-General_Concept
used	O
in	O
the	O
GeForce	B-Application
400	O
series	O
and	O
GeForce	B-Application
500	O
series	O
.	O
</s>
<s>
It	O
was	O
followed	O
by	O
Kepler	B-General_Concept
,	O
and	O
used	O
alongside	O
Kepler	B-General_Concept
in	O
the	O
GeForce	B-Application
600	O
series	O
,	O
GeForce	B-Application
700	O
series	O
,	O
and	O
GeForce	B-Application
800	O
series	O
,	O
in	O
the	O
latter	O
two	O
only	O
in	O
mobile	O
GPUs	B-Architecture
.	O
</s>
<s>
In	O
the	O
workstation	O
market	O
,	O
Fermi	B-General_Concept
found	O
use	O
in	O
the	O
Quadro	B-Application
x000	O
series	O
,	O
Quadro	B-Application
NVS	O
models	O
,	O
as	O
well	O
as	O
in	O
Nvidia	B-Device
Tesla	I-Device
computing	O
modules	O
.	O
</s>
<s>
All	O
desktop	O
Fermi	B-General_Concept
GPUs	B-Architecture
were	O
manufactured	O
in	O
40nm	O
,	O
mobile	O
Fermi	B-General_Concept
GPUs	B-Architecture
in	O
40nm	O
and	O
28nm	O
.	O
</s>
<s>
Fermi	B-General_Concept
is	O
the	O
oldest	O
microarchitecture	B-General_Concept
from	O
NVIDIA	O
that	O
received	O
support	O
for	O
the	O
Microsoft	O
's	O
rendering	O
API	O
Direct3D	O
12	O
feature_level	O
11	O
.	O
</s>
<s>
The	O
architecture	O
is	O
named	O
after	O
Enrico	O
Fermi	B-General_Concept
,	O
an	O
Italian	O
physicist	O
.	O
</s>
<s>
Fermi	B-General_Concept
Graphic	B-Architecture
Processing	I-Architecture
Units	I-Architecture
(	O
GPUs	B-Architecture
)	O
feature	O
3.0	O
billion	O
transistors	O
and	O
a	O
schematic	O
is	O
sketched	O
in	O
Fig	O
.	O
</s>
<s>
Streaming	O
Multiprocessor	O
(	O
SM	O
)	O
:	O
composed	O
of	O
32	O
CUDA	B-Architecture
cores	O
(	O
see	O
Streaming	O
Multiprocessor	O
and	O
CUDA	B-Architecture
core	O
sections	O
)	O
.	O
</s>
<s>
GigaThread	O
global	O
scheduler	O
:	O
distributes	O
thread	B-Operating_System
blocks	O
to	O
SM	O
thread	B-Operating_System
schedulers	O
and	O
manages	O
the	O
context	O
switches	O
between	O
threads	B-Operating_System
during	O
execution	O
(	O
see	O
Warp	O
Scheduling	O
section	O
)	O
.	O
</s>
<s>
Host	O
interface	O
:	O
connects	O
the	O
GPU	B-Architecture
to	O
the	O
CPU	O
via	O
a	O
PCI-Express	O
v2	O
bus	O
(	O
peak	O
transfer	O
rate	O
of	O
8GB/s	O
)	O
.	O
</s>
<s>
DRAM	O
bandwidth	B-Algorithm
:	O
192GB/s	O
.	O
</s>
<s>
Each	O
SM	O
features	O
32	O
single-precision	O
CUDA	B-Architecture
cores	O
,	O
16	O
load/store	O
units	O
,	O
four	O
Special	O
Function	O
Units	O
(	O
SFUs	O
)	O
,	O
a	O
64KB	O
block	O
of	O
high	O
speed	O
on-chip	O
memory	O
(	O
see	O
L1+Shared	O
Memory	O
subsection	O
)	O
and	O
an	O
interface	O
to	O
the	O
L2	O
cache	B-General_Concept
(	O
see	O
L2	O
Cache	B-General_Concept
subsection	O
)	O
.	O
</s>
<s>
Allow	O
source	O
and	O
destination	O
addresses	O
to	O
be	O
calculated	O
for	O
16	O
threads	B-Operating_System
per	O
clock	O
.	O
</s>
<s>
Load	O
and	O
store	O
the	O
data	O
from/to	O
cache	B-General_Concept
or	O
DRAM	O
.	O
</s>
<s>
Each	O
SFU	O
executes	O
one	O
instruction	O
per	O
thread	B-Operating_System
,	O
per	O
clock	O
;	O
a	O
warp	O
executes	O
over	O
eight	O
clocks	O
.	O
</s>
<s>
Implements	O
the	O
new	O
IEEE	O
754-2008	O
floating-point	B-Algorithm
standard	O
,	O
providing	O
the	O
fused	O
multiply-add	O
(	O
FMA	O
)	O
instruction	O
for	O
both	O
single	O
and	O
double	O
precision	O
arithmetic	O
.	O
</s>
<s>
The	O
Fermi	B-General_Concept
architecture	I-General_Concept
uses	O
a	O
two-level	O
,	O
distributed	O
thread	B-Operating_System
scheduler	O
.	O
</s>
<s>
Note	O
that	O
64-bit	O
floating	B-Algorithm
point	I-Algorithm
operations	O
consumes	O
both	O
the	O
first	O
two	O
execution	O
columns	O
.	O
</s>
<s>
This	O
implies	O
that	O
an	O
SM	O
can	O
issue	O
up	O
to	O
32	O
single-precision	O
(	O
32-bit	O
)	O
floating	B-Algorithm
point	I-Algorithm
operations	O
or	O
16	O
double-precision	O
(	O
64-bit	O
)	O
floating	B-Algorithm
point	I-Algorithm
operations	O
at	O
a	O
time	O
.	O
</s>
<s>
The	O
GigaThread	O
engine	O
schedules	O
thread	B-Operating_System
blocks	O
to	O
various	O
SMs	O
.	O
</s>
<s>
At	O
the	O
SM	O
level	O
,	O
each	O
warp	O
scheduler	O
distributes	O
warps	O
of	O
32	O
threads	B-Operating_System
to	O
its	O
execution	O
units	O
.	O
</s>
<s>
Threads	B-Operating_System
are	O
scheduled	O
in	O
groups	O
of	O
32	O
threads	B-Operating_System
called	O
warps	O
.	O
</s>
<s>
Most	O
instructions	O
can	O
be	O
dual	O
issued	O
;	O
two	O
integer	O
instructions	O
,	O
two	O
floating	O
instructions	O
,	O
or	O
a	O
mix	O
of	O
integer	O
,	O
floating	B-Algorithm
point	I-Algorithm
,	O
load	O
,	O
store	O
,	O
and	O
SFU	O
instructions	O
can	O
be	O
issued	O
concurrently	O
.	O
</s>
<s>
The	O
theoretical	O
single-precision	O
processing	O
power	O
of	O
a	O
Fermi	B-General_Concept
GPU	B-Architecture
in	O
GFLOPS	O
is	O
computed	O
as	O
2	O
(	O
operations	O
per	O
FMA	O
instruction	O
per	O
CUDA	B-Architecture
core	O
per	O
cycle	O
)	O
×	O
number	O
of	O
CUDA	B-Architecture
cores	O
×	O
shader	O
clock	O
speed	O
(	O
in	O
GHz	O
)	O
.	O
</s>
<s>
Note	O
that	O
the	O
previous	O
generation	O
Tesla	B-Device
could	O
dual-issue	O
MAD+MUL	O
to	O
CUDA	B-Architecture
cores	O
and	O
SFUs	O
in	O
parallel	O
,	O
but	O
Fermi	B-General_Concept
lost	O
this	O
ability	O
as	O
it	O
can	O
only	O
issue	O
32	O
instructions	O
per	O
cycle	O
per	O
SM	O
which	O
keeps	O
just	O
its	O
32	O
CUDA	B-Architecture
cores	O
fully	O
utilized	O
.	O
</s>
<s>
Therefore	O
,	O
it	O
is	O
not	O
possible	O
to	O
leverage	O
the	O
SFUs	O
to	O
reach	O
more	O
than	O
2	O
operations	O
per	O
CUDA	B-Architecture
core	O
per	O
cycle	O
.	O
</s>
<s>
The	O
theoretical	O
double-precision	O
processing	O
power	O
of	O
a	O
Fermi	B-General_Concept
GPU	B-Architecture
is	O
1/2	O
of	O
the	O
single	O
precision	O
performance	O
on	O
GF100/110	O
.	O
</s>
<s>
However	O
,	O
in	O
practice	O
this	O
double-precision	O
power	O
is	O
only	O
available	O
on	O
professional	O
Quadro	B-Application
and	O
Tesla	B-Device
cards	O
,	O
while	O
consumer	O
GeForce	B-Application
cards	O
are	O
capped	O
to	O
1/8	O
.	O
</s>
<s>
L1	O
cache	B-General_Concept
per	O
SM	O
and	O
unified	O
L2	O
cache	B-General_Concept
that	O
services	O
all	O
operations	O
(	O
load	O
,	O
store	O
and	O
texture	O
)	O
.	O
</s>
<s>
Each	O
thread	B-Operating_System
has	O
access	O
to	O
its	O
own	O
registers	O
and	O
not	O
those	O
of	O
other	O
threads	B-Operating_System
.	O
</s>
<s>
The	O
maximum	O
number	O
of	O
registers	O
that	O
can	O
be	O
used	O
by	O
a	O
CUDA	B-Architecture
kernel	O
is	O
63	O
.	O
</s>
<s>
The	O
number	O
of	O
available	O
registers	O
degrades	O
gracefully	O
from	O
63	O
to	O
21	O
as	O
the	O
workload	O
(	O
and	O
hence	O
resource	O
requirements	O
)	O
increases	O
by	O
number	O
of	O
threads	B-Operating_System
.	O
</s>
<s>
Registers	O
have	O
a	O
very	O
high	O
bandwidth	B-Algorithm
:	O
about	O
8,000	O
GB/s	O
.	O
</s>
<s>
On-chip	O
memory	O
that	O
can	O
be	O
used	O
either	O
to	O
cache	B-General_Concept
data	O
for	O
individual	O
threads	B-Operating_System
(	O
register	O
spilling/L1	O
cache	B-General_Concept
)	O
and/or	O
to	O
share	O
data	O
among	O
several	O
threads	B-Operating_System
(	O
shared	O
memory	O
)	O
.	O
</s>
<s>
This	O
64	O
KB	O
memory	O
can	O
be	O
configured	O
as	O
either	O
48	O
KB	O
of	O
shared	O
memory	O
with	O
16	O
KB	O
of	O
L1	O
cache	B-General_Concept
,	O
or	O
16	O
KB	O
of	O
shared	O
memory	O
with	O
48	O
KB	O
of	O
L1	O
cache	B-General_Concept
.	O
</s>
<s>
Shared	O
memory	O
enables	O
threads	B-Operating_System
within	O
the	O
same	O
thread	B-Operating_System
block	O
to	O
cooperate	O
,	O
facilitates	O
extensive	O
reuse	O
of	O
on-chip	O
data	O
,	O
and	O
greatly	O
reduces	O
off-chip	O
traffic	O
.	O
</s>
<s>
Shared	O
memory	O
is	O
accessible	O
by	O
the	O
threads	B-Operating_System
in	O
the	O
same	O
thread	B-Operating_System
block	O
.	O
</s>
<s>
It	O
provides	O
low-latency	O
access	O
(	O
10-20	O
cycles	O
)	O
and	O
very	O
high	O
bandwidth	B-Algorithm
(	O
1,600	O
GB/s	O
)	O
to	O
moderate	O
amounts	O
of	O
data	O
(	O
such	O
as	O
intermediate	O
results	O
in	O
a	O
series	O
of	O
calculations	O
,	O
one	O
row	O
or	O
column	O
of	O
data	O
for	O
matrix	O
operations	O
,	O
a	O
line	O
of	O
video	O
,	O
etc	O
.	O
</s>
<s>
Register	O
spilling	O
occurs	O
when	O
a	O
thread	B-Operating_System
block	O
requires	O
more	O
register	O
storage	O
than	O
is	O
available	O
on	O
an	O
SM	O
.	O
</s>
<s>
768	O
KB	O
unified	O
L2	O
cache	B-General_Concept
,	O
shared	O
among	O
the	O
16	O
SMs	O
,	O
that	O
services	O
all	O
load	O
and	O
store	O
from/to	O
global	O
memory	O
,	O
including	O
copies	O
to/from	O
CPU	O
host	O
,	O
and	O
also	O
texture	O
requests	O
.	O
</s>
<s>
The	O
L2	O
cache	B-General_Concept
subsystem	O
also	O
implements	O
atomic	O
operations	O
,	O
used	O
for	O
managing	O
access	O
to	O
data	O
that	O
must	O
be	O
shared	O
across	O
thread	B-Operating_System
blocks	O
or	O
even	O
kernels	O
.	O
</s>
<s>
Accessible	O
by	O
all	O
threads	B-Operating_System
as	O
well	O
as	O
host	O
(	O
CPU	O
)	O
.	O
</s>
<s>
See	O
Nvidia	B-General_Concept
NVDEC	I-General_Concept
(	O
formerly	O
called	O
NVCUVID	B-General_Concept
)	O
as	O
well	O
as	O
Nvidia	O
PureVideo	O
.	O
</s>
<s>
The	O
Nvidia	B-General_Concept
NVENC	I-General_Concept
technology	O
was	O
not	O
available	O
yet	O
,	O
but	O
introduced	O
in	O
the	O
successor	O
,	O
Kepler	B-General_Concept
.	O
</s>
