<s>
The	O
Fairchild	B-General_Concept
F8	I-General_Concept
is	O
an	O
8-bit	O
microprocessor	B-Architecture
system	O
from	O
Fairchild	O
Semiconductor	O
,	O
announced	O
in	O
1974	O
and	O
shipped	O
in	O
1975	O
.	O
</s>
<s>
The	O
original	O
processor	O
family	O
included	O
four	O
main	O
40-pin	O
integrated	O
circuits	O
(	O
ICs	O
)	O
;	O
the	O
3850	O
CPU	O
which	O
was	O
the	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
,	O
the	O
3851	O
Program	O
Storage	O
Unit	O
(	O
PSU	O
)	O
which	O
contained	O
of	O
program	O
ROM	B-Device
and	O
handled	O
instruction	O
decoding	O
,	O
and	O
the	O
3852	O
Dynamic	O
Memory	O
Interface	O
(	O
DMI	O
)	O
or	O
3853	O
Static	O
Memory	O
Interface	O
(	O
SMI	O
)	O
to	O
control	O
additional	O
RAM	B-Architecture
or	O
ROM	B-Device
holding	O
the	O
user	O
programs	O
or	O
data	O
.	O
</s>
<s>
The	O
3854	O
DMA	O
was	O
an	O
optional	O
system	O
that	O
added	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
into	O
the	O
RAM	B-Architecture
controlled	O
by	O
the	O
3852	O
.	O
</s>
<s>
A	O
minimal	O
system	O
containing	O
a	O
3850	O
and	O
3851	O
also	O
included	O
four	O
8-bit	O
data	O
ports	O
,	O
64	O
bytes	O
of	O
RAM	B-Architecture
,	O
and	O
a	O
user	O
program	O
on	O
ROM	B-Device
.	O
</s>
<s>
This	O
allowed	O
microcontroller	B-Architecture
applications	O
to	O
be	O
built	O
using	O
just	O
two	O
chips	O
.	O
</s>
<s>
As	O
a	O
result	O
of	O
these	O
tradeoffs	O
,	O
the	O
F8	O
series	O
found	O
widespread	O
use	O
in	O
the	O
microcontroller	B-Architecture
market	O
but	O
saw	O
less	O
use	O
as	O
a	O
CPU	O
in	O
general-purpose	O
computers	O
.	O
</s>
<s>
More	O
important	O
,	O
Mostek	O
re-arranged	O
the	O
assembly	O
line	O
so	O
user	O
code	O
in	O
ROM	B-Device
was	O
added	O
at	O
the	O
last	O
step	O
,	O
greatly	O
reducing	O
the	O
cost	O
of	O
customizing	O
the	O
design	O
for	O
controller	O
use	O
.	O
</s>
<s>
The	O
F8	O
story	O
begins	O
with	O
a	O
microprocessor	B-Architecture
development	O
project	O
at	O
Olympia-Werke	O
,	O
a	O
subsidiary	O
of	O
AEG	O
.	O
</s>
<s>
The	O
F8	O
was	O
introduced	O
at	O
a	O
single-unit	O
price	O
of	O
,	O
making	O
it	O
less	O
expensive	O
than	O
contemporary	O
designs	O
like	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
or	O
Motorola	B-Device
6800	I-Device
which	O
were	O
at	O
least	O
twice	O
that	O
price	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
minimal	O
system	O
included	O
four	O
8-bit	O
input/output	B-General_Concept
ports	O
,	O
a	O
small	O
amount	O
of	O
RAM	B-Architecture
,	O
and	O
of	O
ROM	B-Device
.	O
</s>
<s>
In	O
contrast	O
,	O
designs	O
like	O
the	O
8080	B-General_Concept
supported	O
this	O
sort	O
of	O
functionality	O
using	O
separate	O
dedicated-purpose	O
ICs	O
,	O
often	O
dozens	O
,	O
so	O
an	O
F8	O
system	O
could	O
be	O
implemented	O
for	O
far	O
less	O
total	O
cost	O
.	O
</s>
<s>
Offsetting	O
this	O
to	O
some	O
degree	O
was	O
that	O
the	O
program	O
ROM	B-Device
in	O
the	O
PSU	O
was	O
masked	B-Algorithm
onto	O
the	O
chips	O
early	O
in	O
the	O
production	O
process	O
,	O
which	O
required	O
separate	O
production	O
lines	O
for	O
each	O
customer	O
.	O
</s>
<s>
Although	O
the	O
F8	O
was	O
marketed	O
as	O
a	O
general-purpose	O
microprocessor	B-Architecture
,	O
historically	O
it	O
represents	O
the	O
first	O
purpose-designed	O
8-bit	O
microcontroller	B-Architecture
,	O
a	O
design	O
that	O
implements	O
a	O
complete	O
computer	O
system	O
on	O
a	O
small	O
number	O
of	O
ICs	O
.	O
</s>
<s>
Its	O
release	O
had	O
a	O
profound	O
influence	O
on	O
the	O
market	O
,	O
and	O
led	O
to	O
the	O
introduction	O
of	O
dedicated	O
microcontrollers	B-Architecture
from	O
most	O
other	O
vendors	O
,	O
among	O
them	O
the	O
Intel	B-Device
MCS-48	I-Device
,	O
Motorola	O
MC6801	O
and	O
MOS	B-General_Concept
6510	I-General_Concept
,	O
all	O
of	O
which	O
combined	O
various	O
systems	O
formerly	O
left	O
to	O
the	O
circuit	O
board	O
designer	O
to	O
implement	O
.	O
</s>
<s>
The	O
line	O
was	O
also	O
updated	O
with	O
the	O
addition	O
of	O
the	O
3856	O
,	O
a	O
3851	O
with	O
of	O
ROM	B-Device
,	O
and	O
the	O
3857	O
,	O
a	O
3856	O
with	O
additional	O
address	O
lines	O
to	O
access	O
external	O
ROM	B-Device
in	O
addition	O
to	O
the	O
2KB	O
internal	O
,	O
eliminating	O
the	O
need	O
for	O
a	O
separate	O
3853	O
in	O
many	O
roles	O
.	O
</s>
<s>
A	O
much	O
more	O
important	O
change	O
was	O
that	O
custom	O
ROM	B-Device
code	O
was	O
now	O
masked	B-Algorithm
onto	O
the	O
IC	O
as	O
the	O
very	O
last	O
step	O
in	O
the	O
process	O
,	O
so	O
all	O
of	O
the	O
CPUs	O
were	O
identical	O
until	O
the	O
end	O
of	O
the	O
production	O
line	O
.	O
</s>
<s>
Among	O
the	O
most	O
important	O
of	O
these	O
was	O
the	O
addition	O
of	O
a	O
socket	O
on	O
top	O
of	O
the	O
chip	O
that	O
allowed	O
an	O
EPROM	B-General_Concept
to	O
be	O
plugged	O
in	O
with	O
no	O
other	O
support	O
circuitry	O
required	O
.	O
</s>
<s>
This	O
eliminated	O
the	O
need	O
for	O
the	O
on-board	O
ROM	B-Device
and	O
allowed	O
customers	O
to	O
produce	O
their	O
own	O
ROM	B-Device
and	O
eliminate	O
the	O
masking	O
fees	O
.	O
</s>
<s>
Variations	O
also	O
included	O
examples	O
with	O
more	O
ROM	B-Device
or	O
RAM	B-Architecture
or	O
other	O
more	O
minor	O
changes	O
.	O
</s>
<s>
Although	O
little-known	O
today	O
,	O
"	O
in	O
1977	O
the	O
F8	O
was	O
the	O
world	O
's	O
leading	O
microprocessor	B-Architecture
in	O
terms	O
of	O
CPU	O
sales.	O
"	O
</s>
<s>
The	O
design	O
remains	O
somewhat	O
obscure	O
because	O
most	O
of	O
those	O
uses	O
were	O
as	O
embedded	O
microcontrollers	B-Architecture
where	O
the	O
chip	O
inside	O
the	O
device	O
is	O
rarely	O
identified	O
,	O
as	O
opposed	O
to	O
products	O
like	O
home	O
computers	O
where	O
the	O
CPU	O
inside	O
is	O
better	O
known	O
.	O
</s>
<s>
Among	O
its	O
few	O
better-known	O
uses	O
were	O
the	O
Fairchild	B-Operating_System
Channel	I-Operating_System
F	I-Operating_System
in	O
1976	O
,	O
and	O
in	O
the	O
VideoBrain	B-Device
Computer	I-Device
system	O
in	O
1977	O
.	O
</s>
<s>
Both	O
were	O
wiped	O
out	O
of	O
the	O
market	O
by	O
the	O
introduction	O
of	O
the	O
Atari	B-General_Concept
2600	I-General_Concept
in	O
1977	O
.	O
</s>
<s>
The	O
PSU	O
contained	O
a	O
program	O
known	O
as	O
"	O
Fairbug	O
"	O
that	O
could	O
be	O
accessed	O
using	O
a	O
terminal	B-General_Concept
connected	O
to	O
the	O
CPU	O
over	O
its	O
8-bit	O
I/O	B-General_Concept
port	O
.	O
</s>
<s>
A	O
typical	O
computer	O
system	O
generally	O
requires	O
a	O
CPU	O
,	O
some	O
form	O
of	O
input/output	B-General_Concept
to	O
communicate	O
with	O
the	O
outside	O
world	O
,	O
and	O
memory	O
holding	O
the	O
program	O
code	O
and	O
user	O
data	O
.	O
</s>
<s>
Typically	O
,	O
I/O	B-General_Concept
would	O
be	O
handled	O
by	O
dedicated	O
chips	O
,	O
and	O
memory	O
would	O
be	O
accessed	O
through	O
an	O
address	B-Architecture
bus	I-Architecture
selecting	O
locations	O
in	O
external	O
memory	O
and	O
then	O
returning	O
that	O
data	O
to	O
the	O
CPU	O
over	O
a	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Depending	O
on	O
the	O
design	O
,	O
the	O
I/O	B-General_Concept
would	O
communicate	O
with	O
the	O
processor	O
over	O
a	O
dedicated	O
bus	O
,	O
or	O
alternately	O
by	O
placing	O
data	O
in	O
memory	O
and	O
then	O
having	O
the	O
CPU	O
read	O
it	O
.	O
</s>
<s>
In	O
particular	O
,	O
implementing	O
an	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
,	O
16-bit	O
address	B-Architecture
bus	I-Architecture
and	O
another	O
8-bit	O
I/O	B-General_Concept
bus	I-General_Concept
would	O
leave	O
only	O
8	O
more	O
pins	O
for	O
every	O
other	O
function	O
,	O
from	O
power	O
supply	O
and	O
ground	O
to	O
the	O
various	O
clock	O
signals	O
and	O
control	O
lines	O
.	O
</s>
<s>
Other	O
designs	O
sometimes	O
multiplexed	B-Architecture
the	O
address	O
and	O
data	O
lines	O
so	O
the	O
same	O
pins	O
could	O
be	O
used	O
for	O
multiple	O
functions	O
,	O
at	O
the	O
cost	O
of	O
requiring	O
more	O
cycles	O
to	O
complete	O
an	O
operation	O
.	O
</s>
<s>
The	O
F8	O
addressed	O
this	O
problem	O
by	O
internalizing	O
some	O
of	O
the	O
functions	O
,	O
like	O
adding	O
a	O
small	O
amount	O
of	O
RAM	B-Architecture
to	O
the	O
CPU	O
core	O
,	O
while	O
moving	O
others	O
out	O
of	O
the	O
CPU	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
there	O
is	O
no	O
need	O
for	O
an	O
address	B-Architecture
bus	I-Architecture
at	O
all	O
;	O
the	O
RAM	B-Architecture
is	O
contained	O
in	O
the	O
3850	O
and	O
the	O
program	O
ROM	B-Device
in	O
the	O
3851	O
.	O
</s>
<s>
It	O
is	O
the	O
PSU	O
that	O
is	O
responsible	O
for	O
keeping	O
track	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
fetching	O
instructions	O
from	O
the	O
internal	O
ROM	B-Device
and	O
feeding	O
them	O
to	O
the	O
3850	O
for	O
processing	O
over	O
a	O
dedicated	O
5-pin	O
instruction	O
bus	O
along	O
with	O
any	O
associated	O
data	O
over	O
the	O
separate	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
This	O
freed	O
up	O
11	O
pins	O
that	O
would	O
otherwise	O
be	O
used	O
for	O
additional	O
address	O
lines	O
,	O
which	O
,	O
along	O
with	O
other	O
simplifications	O
and	O
splitting	O
of	O
duty	O
,	O
allowed	O
the	O
CPU	O
to	O
have	O
two	O
complete	O
I/O	B-General_Concept
busses	O
.	O
</s>
<s>
The	O
3851	O
added	O
another	O
two	O
I/O	B-General_Concept
ports	O
,	O
so	O
that	O
a	O
minimal	O
system	O
had	O
four	O
ports	O
in	O
total	O
.	O
</s>
<s>
With	O
only	O
1KB	O
of	O
ROM	B-Device
and	O
64	O
bytes	O
of	O
RAM	B-Architecture
,	O
only	O
small	O
programs	O
can	O
be	O
managed	O
,	O
but	O
for	O
many	O
systems	O
,	O
like	O
cash	O
registers	O
,	O
gasoline	O
pumps	O
and	O
similar	O
roles	O
,	O
this	O
is	O
more	O
than	O
enough	O
.	O
</s>
<s>
These	O
interface	O
with	O
the	O
PSU	O
and	O
contain	O
additional	O
logic	O
for	O
handling	O
their	O
associated	O
memory	O
;	O
for	O
instance	O
,	O
the	O
3852	O
had	O
a	O
complete	O
address	B-Architecture
bus	I-Architecture
able	O
to	O
access	O
64KB	O
of	O
RAM	B-Architecture
and	O
the	O
circuitry	O
needed	O
to	O
refresh	O
the	O
data	O
.	O
</s>
<s>
The	O
PSU	O
is	O
still	O
required	O
in	O
these	O
systems	O
,	O
and	O
the	O
program	B-General_Concept
counter	I-General_Concept
and	O
other	O
pointers	O
are	O
maintained	O
separately	O
in	O
all	O
of	O
these	O
chips	O
by	O
reading	O
the	O
same	O
control	O
lines	O
.	O
</s>
<s>
The	O
main	O
difference	O
between	O
the	O
3852	O
and	O
3853	O
was	O
that	O
the	O
former	O
included	O
the	O
dynamic	O
RAM	B-Architecture
refresh	O
circuitry	O
and	O
a	O
3-pin	O
link	O
to	O
the	O
3854	O
DMA	B-General_Concept
controller	I-General_Concept
,	O
while	O
the	O
3853	O
removed	O
these	O
and	O
added	O
a	O
new	O
interrupt	O
handler	O
and	O
timer	O
.	O
</s>
<s>
The	O
3854	O
DMA	B-General_Concept
controller	I-General_Concept
was	O
linked	O
directly	O
to	O
the	O
3852	O
RAM	B-Architecture
controller	O
and	O
did	O
not	O
use	O
the	O
5-pin	O
control	O
bus	O
found	O
on	O
the	O
other	O
members	O
of	O
the	O
family	O
.	O
</s>
<s>
Internally	O
,	O
the	O
CPU	O
contained	O
an	O
8-bit	O
accumulator	B-General_Concept
,	O
a	O
5-bit	O
processor	O
status	B-General_Concept
register	I-General_Concept
,	O
a	O
6-bit	O
"	O
Indirect	O
Scratchpad	O
Address	O
Register	O
"	O
,	O
or	O
ISAR	O
,	O
and	O
64	O
bytes	O
of	O
"	O
scratchpad	O
"	O
RAM	B-Architecture
.	O
</s>
<s>
The	O
first	O
twelve	O
locations	O
within	O
the	O
RAM	B-Architecture
can	O
be	O
directly	O
accessed	O
and	O
used	O
as	O
secondary	O
accumulators	B-General_Concept
,	O
labeled	O
A	O
through	O
J	O
.	O
</s>
<s>
The	O
3851/3852/3853	O
contain	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
,	O
along	O
with	O
a	O
secondary	O
program	B-General_Concept
counter	I-General_Concept
,	O
.	O
</s>
<s>
The	O
instruction	O
set	O
included	O
70	O
opcodes	B-Language
encoded	O
in	O
8-bits	O
.	O
</s>
<s>
As	O
was	O
typical	O
of	O
the	O
era	O
,	O
many	O
instructions	O
had	O
a	O
variety	O
of	O
addressing	O
modes	O
with	O
some	O
of	O
the	O
modes	O
encoded	O
in	O
the	O
instruction	B-Language
opcode	I-Language
.	O
</s>
<s>
The	O
version	O
starting	O
with	O
was	O
followed	O
by	O
two	O
zero	O
bits	O
and	O
then	O
another	O
two	O
bits	O
indicating	O
locations	O
in	O
the	O
scratchpad	O
in	O
locations	O
12	O
through	O
15	O
,	O
so	O
this	O
used	O
opcodes	B-Language
through	O
.	O
</s>
<s>
The	O
machine	O
instructions	O
can	O
be	O
grouped	O
into	O
six	O
categories	O
:	O
accumulator	B-General_Concept
instructions	O
,	O
branch	O
instructions	O
,	O
memory	O
reference	O
instructions	O
,	O
address	O
register	O
instructions	O
,	O
scratchpad	O
register	O
instruction	O
,	O
miscellaneous	O
instructions	O
(	O
interrupt	O
,	O
input	O
,	O
output	O
,	O
indirect	O
scratchpad	O
register	O
,	O
load	O
,	O
and	O
store	O
)	O
.	O
</s>
<s>
In	O
the	O
F8	O
the	O
control	O
bus	O
regulates	O
the	O
use	O
of	O
the	O
data	B-General_Concept
bus	I-General_Concept
through	O
the	O
use	O
of	O
timing	O
signals	O
and	O
state	O
controls	O
.	O
</s>
<s>
Fairchild	O
provided	O
development	O
and	O
evaluation	O
kits	O
for	O
the	O
F8	O
,	O
these	O
kits	O
included	O
a	O
3851A	O
PSU	O
(	O
Program	O
Storage	O
Unit	O
)	O
which	O
contained	O
a	O
monitor	O
in	O
mask	B-Device
ROM	I-Device
,	O
vectored	O
to	O
start	O
at	O
address	O
0x8080	O
.	O
</s>
<s>
At	O
power-on	O
,	O
the	O
ROM	B-Device
was	O
entered	O
.	O
</s>
<s>
The	O
ROM	B-Device
monitor	O
was	O
referred	O
to	O
in	O
Fairchild	O
literature	O
as	O
FAIR-BUG	O
.	O
</s>
<s>
FAIR-BUG	O
is	O
essentially	O
a	O
random	O
access	O
management	O
routine	O
for	O
all	O
memory	O
,	O
both	O
RAM	B-Architecture
and	O
ROM	B-Device
,	O
and	O
all	O
registers	O
including	O
program	B-General_Concept
counter	I-General_Concept
,	O
data	O
counter	O
,	O
and	O
scratchpad	O
.	O
</s>
<s>
The	O
programmer	O
can	O
then	O
use	O
the	O
G	O
command	O
to	O
load	O
a	O
specific	O
address	O
into	O
the	O
program	B-General_Concept
counter	I-General_Concept
and	O
execute	O
the	O
routine	O
at	O
that	O
address	O
.	O
</s>
