<s>
FASTBUS	B-Architecture
(	O
IEEE	O
960	O
)	O
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
standard	O
,	O
originally	O
intended	O
to	O
replace	O
Computer	B-Architecture
Automated	I-Architecture
Measurement	I-Architecture
and	I-Architecture
Control	I-Architecture
(	O
CAMAC	O
)	O
in	O
high-speed	O
,	O
large-scale	O
data	O
acquisition	O
.	O
</s>
<s>
It	O
is	O
also	O
a	O
modular	O
crate	O
electronics	O
standard	O
commonly	O
used	O
in	O
data	O
acquisition	O
systems	O
in	O
particle	B-Algorithm
detectors	I-Algorithm
.	O
</s>
<s>
A	O
FASTBUS	B-Architecture
system	O
consists	O
of	O
one	O
or	O
more	O
segments	O
.	O
</s>
<s>
Segments	O
are	O
connected	O
together	O
using	O
a	O
segment	O
interconnect	B-General_Concept
(	O
SI	O
)	O
.	O
</s>
<s>
A	O
crate	O
segment	O
typically	O
consists	O
of	O
a	O
backplane	O
with	O
slots	O
to	O
hold	O
up	O
to	O
26	O
modules	O
,	O
mounted	O
in	O
a	O
19-inch	B-Application
rack	I-Application
.	O
</s>
<s>
Each	O
module	O
is	O
typically	O
a	O
printed	O
circuit	O
board	O
with	O
a	O
front	O
panel	O
,	O
similar	O
to	O
a	O
blade	B-Architecture
PC	I-Architecture
.	O
</s>
<s>
Small	O
systems	O
may	O
consist	O
of	O
only	O
one	O
crate	O
segment	O
,	O
or	O
a	O
small	O
number	O
of	O
independent	O
crate	O
segments	O
connected	O
directly	O
to	O
a	O
central	O
computer	O
rather	O
than	O
using	O
segment	O
interconnects	B-General_Concept
.	O
</s>
<s>
FASTBUS	B-Architecture
uses	O
the	O
emitter	B-General_Concept
coupled	I-General_Concept
logic	I-General_Concept
(	O
ECL	O
)	O
electrical	O
standard	O
,	O
which	O
allows	O
higher	O
speed	O
than	O
TTL	O
and	O
generates	O
less	O
switching	O
noise	O
.	O
</s>
<s>
The	O
FASTBUS	B-Architecture
standard	O
also	O
has	O
+15V	O
and	O
-15V	O
pins	O
on	O
the	O
backplane	O
,	O
which	O
are	O
typically	O
fed	O
with	O
very	O
small	O
power	O
supplies	O
as	O
most	O
modules	O
use	O
very	O
little	O
+	O
/	O
-	O
15V	O
(	O
or	O
any	O
at	O
all	O
)	O
.	O
</s>
<s>
A	O
FASTBUS	B-Architecture
crate	O
is	O
quite	O
a	O
bit	O
taller	O
than	O
other	O
types	O
of	O
electronics	O
crates	O
.	O
</s>
<s>
The	O
power	O
supply	O
for	O
a	O
FASTBUS	B-Architecture
crate	O
is	O
typically	O
mounted	O
below	O
the	O
crate	O
,	O
rather	O
than	O
being	O
integral	O
for	O
the	O
crate	O
itself	O
,	O
taking	O
up	O
even	O
more	O
vertical	O
rack	O
space	O
.	O
</s>
<s>
FASTBUS	B-Architecture
was	O
conceived	O
as	O
a	O
replacement	O
for	O
CAMAC	O
in	O
data	O
acquisition	O
systems	O
.	O
</s>
<s>
FASTBUS	B-Architecture
sought	O
improvement	O
in	O
all	O
these	O
areas	O
by	O
using	O
a	O
faster	O
bus	O
logic	O
(	O
ECL	O
)	O
,	O
an	O
asynchronous	B-General_Concept
bus	I-General_Concept
protocol	O
,	O
and	O
a	O
sophisticated	O
multi-segment	O
design	O
.	O
</s>
<s>
Later	O
developments	O
have	O
moved	O
to	O
high-speed	O
serial	O
protocols	O
such	O
as	O
SATA	O
,	O
leaving	O
designs	O
such	O
as	O
the	O
FASTBUS	B-Architecture
serial	O
segment	O
as	O
a	O
technological	O
dead	O
end	O
.	O
</s>
<s>
FASTBUS	B-Architecture
was	O
used	O
in	O
many	O
high-energy	O
physics	O
experiments	O
during	O
the	O
1980s	O
,	O
principally	O
at	O
laboratories	O
involved	O
in	O
the	O
development	O
of	O
the	O
standard	O
.	O
</s>
<s>
FASTBUS	B-Architecture
has	O
now	O
largely	O
been	O
replaced	O
by	O
VMEbus	B-Architecture
in	O
smaller-scale	O
systems	O
and	O
by	O
custom	O
designs	O
(	O
which	O
have	O
lower	O
per-channel	O
cost	O
)	O
in	O
large	O
systems	O
.	O
</s>
<s>
The	O
system	O
interconnect	B-General_Concept
modules	O
were	O
also	O
complex	O
and	O
expensive	O
,	O
again	O
discouraging	O
cable	O
segment	O
use	O
.	O
</s>
<s>
These	O
problems	O
,	O
together	O
with	O
the	O
late	O
development	O
of	O
inexpensive	O
protocol	O
chips	O
,	O
hindered	O
the	O
expression	O
of	O
the	O
full	O
potential	O
of	O
FASTBUS	B-Architecture
multi-segment	O
architecture	O
.	O
</s>
