<s>
Explicit	B-Architecture
data	I-Architecture
graph	I-Architecture
execution	I-Architecture
,	O
or	O
EDGE	O
,	O
is	O
a	O
type	O
of	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
which	O
intends	O
to	O
improve	O
computing	O
performance	O
compared	O
to	O
common	O
processors	O
like	O
the	O
Intel	B-Operating_System
x86	I-Operating_System
line	O
.	O
</s>
<s>
In	O
the	O
1960s	O
memory	O
was	O
relatively	O
expensive	O
,	O
and	O
CPU	O
designers	O
produced	O
instruction	B-General_Concept
sets	I-General_Concept
that	O
densely	O
encoded	O
instructions	O
and	O
data	O
in	O
order	O
to	O
better	O
utilize	O
this	O
resource	O
.	O
</s>
<s>
In	O
1964	O
,	O
IBM	O
introduced	O
its	O
System/360	B-Application
series	O
which	O
used	O
microcode	B-Device
to	O
allow	O
a	O
single	O
expansive	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
to	O
run	O
across	O
a	O
wide	O
variety	O
of	O
machines	O
by	O
implementing	O
more	O
or	O
less	O
instructions	O
in	O
hardware	O
depending	O
on	O
the	O
need	O
.	O
</s>
<s>
This	O
style	O
of	O
memory	O
access	O
with	O
wide	O
variety	O
of	O
modes	O
led	O
to	O
instruction	B-General_Concept
sets	I-General_Concept
with	O
hundreds	O
of	O
different	O
instructions	O
,	O
a	O
style	O
known	O
today	O
as	O
CISC	B-Architecture
(	O
Complex	B-Architecture
Instruction	I-Architecture
Set	I-Architecture
Computing	I-Architecture
)	O
.	O
</s>
<s>
This	O
study	O
demonstrated	O
that	O
the	O
complex	O
ISA	O
was	O
in	O
fact	O
a	O
significant	O
problem	O
;	O
because	O
only	O
the	O
most	O
basic	O
instructions	O
were	O
guaranteed	O
to	O
be	O
implemented	O
in	O
hardware	O
,	O
compilers	B-Language
ignored	O
the	O
more	O
complex	O
ones	O
that	O
only	O
ran	O
in	O
hardware	O
on	O
certain	O
machines	O
.	O
</s>
<s>
Further	O
,	O
even	O
when	O
the	O
program	O
called	O
one	O
of	O
those	O
five	O
instructions	O
,	O
the	O
microcode	B-Device
required	O
a	O
finite	O
time	O
to	O
decode	O
it	O
,	O
even	O
if	O
it	O
was	O
just	O
to	O
call	O
the	O
internal	O
hardware	O
.	O
</s>
<s>
Their	O
work	O
,	O
known	O
at	O
the	O
time	O
as	O
the	O
IBM	B-Device
801	I-Device
,	O
eventually	O
led	O
to	O
the	O
RISC	B-Architecture
(	O
Reduced	B-Architecture
Instruction	I-Architecture
Set	I-Architecture
Computing	I-Architecture
)	O
concept	O
.	O
</s>
<s>
Microcode	B-Device
was	O
removed	O
,	O
and	O
only	O
the	O
most	O
basic	O
versions	O
of	O
any	O
given	O
instruction	O
were	O
put	O
into	O
the	O
CPU	O
.	O
</s>
<s>
Any	O
more	O
complex	O
code	O
was	O
left	O
to	O
the	O
compiler	B-Language
.	O
</s>
<s>
The	O
removal	O
of	O
so	O
much	O
circuitry	O
,	O
about	O
of	O
the	O
transistors	O
in	O
the	O
Motorola	B-Device
68000	I-Device
for	O
instance	O
,	O
allowed	O
the	O
CPU	O
to	O
include	O
more	O
registers	O
,	O
which	O
had	O
a	O
direct	O
impact	O
on	O
performance	O
.	O
</s>
<s>
By	O
the	O
mid-1980s	O
,	O
further	O
developed	O
versions	O
of	O
these	O
basic	O
concepts	O
were	O
delivering	O
performance	O
as	O
much	O
as	O
10	O
times	O
that	O
of	O
the	O
fastest	O
CISC	B-Architecture
designs	O
,	O
in	O
spite	O
of	O
using	O
less-developed	O
fabrication	O
.	O
</s>
<s>
To	O
improve	O
performance	O
,	O
CPU	O
designs	O
started	O
adding	O
internal	O
parallelism	O
,	O
becoming	O
"	O
superscalar	B-General_Concept
"	O
.	O
</s>
<s>
The	O
amount	O
of	O
parallelism	O
that	O
can	O
be	O
extracted	O
in	O
superscalar	B-General_Concept
designs	O
is	O
limited	O
by	O
the	O
number	O
of	O
instructions	O
that	O
the	O
scheduler	O
can	O
examine	O
for	O
interdependencies	O
.	O
</s>
<s>
Despite	O
massive	O
efforts	O
,	O
CPU	O
designs	O
using	O
classic	O
RISC	B-Architecture
or	O
CISC	B-Architecture
ISA	O
's	O
have	O
plateaued	O
at	O
about	O
three	O
or	O
four	O
functional	O
units	O
.	O
</s>
<s>
Additional	O
performance	O
can	O
be	O
wrung	O
from	O
systems	O
by	O
examining	O
the	O
instructions	O
to	O
find	O
ones	O
that	O
operate	O
on	O
different	O
types	O
of	O
data	O
and	O
adding	O
units	O
dedicated	O
to	O
that	O
sort	O
of	O
data	O
;	O
this	O
has	O
led	O
to	O
the	O
introduction	O
of	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
and	O
,	O
more	O
recently	O
,	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
units	O
.	O
</s>
<s>
That	O
means	O
that	O
the	O
relative	O
distance	O
between	O
any	O
one	O
function	O
unit	O
and	O
the	O
global	O
register	B-General_Concept
file	O
has	O
grown	O
over	O
time	O
.	O
</s>
<s>
Once	O
introduced	O
in	O
order	O
to	O
avoid	O
delays	O
in	O
talking	O
to	O
main	O
memory	O
,	O
the	O
global	O
register	B-General_Concept
file	O
has	O
itself	O
become	O
a	O
delay	O
that	O
is	O
worth	O
avoiding	O
.	O
</s>
<s>
Just	O
as	O
the	O
delays	O
talking	O
to	O
memory	O
while	O
its	O
price	O
fell	O
suggested	O
a	O
radical	O
change	O
in	O
ISA	O
(	O
Instruction	B-General_Concept
Set	I-General_Concept
Architecture	I-General_Concept
)	O
from	O
CISC	B-Architecture
to	O
RISC	B-Architecture
,	O
designers	O
are	O
considering	O
whether	O
the	O
problems	O
scaling	O
in	O
parallelism	O
and	O
the	O
increasing	O
delays	O
talking	O
to	O
registers	O
demands	O
another	O
switch	O
in	O
basic	O
ISA	O
.	O
</s>
<s>
Among	O
the	O
ways	O
to	O
introduce	O
a	O
new	O
ISA	O
are	O
the	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
architectures	O
,	O
typified	O
by	O
the	O
Itanium	B-General_Concept
.	O
</s>
<s>
VLIW	B-General_Concept
moves	O
the	O
scheduler	O
logic	O
out	O
of	O
the	O
CPU	O
and	O
into	O
the	O
compiler	B-Language
,	O
where	O
it	O
has	O
much	O
more	O
memory	O
and	O
longer	O
timelines	O
to	O
examine	O
the	O
instruction	O
stream	O
.	O
</s>
<s>
This	O
static	O
placement	O
,	O
static	O
issue	O
execution	O
model	O
works	O
well	O
when	O
all	O
delays	O
are	O
known	O
,	O
but	O
in	O
the	O
presence	O
of	O
cache	O
latencies	O
,	O
filling	O
instruction	O
words	O
has	O
proven	O
to	O
be	O
a	O
difficult	O
challenge	O
for	O
the	O
compiler	B-Language
.	O
</s>
<s>
An	O
instruction	O
that	O
might	O
take	O
five	O
cycles	O
if	O
the	O
data	O
is	O
in	O
the	O
cache	O
could	O
take	O
hundreds	O
if	O
it	O
is	O
not	O
,	O
but	O
the	O
compiler	B-Language
has	O
no	O
way	O
to	O
know	O
whether	O
that	O
data	O
will	O
be	O
in	O
the	O
cache	O
at	O
runtime	O
that	O
's	O
determined	O
by	O
overall	O
system	O
load	O
and	O
other	O
factors	O
that	O
have	O
nothing	O
to	O
do	O
with	O
the	O
program	O
being	O
compiled	B-Language
.	O
</s>
<s>
VLIW	B-General_Concept
uses	O
a	O
static	O
placement	O
,	O
static	O
issue	O
model	O
,	O
but	O
has	O
proven	O
difficult	O
to	O
master	O
because	O
the	O
runtime	O
behavior	O
of	O
programs	O
is	O
difficult	O
to	O
predict	O
and	O
properly	O
schedule	O
in	O
advance	O
.	O
</s>
<s>
EDGE	O
systems	O
compile	B-Language
source	O
code	O
into	O
a	O
form	O
consisting	O
of	O
statically-allocated	O
hyperblocks	O
containing	O
many	O
individual	O
instructions	O
,	O
hundreds	O
or	O
thousands	O
.	O
</s>
<s>
EDGE	O
thus	O
combines	O
the	O
advantages	O
of	O
the	O
VLIW	B-General_Concept
concept	O
of	O
looking	O
for	O
independent	O
data	O
at	O
compile	B-Language
time	O
,	O
with	O
the	O
superscalar	B-General_Concept
RISC	B-Architecture
concept	O
of	O
executing	O
the	O
instructions	O
when	O
the	O
data	O
for	O
them	O
becomes	O
available	O
.	O
</s>
<s>
This	O
information	O
is	O
lost	O
as	O
the	O
high	B-Language
level	I-Language
language	I-Language
is	O
converted	O
into	O
the	O
processor	O
's	O
much	O
simpler	O
ISA	O
.	O
</s>
<s>
But	O
this	O
information	O
is	O
so	O
useful	O
that	O
modern	O
compilers	B-Language
have	O
generalized	O
the	O
concept	O
as	O
the	O
"	O
basic	B-Application
block	I-Application
"	O
,	O
attempting	O
to	O
identify	O
them	O
within	O
programs	O
while	O
they	O
optimize	O
memory	O
access	O
through	O
the	O
registers	O
.	O
</s>
<s>
Since	O
basic	B-Application
blocks	I-Application
access	O
memory	O
in	O
well-defined	O
ways	O
,	O
the	O
processor	O
can	O
load	O
up	O
related	O
blocks	O
and	O
schedule	O
them	O
so	O
that	O
the	O
output	O
of	O
one	O
block	O
feeds	O
directly	O
into	O
the	O
one	O
that	O
will	O
consume	O
its	O
data	O
.	O
</s>
<s>
This	O
eliminates	O
the	O
need	O
for	O
a	O
global	O
register	B-General_Concept
file	O
,	O
and	O
simplifies	O
the	O
compiler	B-Language
's	O
task	O
in	O
scheduling	O
access	O
to	O
the	O
registers	O
by	O
the	O
program	O
as	O
a	O
whole	O
instead	O
,	O
each	O
basic	B-Application
block	I-Application
is	O
given	O
its	O
own	O
local	O
registers	O
and	O
the	O
compiler	B-Language
optimizes	O
access	O
within	O
the	O
block	O
,	O
a	O
much	O
simpler	O
task	O
.	O
</s>
<s>
EDGE	O
systems	O
bear	O
a	O
strong	O
resemblance	O
to	O
dataflow	B-Application
languages	I-Application
from	O
the	O
1960s	O
–	O
1970s	O
,	O
and	O
again	O
in	O
the	O
1990s	O
.	O
</s>
<s>
Due	O
to	O
the	O
isolation	O
of	O
data	O
,	O
similar	O
to	O
EDGE	O
,	O
dataflow	B-Application
languages	I-Application
are	O
inherently	O
parallel	O
,	O
and	O
interest	O
in	O
them	O
followed	O
the	O
more	O
general	O
interest	O
in	O
massive	O
parallelism	O
as	O
a	O
solution	O
to	O
general	O
computing	O
problems	O
.	O
</s>
<s>
Another	O
reason	O
that	O
dataflow	O
systems	O
never	O
became	O
popular	O
is	O
that	O
compilers	B-Language
of	O
the	O
era	O
found	O
it	O
difficult	O
to	O
work	O
with	O
common	O
imperative	O
languages	O
like	O
C++	B-Language
.	O
</s>
<s>
Instead	O
,	O
most	O
dataflow	O
systems	O
used	O
dedicated	O
languages	O
like	O
Prograph	B-Language
,	O
which	O
limited	O
their	O
commercial	O
interest	O
.	O
</s>
<s>
A	O
decade	O
of	O
compiler	B-Language
research	O
has	O
eliminated	O
many	O
of	O
these	O
problems	O
,	O
and	O
a	O
key	O
difference	O
between	O
dataflow	O
and	O
EDGE	O
approaches	O
is	O
that	O
EDGE	O
designs	O
intend	O
to	O
work	O
with	O
commonly	O
used	O
languages	O
.	O
</s>
<s>
Due	O
to	O
the	O
information	O
encoded	O
into	O
the	O
block	O
by	O
the	O
compiler	B-Language
,	O
the	O
scheduler	O
can	O
examine	O
an	O
entire	O
block	O
to	O
see	O
if	O
its	O
inputs	O
are	O
available	O
and	O
send	O
it	O
into	O
an	O
engine	O
for	O
execution	O
there	O
is	O
no	O
need	O
to	O
examine	O
the	O
individual	O
instructions	O
within	O
.	O
</s>
<s>
Unlike	O
modern	O
CPU	O
designs	O
where	O
different	O
portions	O
of	O
the	O
CPU	O
are	O
dedicated	O
to	O
different	O
sorts	O
of	O
data	O
,	O
an	O
EDGE	O
CPU	O
would	O
normally	O
consist	O
of	O
a	O
single	O
type	O
of	O
ALU-like	O
unit	O
.	O
</s>
<s>
issue	O
at	O
most	O
32	O
register	B-General_Concept
bank	O
reads	O
and/or	O
writes	O
,	O
</s>
<s>
The	O
TRIPS	O
compiler	B-Language
statically	O
bundles	O
instructions	O
into	O
hyperblocks	O
,	O
but	O
also	O
statically	O
compiles	B-Language
these	O
blocks	O
to	O
run	O
on	O
particular	O
ALUs	O
.	O
</s>
<s>
This	O
means	O
that	O
TRIPS	O
programs	O
have	O
some	O
dependency	O
on	O
the	O
precise	O
implementation	O
they	O
are	O
compiled	B-Language
for	O
.	O
</s>
<s>
CMU	O
's	O
CASH	O
is	O
a	O
compiler	B-Language
that	O
produces	O
an	O
intermediate	O
code	O
called	O
"	O
Pegasus	O
"	O
.	O
</s>
