<s>
The	O
ESPRESSO	O
logic	O
minimizer	O
is	O
a	O
computer	O
program	O
using	O
heuristic	B-Algorithm
and	O
specific	O
algorithms	O
for	O
efficiently	O
reducing	O
the	O
complexity	O
of	O
digital	O
logic	O
gate	O
circuits	O
.	O
</s>
<s>
ESPRESSO-I	O
was	O
originally	O
developed	O
at	O
IBM	O
by	O
Robert	B-Algorithm
K	I-Algorithm
.	I-Algorithm
Brayton	I-Algorithm
et	O
al	O
.	O
</s>
<s>
All	O
digital	O
systems	O
are	O
composed	O
of	O
two	O
elementary	O
functions	O
:	O
memory	B-General_Concept
elements	I-General_Concept
for	O
storing	O
information	O
,	O
and	O
combinational	O
circuits	O
that	O
transform	O
that	O
information	O
.	O
</s>
<s>
State	B-Architecture
machines	I-Architecture
,	O
like	O
counters	O
,	O
are	O
a	O
combination	O
of	O
memory	B-General_Concept
elements	I-General_Concept
and	O
combinational	O
logic	O
circuits	O
.	O
</s>
<s>
Since	O
memory	B-General_Concept
elements	I-General_Concept
are	O
standard	O
logic	O
circuits	O
they	O
are	O
selected	O
out	O
of	O
a	O
limited	O
set	O
of	O
alternative	O
circuits	O
;	O
so	O
designing	O
digital	O
functions	O
comes	O
down	O
to	O
designing	O
the	O
combinational	O
gate	O
circuits	O
and	O
interconnecting	O
them	O
.	O
</s>
<s>
The	O
below	O
example	O
shows	O
a	O
part	O
of	O
such	O
a	O
table	O
for	O
a	O
7-segment	B-General_Concept
display	I-General_Concept
driver	O
that	O
translates	O
the	O
binary	O
code	O
for	O
the	O
values	O
of	O
a	O
decimal	O
digit	O
into	O
the	O
signals	O
that	O
cause	O
the	O
respective	O
segments	O
of	O
the	O
display	O
to	O
light	O
up	O
.	O
</s>
<s>
It	O
is	O
a	O
resource	O
and	O
performance	O
efficient	O
algorithm	O
aimed	O
at	O
solving	O
the	O
heuristic	B-Algorithm
hazard-free	O
two-level	O
logic	O
minimization	O
problem	O
.	O
</s>
<s>
For	O
implementing	O
a	O
function	O
in	O
multi-level	O
logic	O
,	O
the	O
minimization	O
result	O
is	O
optimized	O
by	O
factorization	O
and	O
mapped	O
onto	O
the	O
available	O
basic	O
logic	O
cells	O
in	O
the	O
target	O
technology	O
,	O
whether	O
this	O
concerns	O
a	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
or	O
an	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
.	O
</s>
<s>
The	O
original	O
ESPRESSO	O
program	O
is	O
available	O
as	O
C	B-Language
source	O
code	O
from	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
website	O
.	O
</s>
<s>
The	O
ESPRESSO-AB	O
and	O
EQNTOTT	O
(	O
equation	O
to	O
truth	O
table	O
)	O
program	O
,	O
an	O
updated	O
version	O
of	O
ESPRESSO	O
for	O
modern	O
POSIX	O
systems	O
,	O
is	O
available	O
in	O
Debian	O
Linux	B-Application
distribution	I-Application
(	O
.deb	O
)	O
file	O
format	O
as	O
well	O
the	O
C	B-Language
source	O
code	O
.	O
</s>
<s>
A	O
Windows	B-Application
and	O
C++20	O
compatible	O
was	O
ported	O
to	O
github	B-Application
in	O
2020	O
.	O
</s>
<s>
Logic	O
Friday	O
is	O
a	O
free	O
Windows	B-Application
program	O
that	O
provides	O
a	O
graphical	O
interface	O
to	O
Espresso	O
,	O
as	O
well	O
as	O
to	O
misII	O
,	O
another	O
module	O
in	O
the	O
Berkeley	O
Octtools	O
package	O
.	O
</s>
<s>
Minilog	O
is	O
a	O
free	O
Windows	B-Application
program	O
that	O
provides	O
logic	O
minimization	O
exploiting	O
this	O
Espresso	O
algorithm	O
.	O
</s>
<s>
It	O
is	O
able	O
to	O
generate	O
a	O
two-level	O
gate	O
implementation	O
for	O
a	O
combinational	O
function	O
block	O
with	O
up	O
to	O
40	O
inputs	O
and	O
outputs	O
or	O
a	O
synchronous	B-Architecture
state	I-Architecture
machine	I-Architecture
with	O
up	O
to	O
256	O
states	O
.	O
</s>
<s>
It	O
is	O
part	O
of	O
the	O
Publicad	B-Algorithm
educational	O
design	O
package	O
.	O
</s>
