<s>
The	O
EnCore	O
microprocessor	B-Architecture
family	O
is	O
a	O
configurable	O
and	O
extendable	O
implementation	O
of	O
a	O
compact	O
32-bit	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
architecture	O
-	O
developed	O
by	O
the	O
at	O
the	O
University	O
of	O
Edinburgh	O
School	O
of	O
Informatics	O
.	O
</s>
<s>
The	O
following	O
are	O
key	O
features	O
of	O
the	O
EnCore	O
microprocessor	B-Architecture
family	O
:	O
</s>
<s>
The	O
first	O
silicon	O
implementation	O
of	O
the	O
EnCore	B-General_Concept
processor	I-General_Concept
is	O
a	O
code-named	O
Calton	O
,	O
fabricated	O
in	O
a	O
CMOS	B-Device
process	O
using	O
a	O
standard	O
.	O
</s>
<s>
130nm	O
implementation	O
of	O
EnCore	B-General_Concept
processor	I-General_Concept
in	O
baseline	O
configuration	O
extended	O
with	O
barrel	O
shifter	O
,	O
multiplier	O
,	O
and	O
a	O
full	O
set	O
of	O
32	O
general	O
purpose	O
registers	B-General_Concept
.	O
</s>
<s>
Complete	O
system-on-chip	B-Architecture
occupies	O
1mm2	O
of	O
silicon	O
at	O
75%	O
utilization	O
.	O
</s>
<s>
codenamed	O
Castle	O
,	O
fabricated	O
in	O
a	O
CMOS	B-Device
process	O
.	O
</s>
