<s>
The	O
Emotion	B-Architecture
Engine	I-Architecture
is	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
developed	O
and	O
manufactured	O
by	O
Sony	O
Computer	O
Entertainment	O
and	O
Toshiba	O
for	O
use	O
in	O
the	O
PlayStation	B-Device
2	I-Device
video	B-Device
game	I-Device
console	I-Device
.	O
</s>
<s>
It	O
was	O
also	O
used	O
in	O
early	O
PlayStation	B-Operating_System
3	I-Operating_System
models	O
sold	O
in	O
Japan	O
and	O
North	O
America	O
(	O
Model	O
Numbers	O
CECHAxx	O
&	O
CECHBxx	O
)	O
to	O
provide	O
PlayStation	B-Device
2	I-Device
game	O
support	O
.	O
</s>
<s>
Mass	O
production	O
of	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
began	O
in	O
1999	O
and	O
ended	O
in	O
late	O
2012	O
with	O
the	O
discontinuation	O
of	O
the	O
PlayStation	B-Device
2	I-Device
.	O
</s>
<s>
The	O
Emotion	B-Architecture
Engine	I-Architecture
consists	O
of	O
eight	O
separate	O
"	O
units	O
"	O
,	O
each	O
performing	O
a	O
specific	O
task	O
,	O
integrated	O
onto	O
the	O
same	O
die	O
.	O
</s>
<s>
These	O
units	O
are	O
:	O
a	O
CPU	O
core	O
,	O
two	O
Vector	B-Operating_System
Processing	I-Operating_System
Units	I-Operating_System
(	O
VPU	O
)	O
,	O
a	O
10-channel	O
DMA	B-General_Concept
unit	O
,	O
a	O
memory	B-General_Concept
controller	I-General_Concept
,	O
and	O
an	O
Image	B-General_Concept
Processing	I-General_Concept
Unit	I-General_Concept
(	O
IPU	O
)	O
.	O
</s>
<s>
The	O
second	O
VPU	O
,	O
VPU1	O
,	O
is	O
dedicated	O
to	O
geometry-transformations	O
and	O
lighting	O
and	O
operates	O
independently	O
,	O
parallel	O
to	O
the	O
CPU	O
core	O
,	O
controlled	O
by	O
microcode	B-Device
.	O
</s>
<s>
The	O
CPU	O
core	O
is	O
a	O
two-way	O
superscalar	B-General_Concept
in-order	O
RISC	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Based	O
on	O
the	O
MIPS	O
R5900	O
,	O
it	O
implements	O
the	O
MIPS-III	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
and	O
much	O
of	O
MIPS-IV	O
,	O
in	O
addition	O
to	O
a	O
custom	O
instruction	B-General_Concept
set	I-General_Concept
developed	O
by	O
Sony	O
which	O
operated	O
on	O
128-bit	O
wide	O
groups	O
of	O
either	O
32-bit	O
,	O
16-bit	O
,	O
or	O
8-bit	O
integers	O
in	O
single	B-Device
instruction	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
fashion	O
(	O
i.e.	O
</s>
<s>
Contrary	O
to	O
some	O
misconceptions	O
,	O
these	O
SIMD	B-Device
capabilities	O
did	O
not	O
amount	O
to	O
the	O
processor	O
being	O
"	O
128-bit	O
"	O
,	O
as	O
neither	O
the	O
memory	O
addresses	O
nor	O
the	O
integers	O
themselves	O
were	O
128-bit	O
,	O
only	O
the	O
shared	O
SIMD/integer	O
registers	B-General_Concept
.	O
</s>
<s>
For	O
comparison	O
,	O
128-bit	O
wide	O
registers	B-General_Concept
and	O
SIMD	B-Device
instructions	O
had	O
been	O
present	O
in	O
the	O
32-bit	O
x86	B-Operating_System
architecture	I-Operating_System
since	O
1999	O
,	O
with	O
the	O
introduction	O
of	O
SSE	B-General_Concept
.	O
</s>
<s>
However	O
the	O
internal	O
data	O
paths	O
were	O
128bit	O
wide	O
,	O
and	O
its	O
processors	O
were	O
capable	O
of	O
operating	O
on	O
4x32bit	O
quantities	O
in	O
parallel	O
in	O
single	O
registers	B-General_Concept
.	O
</s>
<s>
It	O
has	O
a	O
6	O
stage	O
long	O
integer	O
pipelines	B-General_Concept
and	O
a	O
15	O
stage	O
long	O
floating	B-Algorithm
point	I-Algorithm
pipeline	B-General_Concept
.	O
</s>
<s>
Its	O
assortment	O
of	O
registers	B-General_Concept
consists	O
of	O
32	O
128-bit	O
VLIW	O
SIMD	B-Device
registers	B-General_Concept
(	O
naming/renaming	O
)	O
,	O
one	O
64-bit	O
accumulator	O
and	O
two	O
64&	O
-bit	O
general	O
data	O
registers	B-General_Concept
,	O
8	O
16-bit	O
fix	O
function	O
registers	B-General_Concept
,	O
16	O
8-bit	O
controller	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
processor	O
also	O
has	O
two	O
64-bit	O
integer	O
ALUs	O
,	O
a	O
128bit	O
Load-Store	O
Unit	O
(	O
LSU	O
)	O
,	O
a	O
Branch	O
Execution	O
Unit	O
(	O
BXU	O
)	O
and	O
a	O
32-bit	O
VU1	O
FPU	O
coprocessor	O
(	O
which	O
acted	O
as	O
a	O
sync	O
controller	O
for	O
the	O
VPU0/VPU1	O
)	O
containing	O
a	O
MIPS	O
base	O
processor	O
core	O
with	O
32	O
64-bit	O
FP	O
registers	B-General_Concept
and	O
15	O
32-bit	O
integer	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
custom	O
instruction	B-General_Concept
set	I-General_Concept
107	O
MMI	O
(	O
Multimedia	O
Extensions	O
)	O
was	O
implemented	O
by	O
grouping	O
the	O
two	O
64-bit	O
integer	O
ALUs	O
.	O
</s>
<s>
Both	O
the	O
integer	O
and	O
floating-point	B-Algorithm
pipelines	B-General_Concept
are	O
six	O
stages	O
long	O
.	O
</s>
<s>
To	O
feed	O
the	O
execution	O
units	O
with	O
instructions	O
and	O
data	O
,	O
there	O
is	O
a	O
16KB	O
two-way	O
set	O
associative	B-General_Concept
instruction	B-General_Concept
cache	I-General_Concept
,	O
an	O
8KB	O
two-way	O
set	O
associative	B-General_Concept
non	O
blocking	O
data	B-General_Concept
cache	I-General_Concept
and	O
a	O
16KB	O
scratchpad	B-General_Concept
RAM	I-General_Concept
.	O
</s>
<s>
Both	O
the	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
are	O
virtually	O
indexed	O
and	O
physically	O
tagged	O
while	O
the	O
scratchpad	B-General_Concept
RAM	I-General_Concept
exists	O
in	O
a	O
separate	O
memory	O
space	O
.	O
</s>
<s>
A	O
combined	O
48	O
double	O
entry	O
instruction	O
and	O
data	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
is	O
provided	O
for	O
translating	O
virtual	B-General_Concept
addresses	I-General_Concept
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
is	O
achieved	O
by	O
a	O
64-entry	O
branch	O
target	O
address	O
cache	O
and	O
a	O
branch	O
history	O
table	O
that	O
is	O
integrated	O
into	O
the	O
instruction	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
branch	O
mispredict	O
penalty	O
is	O
three	O
cycles	O
due	O
to	O
the	O
short	O
six	O
stage	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
majority	O
of	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
's	O
floating	B-Algorithm
point	I-Algorithm
performance	O
is	O
provided	O
by	O
two	O
vector	B-Operating_System
processing	I-Operating_System
units	I-Operating_System
(	O
VPU	O
)	O
,	O
designated	O
VPU0	O
and	O
VPU1	O
.	O
</s>
<s>
These	O
were	O
essentially	O
DSPs	O
tailored	O
for	O
3D	O
math	O
,	O
and	O
the	O
forerunner	O
to	O
hardware	O
vertex	O
shader	O
pipelines	B-General_Concept
.	O
</s>
<s>
Each	O
VPU	O
features	O
32128-bit	O
vector	O
SIMD	B-Device
registers	B-General_Concept
(	O
holding	O
4D	O
vector	O
data	O
)	O
,	O
1616-bit	O
fixed-point	O
registers	B-General_Concept
,	O
four	O
floating	B-Algorithm
point	I-Algorithm
multiply-accumulate	O
(	O
FMAC	O
)	O
units	O
,	O
a	O
floating	B-Algorithm
point	I-Algorithm
divide	O
(	O
FDIV	O
)	O
unit	O
and	O
a	O
local	B-General_Concept
data	I-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
To	O
achieve	O
high	O
bandwidth	O
,	O
the	O
VPU	O
's	O
data	O
memory	O
is	O
connected	O
directly	O
to	O
the	O
GIF	O
,	O
and	O
both	O
of	O
the	O
data	O
memories	O
can	O
be	O
read	O
directly	O
by	O
the	O
DMA	B-General_Concept
unit	O
.	O
</s>
<s>
A	O
single	O
vector	O
instruction	O
consists	O
of	O
four	O
32-bit	O
single-precision	O
floating-point	B-Algorithm
values	O
which	O
are	O
distributed	O
to	O
the	O
four	O
single-precision	O
(	O
32-bit	O
)	O
FMAC	O
units	O
for	O
processing	O
.	O
</s>
<s>
This	O
scheme	O
is	O
similar	O
to	O
the	O
SSEx	B-General_Concept
extensions	O
by	O
Intel	O
.	O
</s>
<s>
The	O
FMAC	O
units	O
take	O
four	O
cycles	O
to	O
execute	O
one	O
instruction	O
,	O
but	O
as	O
the	O
units	O
have	O
a	O
six-stage	O
pipeline	B-General_Concept
,	O
they	O
have	O
a	O
throughput	O
of	O
one	O
instruction	O
per	O
cycle	O
.	O
</s>
<s>
The	O
FDIV	O
unit	O
has	O
a	O
nine-stage	O
pipeline	B-General_Concept
and	O
can	O
execute	O
one	O
instruction	O
every	O
seven	O
cycles	O
.	O
</s>
<s>
The	O
IPU	O
allowed	O
MPEG-2	B-Algorithm
compressed	O
image	O
decoding	O
,	O
allowing	O
playback	O
of	O
DVDs	O
and	O
game	O
FMV	B-Application
.	O
</s>
<s>
The	O
memory	O
management	O
unit	O
,	O
RDRAM	O
controller	O
and	O
DMA	B-General_Concept
controller	I-General_Concept
handle	O
memory	O
access	O
within	O
the	O
system	O
.	O
</s>
<s>
Communications	O
between	O
the	O
MIPS	O
core	O
,	O
the	O
two	O
VPUs	O
,	O
GIF	O
,	O
memory	B-General_Concept
controller	I-General_Concept
and	O
other	O
units	O
is	O
handled	O
by	O
a	O
128-bit	O
wide	O
internal	O
data	O
bus	O
running	O
at	O
half	O
the	O
clock	O
frequency	O
of	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
but	O
,	O
to	O
offer	O
greater	O
bandwidth	O
,	O
there	O
is	O
also	O
a	O
128-bit	O
dedicated	O
path	O
between	O
the	O
CPU	O
and	O
VPU0	O
and	O
a	O
128-bit	O
dedicated	O
path	O
between	O
VPU1	O
and	O
GIF	O
.	O
</s>
<s>
Communication	O
between	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
and	O
RAM	B-Architecture
occurs	O
through	O
two	O
channels	O
of	O
DRDRAM	O
(	O
Direct	O
Rambus	O
Dynamic	O
Random	B-Architecture
Access	I-Architecture
Memory	I-Architecture
)	O
and	O
the	O
memory	B-General_Concept
controller	I-General_Concept
,	O
which	O
interfaces	O
to	O
the	O
internal	O
data	O
bus	O
.	O
</s>
<s>
Because	O
of	O
this	O
,	O
the	O
memory	B-General_Concept
controller	I-General_Concept
buffers	O
data	O
sent	O
from	O
the	O
DRDRAM	O
channels	O
so	O
the	O
extra	O
bandwidth	O
can	O
be	O
utilised	O
by	O
the	O
CPU	O
.	O
</s>
<s>
The	O
Emotion	B-Architecture
Engine	I-Architecture
interfaces	O
directly	O
to	O
the	O
Graphics	O
Synthesizer	O
via	O
the	O
GIF	O
with	O
a	O
dedicated	O
64-bit	O
,	O
150MHz	O
bus	O
that	O
has	O
a	O
maximum	O
theoretical	O
bandwidth	O
of	O
1.2GB/s	O
.	O
</s>
<s>
To	O
provide	O
communications	O
between	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
and	O
the	O
Input	O
Output	O
Processor	O
(	O
IOP	O
)	O
,	O
the	O
input	O
output	O
interface	O
interfaces	O
a	O
32-bit	O
wide	O
,	O
37.5MHz	O
input	O
output	O
bus	O
with	O
a	O
maximum	O
theoretical	O
bandwidth	O
of	O
150MB/s	O
to	O
the	O
internal	O
data	O
bus	O
.	O
</s>
<s>
The	O
Emotion	B-Architecture
Engine	I-Architecture
contained	O
13.5	O
million	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
transistors	O
,	O
on	O
an	O
integrated	O
circuit	O
(	O
IC	O
)	O
die	O
measuring	O
240mm2	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
Sony	O
and	O
Toshiba	O
in	O
a	O
0.25	O
µm	O
(	O
0.18	O
µm	O
effective	O
LG	O
)	O
complementary	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
CMOS	O
)	O
process	O
with	O
four	O
levels	O
of	O
interconnect	O
.	O
</s>
<s>
The	O
Emotion	B-Architecture
Engine	I-Architecture
was	O
packaged	O
in	O
a	O
540-contact	O
plastic	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PBGA	B-Algorithm
)	O
.	O
</s>
<s>
The	O
primary	O
use	O
of	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
was	O
to	O
serve	O
as	O
the	O
PlayStation	B-Device
2	I-Device
's	O
CPU	O
.	O
</s>
<s>
The	O
first	O
SKUs	O
of	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
also	O
featured	O
an	O
Emotion	B-Architecture
Engine	I-Architecture
on	O
the	O
motherboard	O
to	O
achieve	O
backwards	O
compatibility	O
with	O
PlayStation	B-Device
2	I-Device
games	O
.	O
</s>
<s>
However	O
,	O
the	O
second	O
revision	O
of	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
lacked	O
a	O
physical	O
Emotion	B-Architecture
Engine	I-Architecture
in	O
order	O
to	O
lower	O
costs	O
,	O
performing	O
all	O
of	O
its	O
functions	O
using	O
software	O
emulation	O
performed	O
by	O
the	O
Cell	O
Broadband	O
Processor	O
,	O
coupled	O
with	O
a	O
hardware	O
Graphics	O
Synthesizer	O
still	O
present	O
to	O
achieve	O
PlayStation	B-Device
2	I-Device
backwards	O
compatibility	O
.	O
</s>
<s>
In	O
all	O
subsequent	O
revisions	O
,	O
the	O
Graphics	O
Synthesizer	O
was	O
removed	O
;	O
however	O
,	O
a	O
PlayStation	B-Device
2	I-Device
software	O
emulator	O
is	O
available	O
in	O
later	O
system	O
software	O
revisions	O
for	O
use	O
with	O
Sony	O
's	O
PS2	B-Device
Classics	O
titles	O
available	O
for	O
purchase	O
on	O
the	O
Sony	O
Entertainment	O
Network	O
.	O
</s>
