<s>
In	O
computer	B-General_Concept
science	I-General_Concept
,	O
an	O
instruction	O
set	O
architecture	O
(	O
ISA	O
)	O
,	O
also	O
called	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
is	O
an	O
abstract	O
model	O
of	O
a	O
computer	O
.	O
</s>
<s>
A	O
device	O
that	O
executes	O
instructions	B-Language
described	O
by	O
that	O
ISA	O
,	O
such	O
as	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
,	O
is	O
called	O
an	O
implementation	O
.	O
</s>
<s>
In	O
general	O
,	O
an	O
ISA	O
defines	O
the	O
supported	O
instructions	B-Language
,	O
data	O
types	O
,	O
registers	B-General_Concept
,	O
the	O
hardware	O
support	O
for	O
managing	O
main	B-Architecture
memory	I-Architecture
,	O
fundamental	O
features	O
(	O
such	O
as	O
the	O
memory	B-General_Concept
consistency	I-General_Concept
,	O
addressing	B-Language
modes	I-Language
,	O
virtual	B-Architecture
memory	I-Architecture
)	O
,	O
and	O
the	O
input/output	B-General_Concept
model	O
of	O
a	O
family	O
of	O
implementations	O
of	O
the	O
ISA	O
.	O
</s>
<s>
An	O
ISA	O
specifies	O
the	O
behavior	O
of	O
machine	B-Language
code	I-Language
running	O
on	O
implementations	O
of	O
that	O
ISA	O
in	O
a	O
fashion	O
that	O
does	O
not	O
depend	O
on	O
the	O
characteristics	O
of	O
that	O
implementation	O
,	O
providing	O
binary	B-General_Concept
compatibility	I-General_Concept
between	O
implementations	O
.	O
</s>
<s>
This	O
enables	O
multiple	O
implementations	O
of	O
an	O
ISA	O
that	O
differ	O
in	O
characteristics	O
such	O
as	O
performance	O
,	O
physical	O
size	O
,	O
and	O
monetary	O
cost	O
(	O
among	O
other	O
things	O
)	O
,	O
but	O
that	O
are	O
capable	O
of	O
running	O
the	O
same	O
machine	B-Language
code	I-Language
,	O
so	O
that	O
a	O
lower-performance	O
,	O
lower-cost	O
machine	O
can	O
be	O
replaced	O
with	O
a	O
higher-cost	O
,	O
higher-performance	O
machine	O
without	O
having	O
to	O
replace	O
software	O
.	O
</s>
<s>
It	O
also	O
enables	O
the	O
evolution	O
of	O
the	O
microarchitectures	B-General_Concept
of	O
the	O
implementations	O
of	O
that	O
ISA	O
,	O
so	O
that	O
a	O
newer	O
,	O
higher-performance	O
implementation	O
of	O
an	O
ISA	O
can	O
run	O
software	O
that	O
runs	O
on	O
previous	O
generations	O
of	O
implementations	O
.	O
</s>
<s>
If	O
an	O
operating	B-General_Concept
system	I-General_Concept
maintains	O
a	O
standard	O
and	O
compatible	O
application	B-Operating_System
binary	I-Operating_System
interface	I-Operating_System
(	O
ABI	O
)	O
for	O
a	O
particular	O
ISA	O
,	O
machine	B-Language
code	I-Language
will	O
run	O
on	O
future	O
implementations	O
of	O
that	O
ISA	O
and	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
However	O
,	O
if	O
an	O
ISA	O
supports	O
running	O
multiple	O
operating	B-General_Concept
systems	I-General_Concept
,	O
it	O
does	O
not	O
guarantee	O
that	O
machine	B-Language
code	I-Language
for	O
one	O
operating	B-General_Concept
system	I-General_Concept
will	O
run	O
on	O
another	O
operating	B-General_Concept
system	I-General_Concept
,	O
unless	O
the	O
first	O
operating	B-General_Concept
system	I-General_Concept
supports	O
running	O
machine	B-Language
code	I-Language
built	O
for	O
the	O
other	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
An	O
ISA	O
can	O
be	O
extended	O
by	O
adding	O
instructions	B-Language
or	O
other	O
capabilities	O
,	O
or	O
adding	O
support	O
for	O
larger	O
addresses	O
and	O
data	O
values	O
;	O
an	O
implementation	O
of	O
the	O
extended	O
ISA	O
will	O
still	O
be	O
able	O
to	O
execute	O
machine	B-Language
code	I-Language
for	O
versions	O
of	O
the	O
ISA	O
without	O
those	O
extensions	O
.	O
</s>
<s>
Machine	B-Language
code	I-Language
using	O
those	O
extensions	O
will	O
only	O
run	O
on	O
implementations	O
that	O
support	O
those	O
extensions	O
.	O
</s>
<s>
The	O
binary	B-General_Concept
compatibility	I-General_Concept
that	O
they	O
provide	O
makes	O
ISAs	O
one	O
of	O
the	O
most	O
fundamental	O
abstractions	O
in	O
computing	O
.	O
</s>
<s>
An	O
instruction	O
set	O
architecture	O
is	O
distinguished	O
from	O
a	O
microarchitecture	B-General_Concept
,	O
which	O
is	O
the	O
set	O
of	O
processor	B-General_Concept
design	I-General_Concept
techniques	O
used	O
,	O
in	O
a	O
particular	O
processor	O
,	O
to	O
implement	O
the	O
instruction	O
set	O
.	O
</s>
<s>
Processors	O
with	O
different	O
microarchitectures	B-General_Concept
can	O
share	O
a	O
common	O
instruction	O
set	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
and	O
the	O
AMD	B-Architecture
Athlon	I-Architecture
implement	O
nearly	O
identical	O
versions	O
of	O
the	O
x86	B-Device
instruction	I-Device
set	I-Device
,	O
but	O
they	O
have	O
radically	O
different	O
internal	O
designs	O
.	O
</s>
<s>
The	O
concept	O
of	O
an	O
architecture	O
,	O
distinct	O
from	O
the	O
design	O
of	O
a	O
specific	O
machine	O
,	O
was	O
developed	O
by	O
Fred	O
Brooks	O
at	O
IBM	O
during	O
the	O
design	O
phase	O
of	O
System/360	B-Application
.	O
</s>
<s>
Some	O
virtual	B-Architecture
machines	I-Architecture
that	O
support	O
bytecode	O
as	O
their	O
ISA	O
such	O
as	O
Smalltalk	B-Application
,	O
the	O
Java	B-Language
virtual	I-Language
machine	I-Language
,	O
and	O
Microsoft	O
's	O
Common	O
Language	O
Runtime	O
,	O
implement	O
this	O
by	O
translating	O
the	O
bytecode	O
for	O
commonly	O
used	O
code	O
paths	O
into	O
native	O
machine	B-Language
code	I-Language
.	O
</s>
<s>
In	O
addition	O
,	O
these	O
virtual	B-Architecture
machines	I-Architecture
execute	O
less	O
frequently	O
used	O
code	O
paths	O
by	O
interpretation	O
(	O
see	O
:	O
Just-in-time	O
compilation	B-Language
)	O
.	O
</s>
<s>
Transmeta	O
implemented	O
the	O
x86	B-Device
instruction	I-Device
set	I-Device
atop	O
VLIW	B-General_Concept
processors	O
in	O
this	O
fashion	O
.	O
</s>
<s>
A	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	B-Architecture
)	O
has	O
many	O
specialized	O
instructions	B-Language
,	O
some	O
of	O
which	O
may	O
only	O
be	O
rarely	O
used	O
in	O
practical	O
programs	O
.	O
</s>
<s>
A	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
simplifies	O
the	O
processor	O
by	O
efficiently	O
implementing	O
only	O
the	O
instructions	B-Language
that	O
are	O
frequently	O
used	O
in	O
programs	O
,	O
while	O
the	O
less	O
common	O
operations	O
are	O
implemented	O
as	O
subroutines	O
,	O
having	O
their	O
resulting	O
additional	O
processor	O
execution	O
time	O
offset	O
by	O
infrequent	O
use	O
.	O
</s>
<s>
Other	O
types	O
include	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
architectures	O
,	O
and	O
the	O
closely	O
related	O
explicitly	B-General_Concept
parallel	I-General_Concept
instruction	I-General_Concept
computing	I-General_Concept
(	O
EPIC	O
)	O
architectures	O
.	O
</s>
<s>
These	O
architectures	O
seek	O
to	O
exploit	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
with	O
less	O
hardware	O
than	O
RISC	B-Architecture
and	O
CISC	B-Architecture
by	O
making	O
the	O
compiler	B-Language
responsible	O
for	O
instruction	O
issue	O
and	O
scheduling	O
.	O
</s>
<s>
Architectures	O
with	O
even	O
less	O
complexity	O
have	O
been	O
studied	O
,	O
such	O
as	O
the	O
minimal	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
computer	I-General_Concept
(	O
MISC	O
)	O
and	O
one-instruction	B-Application
set	I-Application
computer	I-Application
(	O
OISC	O
)	O
.	O
</s>
<s>
Machine	B-Language
language	I-Language
is	O
built	O
up	O
from	O
discrete	O
statements	O
or	O
instructions	B-Language
.	O
</s>
<s>
opcode	B-Language
(	O
the	O
instruction	O
to	O
be	O
performed	O
)	O
e.g.	O
</s>
<s>
More	O
complex	O
operations	O
are	O
built	O
up	O
by	O
combining	O
these	O
simple	O
instructions	B-Language
,	O
which	O
are	O
executed	O
sequentially	O
,	O
or	O
as	O
otherwise	O
directed	O
by	O
control	O
flow	O
instructions	B-Language
.	O
</s>
<s>
Set	O
a	O
register	B-General_Concept
to	O
a	O
fixed	O
constant	O
value	O
.	O
</s>
<s>
Copy	O
data	O
from	O
a	O
memory	O
location	O
or	O
a	O
register	B-General_Concept
to	O
a	O
memory	O
location	O
or	O
a	O
register	B-General_Concept
(	O
a	O
machine	B-Language
instruction	I-Language
is	O
often	O
called	O
move	O
;	O
however	O
,	O
the	O
term	O
is	O
misleading	O
)	O
.	O
</s>
<s>
They	O
are	O
used	O
to	O
store	O
the	O
contents	O
of	O
a	O
register	B-General_Concept
,	O
the	O
contents	O
of	O
another	O
memory	O
location	O
or	O
the	O
result	O
of	O
a	O
computation	O
,	O
or	O
to	O
retrieve	O
stored	O
data	O
to	O
perform	O
a	O
computation	O
on	O
it	O
later	O
.	O
</s>
<s>
They	O
are	O
often	O
called	O
load	B-Architecture
and	I-Architecture
store	I-Architecture
operations	O
.	O
</s>
<s>
Add	O
,	O
subtract	O
,	O
multiply	O
,	O
or	O
divide	O
the	O
values	O
of	O
two	O
registers	B-General_Concept
,	O
placing	O
the	O
result	O
in	O
a	O
register	B-General_Concept
,	O
possibly	O
setting	O
one	O
or	O
more	O
condition	O
codes	O
in	O
a	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
Perform	O
bitwise	O
operations	O
,	O
e.g.	O
,	O
taking	O
the	O
conjunction	O
and	O
disjunction	O
of	O
corresponding	O
bits	O
in	O
a	O
pair	O
of	O
registers	B-General_Concept
,	O
taking	O
the	O
negation	O
of	O
each	O
bit	O
in	O
a	O
register	B-General_Concept
.	O
</s>
<s>
Compare	O
two	O
values	O
in	O
registers	B-General_Concept
(	O
for	O
example	O
,	O
to	O
see	O
if	O
one	O
is	O
less	O
,	O
or	O
if	O
they	O
are	O
equal	O
)	O
.	O
</s>
<s>
s	O
for	O
arithmetic	O
on	O
floating-point	B-Algorithm
numbers	I-Algorithm
.	O
</s>
<s>
Branch	B-General_Concept
to	O
another	O
location	O
in	O
the	O
program	O
and	O
execute	O
instructions	B-Language
there	O
.	O
</s>
<s>
Conditionally	B-General_Concept
branch	I-General_Concept
to	O
another	O
location	O
if	O
a	O
certain	O
condition	O
holds	O
.	O
</s>
<s>
Indirectly	B-Language
branch	I-Language
to	O
another	O
location	O
.	O
</s>
<s>
Load/store	O
data	O
to	O
and	O
from	O
a	O
coprocessor	O
or	O
exchanging	O
with	O
CPU	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
Processors	O
may	O
include	O
"	O
complex	O
"	O
instructions	B-Language
in	O
their	O
instruction	O
set	O
.	O
</s>
<s>
A	O
single	O
"	O
complex	O
"	O
instruction	O
does	O
something	O
that	O
may	O
take	O
many	O
instructions	B-Language
on	O
other	O
computers	O
.	O
</s>
<s>
Such	O
instructions	B-Language
are	O
typified	O
by	O
instructions	B-Language
that	O
take	O
multiple	O
steps	O
,	O
control	O
multiple	O
functional	O
units	O
,	O
or	O
otherwise	O
appear	O
on	O
a	O
larger	O
scale	O
than	O
the	O
bulk	O
of	O
simple	O
instructions	B-Language
implemented	O
by	O
the	O
given	O
processor	O
.	O
</s>
<s>
Some	O
examples	O
of	O
"	O
complex	O
"	O
instructions	B-Language
include	O
:	O
</s>
<s>
complicated	O
integer	O
and	O
floating-point	B-Algorithm
arithmetic	I-Algorithm
(	O
e.g.	O
</s>
<s>
Complex	O
instructions	B-Language
are	O
more	O
common	O
in	O
CISC	B-Architecture
instruction	O
sets	O
than	O
in	O
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
,	O
but	O
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
may	O
include	O
them	O
as	O
well	O
.	O
</s>
<s>
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
generally	O
do	O
not	O
include	O
ALU	B-General_Concept
operations	O
with	O
memory	O
operands	O
,	O
or	O
instructions	B-Language
to	O
move	O
large	O
blocks	O
of	O
memory	O
,	O
but	O
most	O
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
include	O
SIMD	B-Device
or	O
vector	B-Operating_System
instructions	B-Language
that	O
perform	O
the	O
same	O
arithmetic	O
operation	O
on	O
multiple	O
pieces	O
of	O
data	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
SIMD	B-Device
instructions	B-Language
have	O
the	O
ability	O
of	O
manipulating	O
large	O
vectors	O
and	O
matrices	O
in	O
minimal	O
time	O
.	O
</s>
<s>
SIMD	B-Device
instructions	B-Language
allow	O
easy	O
parallelization	B-Operating_System
of	O
algorithms	O
commonly	O
involved	O
in	O
sound	O
,	O
image	O
,	O
and	O
video	O
processing	O
.	O
</s>
<s>
Various	O
SIMD	B-Device
implementations	O
have	O
been	O
brought	O
to	O
market	O
under	O
trade	O
names	O
such	O
as	O
MMX	B-Architecture
,	O
3DNow	O
!,	O
and	O
AltiVec	B-General_Concept
.	O
</s>
<s>
On	O
traditional	O
architectures	O
,	O
an	O
instruction	O
includes	O
an	O
opcode	B-Language
that	O
specifies	O
the	O
operation	O
to	O
perform	O
,	O
such	O
as	O
add	O
contents	O
of	O
memory	O
to	O
register	B-General_Concept
—	O
and	O
zero	O
or	O
more	O
operand	O
specifiers	O
,	O
which	O
may	O
specify	O
registers	B-General_Concept
,	O
memory	O
locations	O
,	O
or	O
literal	O
data	O
.	O
</s>
<s>
The	O
operand	O
specifiers	O
may	O
have	O
addressing	B-Language
modes	I-Language
determining	O
their	O
meaning	O
or	O
may	O
be	O
in	O
fixed	O
fields	O
.	O
</s>
<s>
In	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
architectures	O
,	O
which	O
include	O
many	O
microcode	B-Device
architectures	O
,	O
multiple	O
simultaneous	O
opcodes	B-Language
and	O
operands	O
are	O
specified	O
in	O
a	O
single	O
instruction	O
.	O
</s>
<s>
Some	O
exotic	O
instruction	O
sets	O
do	O
not	O
have	O
an	O
opcode	B-Language
field	O
,	O
such	O
as	O
transport	B-General_Concept
triggered	I-General_Concept
architectures	I-General_Concept
(	O
TTA	O
)	O
,	O
only	O
operand(s )	O
.	O
</s>
<s>
Most	O
stack	B-Application
machines	I-Application
have	O
"	O
0-operand	O
"	O
instruction	O
sets	O
in	O
which	O
arithmetic	O
and	O
logical	O
operations	O
lack	O
any	O
operand	O
specifier	O
fields	O
;	O
only	O
instructions	B-Language
that	O
push	O
operands	O
onto	O
the	O
evaluation	O
stack	B-Application
or	O
that	O
pop	O
operands	O
from	O
the	O
stack	B-Application
into	O
variables	O
have	O
operand	O
specifiers	O
.	O
</s>
<s>
The	O
instruction	O
set	O
carries	O
out	O
most	O
ALU	B-General_Concept
actions	O
with	O
postfix	O
(	O
reverse	O
Polish	O
notation	O
)	O
operations	O
that	O
work	O
only	O
on	O
the	O
expression	O
stack	B-Application
,	O
not	O
on	O
data	O
registers	B-General_Concept
or	O
arbitrary	O
main	B-Architecture
memory	I-Architecture
cells	O
.	O
</s>
<s>
This	O
can	O
be	O
very	O
convenient	O
for	O
compiling	B-Language
high-level	B-Language
languages	I-Language
,	O
because	O
most	O
arithmetic	O
expressions	O
can	O
be	O
easily	O
translated	O
into	O
postfix	O
notation	O
.	O
</s>
<s>
Conditional	O
instructions	B-Language
often	O
have	O
a	O
predicate	O
field	O
—	O
a	O
few	O
bits	O
that	O
encode	O
the	O
specific	O
condition	O
to	O
cause	O
an	O
operation	O
to	O
be	O
performed	O
rather	O
than	O
not	O
performed	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
instruction	O
will	O
transfer	O
control	O
if	O
the	O
condition	O
is	O
true	O
,	O
so	O
that	O
execution	O
proceeds	O
to	O
a	O
different	O
part	O
of	O
the	O
program	O
,	O
and	O
not	O
transfer	O
control	O
if	O
the	O
condition	O
is	O
false	O
,	O
so	O
that	O
execution	O
continues	O
sequentially	O
.	O
</s>
<s>
Some	O
instruction	O
sets	O
also	O
have	O
conditional	B-General_Concept
moves	I-General_Concept
,	O
so	O
that	O
the	O
move	O
will	O
be	O
executed	O
,	O
and	O
the	O
data	O
stored	O
in	O
the	O
target	O
location	O
,	O
if	O
the	O
condition	O
is	O
true	O
,	O
and	O
not	O
executed	O
,	O
and	O
the	O
target	O
location	O
not	O
modified	O
,	O
if	O
the	O
condition	O
is	O
false	O
.	O
</s>
<s>
Similarly	O
,	O
IBM	B-Device
z/Architecture	I-Device
has	O
a	O
conditional	O
store	O
instruction	O
.	O
</s>
<s>
A	O
few	O
instruction	O
sets	O
include	O
a	O
predicate	O
field	O
in	O
every	O
instruction	O
;	O
this	O
is	O
called	O
branch	B-General_Concept
predication	I-General_Concept
.	O
</s>
<s>
Instruction	O
sets	O
may	O
be	O
categorized	O
by	O
the	O
maximum	O
number	O
of	O
operands	O
explicitly	O
specified	O
in	O
instructions	B-Language
.	O
</s>
<s>
(	O
In	O
the	O
examples	O
that	O
follow	O
,	O
a	O
,	O
b	O
,	O
and	O
c	O
are	O
(	O
direct	O
or	O
calculated	O
)	O
addresses	O
referring	O
to	O
memory	O
cells	O
,	O
while	O
reg1	O
and	O
so	O
on	O
refer	O
to	O
machine	O
registers	B-General_Concept
.	O
)	O
</s>
<s>
0-operand	O
(	O
zero-address	O
machines	O
)	O
,	O
so	O
called	O
stack	B-Application
machines	I-Application
:	O
All	O
arithmetic	O
operations	O
take	O
place	O
using	O
the	O
top	O
one	O
or	O
two	O
positions	O
on	O
the	O
stack	B-Application
:	O
push	O
a	O
,	O
push	O
b	O
,	O
add	O
,	O
pop	O
c	O
.	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
four	O
instructions	B-Language
.	O
</s>
<s>
For	O
stack	B-Application
machines	I-Application
,	O
the	O
terms	O
"	O
0-operand	O
"	O
and	O
"	O
zero-address	O
"	O
apply	O
to	O
arithmetic	O
instructions	B-Language
,	O
but	O
not	O
to	O
all	O
instructions	B-Language
,	O
as	O
1-operand	O
push	B-Application
and	I-Application
pop	I-Application
instructions	B-Language
are	O
used	O
to	O
access	O
memory	O
.	O
</s>
<s>
1-operand	O
(	O
one-address	O
machines	O
)	O
,	O
so	O
called	O
accumulator	B-General_Concept
machines	I-General_Concept
,	O
include	O
early	O
computers	O
and	O
many	O
small	O
microcontrollers	B-Architecture
:	O
most	O
instructions	B-Language
specify	O
a	O
single	O
right	O
operand	O
(	O
that	O
is	O
,	O
constant	O
,	O
a	O
register	B-General_Concept
,	O
or	O
a	O
memory	O
location	O
)	O
,	O
with	O
the	O
implicit	O
accumulator	B-General_Concept
as	O
the	O
left	O
operand	O
(	O
and	O
the	O
destination	O
if	O
there	O
is	O
one	O
)	O
:	O
load	O
a	O
,	O
add	O
b	O
,	O
store	O
c	O
.	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
three	O
instructions	B-Language
.	O
</s>
<s>
2-operand	O
—	O
many	O
CISC	B-Architecture
and	O
RISC	B-Architecture
machines	O
fall	O
under	O
this	O
category	O
:	O
</s>
<s>
CISC	B-Architecture
—	O
move	O
A	O
to	O
C	O
;	O
then	O
add	O
B	O
to	O
C	O
.	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
two	O
instructions	B-Language
.	O
</s>
<s>
CISC	B-Architecture
—	O
Often	O
machines	O
are	O
per	O
instruction	O
:	O
load	O
a	O
,	O
reg1	O
;	O
add	O
b	O
,	O
reg1	O
;	O
store	O
reg1	O
,	O
c	O
;	O
This	O
requires	O
a	O
load/store	O
pair	O
for	O
any	O
memory	O
movement	O
regardless	O
of	O
whether	O
the	O
add	O
result	O
is	O
an	O
augmentation	O
stored	O
to	O
a	O
different	O
place	O
,	O
as	O
in	O
C	O
=	O
A+B	O
,	O
or	O
the	O
same	O
memory	O
location	O
:	O
A	O
=	O
A+B	O
.	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
three	O
instructions	B-Language
.	O
</s>
<s>
RISC	B-Architecture
—	O
Requiring	O
explicit	O
memory	O
loads	O
,	O
the	O
instructions	B-Language
would	O
be	O
:	O
load	O
a	O
,	O
reg1	O
;	O
load	O
b	O
,	O
reg2	O
;	O
add	O
reg1	O
,	O
reg2	O
;	O
store	O
reg2	O
,	O
c	O
.	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
four	O
instructions	B-Language
.	O
</s>
<s>
CISC	B-Architecture
—	O
Or	O
,	O
on	O
machines	O
limited	O
to	O
two	O
memory	O
operands	O
per	O
instruction	O
,	O
move	O
a	O
,	O
reg1	O
;	O
add	O
reg1	O
,	O
b	O
,	O
c	O
;	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
two	O
instructions	B-Language
.	O
</s>
<s>
RISC	B-Architecture
—	O
arithmetic	O
instructions	B-Language
use	O
registers	B-General_Concept
only	O
,	O
so	O
explicit	O
2-operand	O
load/store	O
instructions	B-Language
are	O
needed	O
:	O
load	O
a	O
,	O
reg1	O
;	O
load	O
b	O
,	O
reg2	O
;	O
add	O
reg1+	O
reg2->reg3	O
;	O
store	O
reg3	O
,	O
c	O
;	O
</s>
<s>
C	O
=	O
A+B	O
needs	O
four	O
instructions	B-Language
.	O
</s>
<s>
Unlike	O
2-operand	O
or	O
1-operand	O
,	O
this	O
leaves	O
all	O
three	O
values	O
a	O
,	O
b	O
,	O
and	O
c	O
in	O
registers	B-General_Concept
available	O
for	O
further	O
reuse	O
.	O
</s>
<s>
more	O
operands	O
—	O
some	O
CISC	B-Architecture
machines	O
permit	O
a	O
variety	O
of	O
addressing	B-Language
modes	I-Language
that	O
allow	O
more	O
than	O
3	O
operands	O
(	O
registers	B-General_Concept
or	O
memory	O
accesses	O
)	O
,	O
such	O
as	O
the	O
VAX	B-Device
"	O
POLY	O
"	O
polynomial	O
evaluation	O
instruction	O
.	O
</s>
<s>
Due	O
to	O
the	O
large	O
number	O
of	O
bits	O
needed	O
to	O
encode	O
the	O
three	O
registers	B-General_Concept
of	O
a	O
3-operand	O
instruction	O
,	O
RISC	B-Architecture
architectures	I-Architecture
that	O
have	O
16-bit	O
instructions	B-Language
are	O
invariably	O
2-operand	O
designs	O
,	O
such	O
as	O
the	O
Atmel	O
AVR	O
,	O
TI	B-Architecture
MSP430	I-Architecture
,	O
and	O
some	O
versions	O
of	O
ARM	B-Architecture
Thumb	O
.	O
</s>
<s>
RISC	B-Architecture
architectures	I-Architecture
that	O
have	O
32-bit	O
instructions	B-Language
are	O
usually	O
3-operand	O
designs	O
,	O
such	O
as	O
the	O
ARM	B-Architecture
,	O
AVR32	B-Device
,	O
MIPS	B-Device
,	O
Power	B-Architecture
ISA	I-Architecture
,	O
and	O
SPARC	B-Architecture
architectures	O
.	O
</s>
<s>
Each	O
instruction	O
specifies	O
some	O
number	O
of	O
operands	O
(	O
registers	B-General_Concept
,	O
memory	O
locations	O
,	O
or	O
immediate	O
values	O
)	O
explicitly	O
.	O
</s>
<s>
Some	O
instructions	B-Language
give	O
one	O
or	O
both	O
operands	O
implicitly	O
,	O
such	O
as	O
by	O
being	O
stored	O
on	O
top	O
of	O
the	O
stack	B-Application
or	O
in	O
an	O
implicit	O
register	B-General_Concept
.	O
</s>
<s>
Operands	O
are	O
either	O
encoded	O
in	O
the	O
"	O
opcode	B-Language
"	O
representation	O
of	O
the	O
instruction	O
,	O
or	O
else	O
are	O
given	O
as	O
values	O
or	O
addresses	O
following	O
the	O
opcode	B-Language
.	O
</s>
<s>
Register	B-General_Concept
pressure	O
measures	O
the	O
availability	O
of	O
free	O
registers	B-General_Concept
at	O
any	O
point	O
in	O
time	O
during	O
the	O
program	O
execution	O
.	O
</s>
<s>
Register	B-General_Concept
pressure	O
is	O
high	O
when	O
a	O
large	O
number	O
of	O
the	O
available	O
registers	B-General_Concept
are	O
in	O
use	O
;	O
thus	O
,	O
the	O
higher	O
the	O
register	B-General_Concept
pressure	O
,	O
the	O
more	O
often	O
the	O
register	B-General_Concept
contents	O
must	O
be	O
spilled	O
into	O
memory	O
.	O
</s>
<s>
Increasing	O
the	O
number	O
of	O
registers	B-General_Concept
in	O
an	O
architecture	O
decreases	O
register	B-General_Concept
pressure	O
but	O
increases	O
the	O
cost	O
.	O
</s>
<s>
While	O
embedded	O
instruction	O
sets	O
such	O
as	O
Thumb	O
suffer	O
from	O
extremely	O
high	O
register	B-General_Concept
pressure	O
because	O
they	O
have	O
small	O
register	B-General_Concept
sets	O
,	O
general-purpose	O
RISC	B-Architecture
ISAs	O
like	O
MIPS	B-Device
and	O
Alpha	B-Device
enjoy	O
low	O
register	B-General_Concept
pressure	O
.	O
</s>
<s>
CISC	B-Architecture
ISAs	O
like	O
x86-64	O
offer	O
low	O
register	B-General_Concept
pressure	O
despite	O
having	O
smaller	O
register	B-General_Concept
sets	O
.	O
</s>
<s>
This	O
is	O
due	O
to	O
the	O
many	O
addressing	B-Language
modes	I-Language
and	O
optimizations	O
(	O
such	O
as	O
sub-register	O
addressing	O
,	O
memory	O
operands	O
in	O
ALU	B-General_Concept
instructions	B-Language
,	O
absolute	O
addressing	O
,	O
PC-relative	O
addressing	O
,	O
and	O
register-to-register	O
spills	O
)	O
that	O
CISC	B-Architecture
ISAs	O
offer	O
.	O
</s>
<s>
The	O
size	O
or	O
length	O
of	O
an	O
instruction	O
varies	O
widely	O
,	O
from	O
as	O
little	O
as	O
four	O
bits	O
in	O
some	O
microcontrollers	B-Architecture
to	O
many	O
hundreds	O
of	O
bits	O
in	O
some	O
VLIW	B-General_Concept
systems	O
.	O
</s>
<s>
Processors	O
used	O
in	O
personal	B-Device
computers	I-Device
,	O
mainframes	B-Architecture
,	O
and	O
supercomputers	B-Architecture
have	O
minimum	O
instruction	O
sizes	O
between	O
8	O
and	O
64	O
bits	O
.	O
</s>
<s>
The	O
longest	O
possible	O
instruction	O
on	O
x86	O
is	O
15	O
bytes	B-Application
(	O
120	O
bits	O
)	O
.	O
</s>
<s>
Within	O
an	O
instruction	O
set	O
,	O
different	O
instructions	B-Language
may	O
have	O
different	O
lengths	O
.	O
</s>
<s>
In	O
some	O
architectures	O
,	O
notably	O
most	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computers	I-Architecture
(	O
RISC	B-Architecture
)	O
,	O
,	O
typically	O
corresponding	O
with	O
that	O
architecture	O
's	O
word	O
size	O
.	O
</s>
<s>
In	O
other	O
architectures	O
,	O
instructions	B-Language
have	O
variable	B-Algorithm
length	I-Algorithm
,	O
typically	O
integral	O
multiples	O
of	O
a	O
byte	B-Application
or	O
a	O
halfword	O
.	O
</s>
<s>
Some	O
,	O
such	O
as	O
the	O
ARM	B-Architecture
with	O
Thumb-extension	O
have	O
mixed	O
variable	O
encoding	O
,	O
that	O
is	O
two	O
fixed	O
,	O
usually	O
32-bit	O
and	O
16-bit	O
encodings	O
,	O
where	O
instructions	B-Language
cannot	O
be	O
mixed	O
freely	O
but	O
must	O
be	O
switched	O
between	O
on	O
a	O
branch	B-General_Concept
(	O
or	O
exception	O
boundary	O
in	O
ARMv8	O
)	O
.	O
</s>
<s>
Fixed-length	O
instructions	B-Language
are	O
less	O
complicated	O
to	O
handle	O
than	O
variable-length	O
instructions	B-Language
for	O
several	O
reasons	O
(	O
not	O
having	O
to	O
check	O
whether	O
an	O
instruction	O
straddles	O
a	O
cache	B-General_Concept
line	O
or	O
virtual	B-Architecture
memory	I-Architecture
page	O
boundary	O
,	O
for	O
instance	O
)	O
,	O
and	O
are	O
therefore	O
somewhat	O
easier	O
to	O
optimize	O
for	O
speed	O
.	O
</s>
<s>
In	O
early	O
1960s	O
computers	O
,	O
main	B-Architecture
memory	I-Architecture
was	O
expensive	O
and	O
very	O
limited	O
,	O
even	O
on	O
mainframes	B-Architecture
.	O
</s>
<s>
Thus	O
the	O
size	O
of	O
the	O
instructions	B-Language
needed	O
to	O
perform	O
a	O
particular	O
task	O
,	O
the	O
code	O
density	O
,	O
was	O
an	O
important	O
characteristic	O
of	O
any	O
instruction	O
set	O
.	O
</s>
<s>
Density	O
remains	O
important	O
today	O
,	O
for	O
smartphone	O
applications	O
,	O
applications	O
downloaded	O
into	O
browsers	O
over	O
slow	O
Internet	O
connections	O
,	O
and	O
in	O
ROMs	B-Device
for	O
embedded	O
applications	O
.	O
</s>
<s>
Computers	O
with	O
high	O
code	O
density	O
often	O
have	O
complex	O
instructions	B-Language
for	O
procedure	O
entry	O
,	O
parameterized	O
returns	O
,	O
loops	O
,	O
etc	O
.	O
</s>
<s>
(	O
therefore	O
retroactively	O
named	O
Complex	B-Architecture
Instruction	I-Architecture
Set	I-Architecture
Computers	I-Architecture
,	O
CISC	B-Architecture
)	O
.	O
</s>
<s>
However	O
,	O
more	O
typical	O
,	O
or	O
frequent	O
,	O
"	O
CISC	B-Architecture
"	O
instructions	B-Language
merely	O
combine	O
a	O
basic	O
ALU	B-General_Concept
operation	O
,	O
such	O
as	O
"	O
add	O
"	O
,	O
with	O
the	O
access	O
of	O
one	O
or	O
more	O
operands	O
in	O
memory	O
(	O
using	O
addressing	B-Language
modes	I-Language
such	O
as	O
direct	O
,	O
indirect	O
,	O
indexed	O
,	O
etc	O
.	O
)	O
.	O
</s>
<s>
Software-implemented	O
instruction	O
sets	O
may	O
have	O
even	O
more	O
complex	O
and	O
powerful	O
instructions	B-Language
.	O
</s>
<s>
Reduced	O
instruction-set	O
computers	O
,	O
RISC	B-Architecture
,	O
were	O
first	O
widely	O
implemented	O
during	O
a	O
period	O
of	O
rapidly	O
growing	O
memory	O
subsystems	O
.	O
</s>
<s>
They	O
sacrifice	O
code	O
density	O
to	O
simplify	O
implementation	O
circuitry	O
,	O
and	O
try	O
to	O
increase	O
performance	O
via	O
higher	O
clock	O
frequencies	O
and	O
more	O
registers	B-General_Concept
.	O
</s>
<s>
A	O
single	O
RISC	B-Architecture
instruction	O
typically	O
performs	O
only	O
a	O
single	O
operation	O
,	O
such	O
as	O
an	O
"	O
add	O
"	O
of	O
registers	B-General_Concept
or	O
a	O
"	O
load	O
"	O
from	O
a	O
memory	O
location	O
into	O
a	O
register	B-General_Concept
.	O
</s>
<s>
A	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
normally	O
has	O
a	O
fixed	O
instruction	O
length	O
,	O
whereas	O
a	O
typical	O
CISC	B-Architecture
instruction	O
set	O
has	O
instructions	B-Language
of	O
widely	O
varying	O
length	O
.	O
</s>
<s>
However	O
,	O
as	O
RISC	B-Architecture
computers	O
normally	O
require	O
more	O
and	O
often	O
longer	O
instructions	B-Language
to	O
implement	O
a	O
given	O
task	O
,	O
they	O
inherently	O
make	O
less	O
optimal	O
use	O
of	O
bus	O
bandwidth	O
and	O
cache	B-General_Concept
memories	O
.	O
</s>
<s>
Certain	O
embedded	O
RISC	B-Architecture
ISAs	O
like	O
Thumb	O
and	O
AVR32	B-Device
typically	O
exhibit	O
very	O
high	O
density	O
owing	O
to	O
a	O
technique	O
called	O
code	O
compression	O
.	O
</s>
<s>
This	O
technique	O
packs	O
two	O
16-bit	O
instructions	B-Language
into	O
one	O
32-bit	O
word	O
,	O
which	O
is	O
then	O
unpacked	O
at	O
the	O
decode	O
stage	O
and	O
executed	O
as	O
two	O
instructions	B-Language
.	O
</s>
<s>
Minimal	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
computers	I-General_Concept
(	O
MISC	O
)	O
are	O
commonly	O
a	O
form	O
of	O
stack	B-Application
machine	I-Application
,	O
where	O
there	O
are	O
few	O
separate	O
instructions	B-Language
(	O
8	O
–	O
32	O
)	O
,	O
so	O
that	O
multiple	O
instructions	B-Language
can	O
be	O
fit	O
into	O
a	O
single	O
machine	O
word	O
.	O
</s>
<s>
These	O
types	O
of	O
cores	O
often	O
take	O
little	O
silicon	O
to	O
implement	O
,	O
so	O
they	O
can	O
be	O
easily	O
realized	O
in	O
an	O
FPGA	B-Architecture
or	O
in	O
a	O
multi-core	B-Architecture
form	O
.	O
</s>
<s>
The	O
code	O
density	O
of	O
MISC	O
is	O
similar	O
to	O
the	O
code	O
density	O
of	O
RISC	B-Architecture
;	O
the	O
increased	O
instruction	O
density	O
is	O
offset	O
by	O
requiring	O
more	O
of	O
the	O
primitive	O
instructions	B-Language
to	O
do	O
a	O
task	O
.	O
</s>
<s>
There	O
has	O
been	O
research	O
into	O
executable	B-Application
compression	I-Application
as	O
a	O
mechanism	O
for	O
improving	O
code	O
density	O
.	O
</s>
<s>
In	O
practice	O
,	O
code	O
density	O
is	O
also	O
dependent	O
on	O
the	O
compiler	B-Language
.	O
</s>
<s>
Most	O
optimizing	B-Application
compilers	I-Application
have	O
options	O
that	O
control	O
whether	O
to	O
optimize	O
code	O
generation	O
for	O
execution	O
speed	O
or	O
for	O
code	O
density	O
.	O
</s>
<s>
For	O
instance	O
GCC	B-Application
has	O
the	O
option	O
-Os	O
to	O
optimize	O
for	O
small	O
machine	B-Language
code	I-Language
size	O
,	O
and	O
-O3	O
to	O
optimize	O
for	O
execution	O
speed	O
at	O
the	O
cost	O
of	O
larger	O
machine	B-Language
code	I-Language
.	O
</s>
<s>
The	O
instructions	B-Language
constituting	O
a	O
program	O
are	O
rarely	O
specified	O
using	O
their	O
internal	O
,	O
numeric	B-Algorithm
form	O
(	O
machine	B-Language
code	I-Language
)	O
;	O
they	O
may	O
be	O
specified	O
by	O
programmers	O
using	O
an	O
assembly	B-Language
language	I-Language
or	O
,	O
more	O
commonly	O
,	O
may	O
be	O
generated	O
from	O
high-level	B-Language
programming	I-Language
languages	I-Language
by	O
compilers	B-Language
.	O
</s>
<s>
The	O
first	O
was	O
the	O
CISC	B-Architecture
(	O
Complex	B-Architecture
Instruction	I-Architecture
Set	I-Architecture
Computer	I-Architecture
)	O
,	O
which	O
had	O
many	O
different	O
instructions	B-Language
.	O
</s>
<s>
In	O
the	O
1970s	O
,	O
however	O
,	O
places	O
like	O
IBM	O
did	O
research	O
and	O
found	O
that	O
many	O
instructions	B-Language
in	O
the	O
set	O
could	O
be	O
eliminated	O
.	O
</s>
<s>
The	O
result	O
was	O
the	O
RISC	B-Architecture
(	O
Reduced	B-Architecture
Instruction	I-Architecture
Set	I-Architecture
Computer	I-Architecture
)	O
,	O
an	O
architecture	O
that	O
uses	O
a	O
smaller	O
set	O
of	O
instructions	B-Language
.	O
</s>
<s>
However	O
,	O
a	O
more	O
complex	O
set	O
may	O
optimize	O
common	O
operations	O
,	O
improve	O
memory	O
and	O
cache	B-General_Concept
efficiency	O
,	O
or	O
simplify	O
programming	O
.	O
</s>
<s>
Some	O
instruction	O
set	O
designers	O
reserve	O
one	O
or	O
more	O
opcodes	B-Language
for	O
some	O
kind	O
of	O
system	B-Operating_System
call	I-Operating_System
or	O
software	O
interrupt	O
.	O
</s>
<s>
For	O
example	O
,	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
uses	O
00H	O
,	O
Zilog	B-General_Concept
Z80	I-General_Concept
uses	O
the	O
eight	O
codes	O
C7	O
,	O
CF	O
,	O
D7	O
,	O
DF	O
,	O
E7	O
,	O
EF	O
,	O
F7	O
,	O
FFH	O
while	O
Motorola	B-Device
68000	I-Device
use	O
codes	O
in	O
the	O
range	O
A000	O
..	O
AFFFH	O
.	O
</s>
<s>
Fast	O
virtual	B-Architecture
machines	I-Architecture
are	O
much	O
easier	O
to	O
implement	O
if	O
an	O
instruction	O
set	O
meets	O
the	O
Popek	B-Architecture
and	I-Architecture
Goldberg	I-Architecture
virtualization	I-Architecture
requirements	I-Architecture
.	O
</s>
<s>
The	O
NOP	B-Language
slide	O
used	O
in	O
immunity-aware	O
programming	O
is	O
much	O
easier	O
to	O
implement	O
if	O
the	O
"	O
unprogrammed	O
"	O
state	O
of	O
the	O
memory	O
is	O
interpreted	O
as	O
a	O
NOP	B-Language
.	O
</s>
<s>
On	O
systems	O
with	O
multiple	O
processors	O
,	O
non-blocking	B-Operating_System
synchronization	I-Operating_System
algorithms	O
are	O
much	O
easier	O
to	O
implement	O
if	O
the	O
instruction	O
set	O
includes	O
support	O
for	O
something	O
such	O
as	O
"	O
fetch-and-add	B-Operating_System
"	O
,	O
"	O
load-link/store	B-Operating_System
-conditional	I-Operating_System
"	O
(	O
LL/SC	B-Operating_System
)	O
,	O
or	O
"	O
atomic	O
compare-and-swap	B-Operating_System
"	O
.	O
</s>
<s>
When	O
designing	O
the	O
microarchitecture	B-General_Concept
of	O
a	O
processor	O
,	O
engineers	O
use	O
blocks	O
of	O
"	O
hard-wired	O
"	O
electronic	O
circuitry	O
(	O
often	O
designed	O
separately	O
)	O
such	O
as	O
adders	O
,	O
multiplexers	O
,	O
counters	O
,	O
registers	B-General_Concept
,	O
ALUs	O
,	O
etc	O
.	O
</s>
<s>
Some	O
kind	O
of	O
register	B-Application
transfer	I-Application
language	I-Application
is	O
then	O
often	O
used	O
to	O
describe	O
the	O
decoding	O
and	O
sequencing	O
of	O
each	O
instruction	O
of	O
an	O
ISA	O
using	O
this	O
physical	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
There	O
are	O
two	O
basic	O
ways	O
to	O
build	O
a	O
control	B-General_Concept
unit	I-General_Concept
to	O
implement	O
this	O
description	O
(	O
although	O
many	O
designs	O
use	O
middle	O
ways	O
or	O
compromises	O
)	O
:	O
</s>
<s>
Some	O
computer	B-General_Concept
designs	I-General_Concept
"	O
hardwire	O
"	O
the	O
complete	O
instruction	O
set	O
decoding	O
and	O
sequencing	O
(	O
just	O
like	O
the	O
rest	O
of	O
the	O
microarchitecture	B-General_Concept
)	O
.	O
</s>
<s>
Other	O
designs	O
employ	O
microcode	B-Device
routines	O
or	O
tables	O
(	O
or	O
both	O
)	O
to	O
do	O
thistypically	O
as	O
on-chip	O
ROMs	B-Device
or	O
PLAs	O
or	O
both	O
(	O
although	O
separate	O
RAMs	B-Architecture
and	O
ROMs	B-Device
have	O
been	O
used	O
historically	O
)	O
.	O
</s>
<s>
The	O
Western	O
Digital	O
MCP-1600	B-General_Concept
is	O
an	O
older	O
example	O
,	O
using	O
a	O
dedicated	O
,	O
separate	O
ROM	B-Device
for	O
microcode	B-Device
.	O
</s>
<s>
Some	O
designs	O
use	O
a	O
combination	O
of	O
hardwired	O
design	O
and	O
microcode	B-Device
for	O
the	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Some	O
CPU	B-General_Concept
designs	I-General_Concept
use	O
a	O
writable	O
control	O
store	O
—	O
they	O
compile	B-Language
the	O
instruction	O
set	O
to	O
a	O
writable	O
RAM	B-Architecture
or	O
flash	B-Device
inside	O
the	O
CPU	O
(	O
such	O
as	O
the	O
Rekursiv	B-General_Concept
processor	O
and	O
the	O
Imsys	O
Cjip	O
)	O
,	O
or	O
an	O
FPGA	B-Architecture
(	O
reconfigurable	B-Architecture
computing	I-Architecture
)	O
.	O
</s>
<s>
An	O
ISA	O
can	O
also	O
be	O
emulated	B-Application
in	O
software	O
by	O
an	O
interpreter	B-Application
.	O
</s>
<s>
Naturally	O
,	O
due	O
to	O
the	O
interpretation	O
overhead	O
,	O
this	O
is	O
slower	O
than	O
directly	O
running	O
programs	O
on	O
the	O
emulated	B-Application
hardware	O
,	O
unless	O
the	O
hardware	O
running	O
the	O
emulator	B-Application
is	O
an	O
order	O
of	O
magnitude	O
faster	O
.	O
</s>
<s>
Today	O
,	O
it	O
is	O
common	O
practice	O
for	O
vendors	O
of	O
new	O
ISAs	O
or	O
microarchitectures	B-General_Concept
to	O
make	O
software	B-Application
emulators	I-Application
available	O
to	O
software	O
developers	O
before	O
the	O
hardware	O
implementation	O
is	O
ready	O
.	O
</s>
<s>
Often	O
the	O
details	O
of	O
the	O
implementation	O
have	O
a	O
strong	O
influence	O
on	O
the	O
particular	O
instructions	B-Language
selected	O
for	O
the	O
instruction	O
set	O
.	O
</s>
<s>
For	O
example	O
,	O
many	O
implementations	O
of	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
only	O
allow	O
a	O
single	O
memory	O
load	O
or	O
memory	O
store	O
per	O
instruction	O
,	O
leading	O
to	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
(	O
RISC	B-Architecture
)	O
.	O
</s>
<s>
For	O
another	O
example	O
,	O
some	O
early	O
ways	O
of	O
implementing	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
led	O
to	O
a	O
delay	B-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
The	O
demands	O
of	O
high-speed	O
digital	O
signal	O
processing	O
have	O
pushed	O
in	O
the	O
opposite	O
direction	O
—	O
forcing	O
instructions	B-Language
to	O
be	O
implemented	O
in	O
a	O
particular	O
way	O
.	O
</s>
<s>
For	O
example	O
,	O
to	O
perform	O
digital	O
filters	O
fast	O
enough	O
,	O
the	O
MAC	O
instruction	O
in	O
a	O
typical	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
must	O
use	O
a	O
kind	O
of	O
Harvard	B-Architecture
architecture	I-Architecture
that	O
can	O
fetch	O
an	O
instruction	O
and	O
two	O
data	O
words	O
simultaneously	O
,	O
and	O
it	O
requires	O
a	O
single-cycle	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
multiplier	O
.	O
</s>
