<s>
The	O
Elbrus	B-General_Concept
2000	I-General_Concept
,	O
E2K	B-General_Concept
(	O
)	O
is	O
a	O
Russian	O
512-bit	O
wide	O
VLIW	B-General_Concept
microprocessor	O
developed	O
by	O
Moscow	O
Center	O
of	O
SPARC	O
Technologies	O
(	O
MCST	O
)	O
and	O
fabricated	O
by	O
TSMC	O
.	O
</s>
<s>
It	O
supports	O
two	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
(	O
ISA	B-General_Concept
)	O
:	O
</s>
<s>
Thanks	O
to	O
its	O
unique	O
architecture	O
the	O
Elbrus	B-General_Concept
2000	I-General_Concept
can	O
execute	O
20	O
instructions	O
per	O
clock	O
,	O
so	O
even	O
with	O
its	O
modest	O
clock	O
speed	O
it	O
can	O
compete	O
with	O
much	O
faster	O
clocked	O
superscalar	B-General_Concept
microprocessors	O
when	O
running	O
in	O
native	O
VLIW	B-General_Concept
mode	O
.	O
</s>
<s>
For	O
security	O
reasons	O
the	O
Elbrus	B-General_Concept
2000	I-General_Concept
architecture	O
implements	O
dynamic	O
data	O
type-checking	O
during	O
execution	B-General_Concept
.	O
</s>
