<s>
The	O
EVEX	B-General_Concept
prefix	I-General_Concept
(	O
enhanced	O
vector	O
extension	O
)	O
and	O
corresponding	O
coding	O
scheme	O
is	O
an	O
extension	O
to	O
the	O
32-bit	O
x86	B-Operating_System
(	O
IA-32	O
)	O
and	O
64-bit	O
x86-64	O
(	O
AMD64	B-Device
)	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
EVEX	B-General_Concept
is	O
based	O
on	O
,	O
but	O
should	O
not	O
be	O
confused	O
with	O
the	O
MVEX	O
prefix	O
used	O
by	O
the	O
Knights	O
Corner	O
processor	O
.	O
</s>
<s>
The	O
EVEX	B-General_Concept
scheme	O
is	O
a	O
4-byte	O
extension	O
to	O
the	O
VEX	B-General_Concept
scheme	O
which	O
supports	O
the	O
AVX-512	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
and	O
allows	O
addressing	O
new	O
512-bit	O
ZMM	O
registers	O
and	O
new	O
64-bit	O
operand	O
mask	O
registers	O
.	O
</s>
<s>
EVEX	B-General_Concept
coding	O
can	O
address	O
8	O
operand	O
mask	O
registers	O
,	O
16	O
general-purpose	O
registers	O
and	O
32	O
vector	O
registers	O
in	O
64-bit	O
mode	O
(	O
otherwise	O
,	O
8	O
general-purpose	O
and	O
8	O
vector	O
)	O
,	O
and	O
can	O
support	O
up	O
to	O
4	O
operands	O
.	O
</s>
<s>
Like	O
the	O
VEX	B-General_Concept
coding	I-General_Concept
scheme	I-General_Concept
,	O
the	O
EVEX	B-General_Concept
prefix	I-General_Concept
unifies	O
existing	O
opcode	O
prefixes	O
and	O
escape	O
codes	O
,	O
memory	O
addressing	O
and	O
operand	O
length	O
modifiers	O
of	O
the	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
The	O
following	O
features	O
are	O
carried	O
over	O
from	O
the	O
VEX	B-General_Concept
scheme	O
:	O
</s>
<s>
Direct	O
encoding	O
of	O
three	O
SIMD	B-Device
registers	O
(	O
XMM	O
,	O
YMM	O
,	O
or	O
ZMM	O
)	O
as	O
source	O
operands	O
(	O
MMX	O
or	O
x87	O
registers	O
are	O
not	O
supported	O
)	O
;	O
</s>
<s>
Compacted	O
SIMD	B-Device
prefix	O
(	O
66h	O
,	O
F2h	O
,	O
F3h	O
)	O
,	O
escape	O
opcode	O
(	O
0Fh	O
)	O
and	O
two-byte	O
escape	O
(	O
0F38h	O
,	O
0F3Ah	O
)	O
;	O
</s>
<s>
EVEX	B-General_Concept
also	O
extends	O
VEX	B-General_Concept
with	O
additional	O
capabilities	O
:	O
</s>
<s>
Extended	O
SIMD	B-Device
register	O
encoding	O
:	O
a	O
total	O
of	O
32	O
new	O
512-bit	O
SIMD	B-Device
registers	O
ZMM0	O
–	O
ZMM31	O
in	O
64-bit	O
mode	O
;	O
</s>
<s>
Direct	O
embedded	O
rounding	O
control	O
for	O
instructions	O
that	O
operate	O
on	O
floating-point	O
SIMD	B-Device
registers	O
with	O
rounding	O
semantics	O
;	O
</s>
<s>
Compressed	O
displacement	O
(	O
Disp8	O
×	O
N	O
)	O
,	O
new	O
memory	O
addressing	O
mode	O
to	O
improve	O
encoding	O
density	O
of	O
instruction	O
byte	B-Application
stream	O
;	O
the	O
scale	O
factor	O
N	O
depends	O
on	O
vector	O
length	O
and	O
broadcast	O
mode	O
.	O
</s>
<s>
where	O
 { k1 } 	O
modifier	O
next	O
to	O
the	O
destination	O
operand	O
encodes	O
the	O
use	O
of	O
opmask	O
register	O
k1	O
for	O
conditional	O
processing	O
and	O
updates	O
to	O
destination	O
,	O
and	O
 { z } 	O
modifier	O
(	O
encoded	O
by	O
EVEX.z	O
)	O
provides	O
the	O
two	O
types	O
of	O
masking	O
(	O
merging	O
and	O
zeroing	O
)	O
,	O
with	O
merging	O
as	O
default	O
when	O
no	O
modifier	O
is	O
attached	O
.	O
</s>
<s>
The	O
EVEX	B-General_Concept
coding	O
scheme	O
uses	O
a	O
code	O
prefix	O
consisting	O
of	O
4	O
bytes	B-Application
;	O
the	O
first	O
byte	B-Application
is	O
always	O
62h	O
and	O
derives	O
from	O
an	O
unused	O
opcode	O
of	O
the	O
32-bit	O
BOUND	O
instruction	O
,	O
which	O
is	O
not	O
supported	O
in	O
64-bit	O
mode	O
.	O
</s>
<s>
The	O
ModR/M	O
byte	B-Application
specifies	O
one	O
operand	O
(	O
always	O
a	O
register	O
)	O
with	O
reg	O
field	O
,	O
and	O
the	O
second	O
operand	O
is	O
encoded	O
with	O
mod	O
and	O
r/m	O
fields	O
,	O
specifying	O
either	O
a	O
register	O
or	O
a	O
location	O
in	O
memory	O
.	O
</s>
<s>
Base-plus-index	O
and	O
scale-plus-index	O
addressing	O
require	O
the	O
SIB	O
byte	B-Application
,	O
which	O
encodes	O
2-bit	O
scale	O
factor	O
as	O
well	O
as	O
3-bit	O
index	O
and	O
3-bit	O
base	O
registers	O
.	O
</s>
<s>
The	O
EVEX	B-General_Concept
prefix	I-General_Concept
retains	O
fields	O
introduced	O
in	O
the	O
VEX	B-General_Concept
prefix	I-General_Concept
:	O
</s>
<s>
W	O
expands	O
the	O
operand	O
size	O
to	O
64	O
bits	O
or	O
serves	O
as	O
an	O
additional	O
opcode	O
,	O
R	O
expands	O
reg	O
,	O
B	O
expands	O
r/m	O
or	O
reg	O
,	O
and	O
X	O
and	O
B	O
expand	O
index	O
and	O
base	O
in	O
the	O
SIB	O
byte	B-Application
.	O
</s>
<s>
Just	O
like	O
in	O
VEX	B-General_Concept
prefix	I-General_Concept
,	O
RXB	O
are	O
provided	O
in	O
inverted	O
form	O
.	O
</s>
<s>
Just	O
like	O
in	O
VEX	B-General_Concept
prefix	I-General_Concept
,	O
vvvv	O
is	O
provided	O
in	O
inverted	O
form	O
.	O
</s>
<s>
Bit	O
X	O
now	O
expands	O
r/m	O
along	O
with	O
bit	O
B	O
when	O
the	O
SIB	O
byte	B-Application
is	O
not	O
present	O
,	O
which	O
allows	O
32	O
SIMD	B-Device
registers	O
.	O
</s>
<s>
The	O
encoding	O
of	O
the	O
EVEX	B-General_Concept
prefix	I-General_Concept
is	O
as	O
follows	O
:	O
</s>
<s>
A	O
few	O
VEX-encoded	O
AVX	O
blending	O
instructions	O
have	O
4	O
operands	O
.	O
</s>
<s>
To	O
accommodate	O
this	O
,	O
VEX	B-General_Concept
has	O
IS4	O
addressing	O
mode	O
,	O
which	O
encodes	O
4th	O
operand	O
(	O
a	O
vector	O
register	O
)	O
in	O
bits	O
Imm8[7:4]	O
of	O
the	O
immediate	O
constant	O
.	O
</s>
<s>
Similar	O
EVEX-encoded	O
blend	O
instructions	O
have	O
their	O
4th	O
operand	O
in	O
a	O
mask	O
register	O
.	O
</s>
<s>
No	O
EVEX-encoded	O
instruction	O
uses	O
IS4	O
addressing	O
mode	O
encoding	O
.	O
</s>
