<s>
The	O
Dragon	B-General_Concept
Protocol	I-General_Concept
is	O
an	O
update	O
based	O
cache	B-General_Concept
coherence	I-General_Concept
protocol	O
used	O
in	O
multi-processor	B-Operating_System
systems	O
.	O
</s>
<s>
Write	O
propagation	O
is	O
performed	O
by	O
directly	O
updating	O
all	O
the	O
cached	B-General_Concept
values	O
across	O
multiple	O
processors	O
.	O
</s>
<s>
Update	O
based	O
protocols	O
such	O
as	O
the	O
Dragon	B-General_Concept
protocol	I-General_Concept
perform	O
efficiently	O
when	O
a	O
write	O
to	O
a	O
cache	B-General_Concept
block	O
is	O
followed	O
by	O
several	O
reads	O
made	O
by	O
other	O
processors	O
,	O
since	O
the	O
updated	O
cache	B-General_Concept
block	O
is	O
readily	O
available	O
across	O
caches	B-General_Concept
associated	O
with	O
all	O
the	O
processors	O
.	O
</s>
<s>
Each	O
cache	B-General_Concept
block	O
resides	O
in	O
one	O
of	O
the	O
four	O
states	O
:	O
exclusive-clean	O
,	O
shared-clean	O
,	O
shared-modified	O
and	O
modify	O
.	O
</s>
<s>
Exclusive-clean	O
(	O
E	O
)	O
:	O
This	O
means	O
that	O
the	O
cache	B-General_Concept
block	O
was	O
first	O
fetched	O
by	O
the	O
current	O
processor	O
and	O
has	O
not	O
been	O
accessed	O
by	O
any	O
other	O
processor	O
since	O
.	O
</s>
<s>
Shared	O
clean	O
(	O
Sc	O
)	O
:	O
This	O
means	O
that	O
the	O
cache	B-General_Concept
block	O
definitely	O
exists	O
in	O
multiple	O
processor	O
’s	O
caches	B-General_Concept
,	O
and	O
that	O
the	O
current	O
processor	O
is	O
not	O
the	O
last	O
one	O
to	O
write	O
the	O
block	O
.	O
</s>
<s>
States	O
E	O
and	O
Sc	O
are	O
maintained	O
separately	O
by	O
the	O
protocol	O
to	O
prevent	O
read-write	O
operations	O
on	O
cache	B-General_Concept
blocks	O
that	O
are	O
not	O
shared	O
,	O
from	O
inducing	O
bus	O
transactions	O
,	O
and	O
hence	O
slowing	O
down	O
the	O
execution	O
.	O
</s>
<s>
Shared	O
modified	O
(	O
Sm	O
)	O
:	O
This	O
means	O
that	O
the	O
block	O
exists	O
in	O
caches	B-General_Concept
of	O
multiple	O
processors	O
,	O
and	O
the	O
current	O
processor	O
is	O
the	O
last	O
one	O
to	O
modify	O
the	O
block	O
.	O
</s>
<s>
It	O
is	O
the	O
processor	O
’s	O
responsibility	O
to	O
update	O
the	O
main	O
memory	O
when	O
the	O
cache	B-General_Concept
block	O
is	O
evicted	O
.	O
</s>
<s>
For	O
any	O
given	O
pair	O
of	O
caches	B-General_Concept
,	O
the	O
permitted	O
states	O
of	O
a	O
given	O
cache	B-General_Concept
block	O
in	O
conjunction	O
with	O
the	O
states	O
of	O
the	O
other	O
cache	B-General_Concept
's	O
states	O
,	O
are	O
as	O
follows	O
(	O
the	O
states	O
abbreviated	O
in	O
the	O
order	O
above	O
)	O
:	O
</s>
<s>
Processor	O
Read	O
(	O
PrRd	O
)	O
:	O
This	O
happens	O
when	O
the	O
processor	O
completes	O
a	O
successful	O
read	O
on	O
a	O
certain	O
cache	B-General_Concept
block	O
placed	O
in	O
its	O
cache	B-General_Concept
.	O
</s>
<s>
Processor	O
Write	O
(	O
PrWr	O
)	O
:	O
This	O
happens	O
when	O
the	O
processor	O
completes	O
a	O
successful	O
write	O
on	O
a	O
certain	O
cache	B-General_Concept
block	O
placed	O
in	O
its	O
cache	B-General_Concept
.	O
</s>
<s>
This	O
makes	O
the	O
processor	O
to	O
be	O
the	O
latest	O
to	O
update	O
the	O
cache	B-General_Concept
block	O
.	O
</s>
<s>
Processor	O
Read	O
Miss	O
(	O
PrRdMiss	O
)	O
:	O
This	O
happens	O
when	O
the	O
processor	O
fails	O
to	O
read	O
a	O
cache	B-General_Concept
block	O
from	O
its	O
cache	B-General_Concept
,	O
and	O
needs	O
to	O
fetch	O
the	O
block	O
from	O
either	O
the	O
memory	O
or	O
another	O
cache	B-General_Concept
.	O
</s>
<s>
Processor	O
Write	O
Miss	O
(	O
PrWrMiss	O
)	O
:	O
This	O
happens	O
when	O
the	O
processor	O
fails	O
to	O
write	O
to	O
a	O
cache	B-General_Concept
block	O
from	O
its	O
cache	B-General_Concept
,	O
and	O
needs	O
to	O
fetch	O
the	O
block	O
from	O
the	O
memory	O
or	O
another	O
cache	B-General_Concept
and	O
then	O
write	O
to	O
it	O
.	O
</s>
<s>
This	O
again	O
makes	O
the	O
processor	O
to	O
be	O
the	O
latest	O
to	O
update	O
the	O
cache	B-General_Concept
block	O
.	O
</s>
<s>
Bus	O
Read	O
(	O
BusRd	O
)	O
:	O
This	O
happens	O
when	O
a	O
processor	O
requests	O
the	O
bus	O
to	O
fetch	O
the	O
latest	O
value	O
of	O
the	O
cache	B-General_Concept
block	O
,	O
whether	O
it	O
be	O
from	O
the	O
main	O
memory	O
or	O
another	O
processor	O
’s	O
cache	B-General_Concept
.	O
</s>
<s>
Flush	O
:	O
This	O
happens	O
when	O
a	O
processor	O
places	O
an	O
entire	O
cache	B-General_Concept
block	O
on	O
the	O
bus	O
.	O
</s>
<s>
This	O
is	O
to	O
reflect	O
the	O
changes	O
made	O
by	O
the	O
processor	O
to	O
the	O
cached	B-General_Concept
block	O
in	O
the	O
main	O
memory	O
.	O
</s>
<s>
Bus	O
Update	O
(	O
BusUpd	O
)	O
:	O
This	O
happens	O
when	O
a	O
processor	O
modifies	O
a	O
cache	B-General_Concept
block	O
,	O
and	O
other	O
processors	O
need	O
an	O
update	O
in	O
their	O
respective	O
cache	B-General_Concept
blocks	O
.	O
</s>
<s>
BusUpd	O
takes	O
shorter	O
time	O
when	O
compared	O
to	O
Flush	O
operation	O
,	O
since	O
writes	O
made	O
to	O
caches	B-General_Concept
are	O
faster	O
than	O
to	O
memory	O
.	O
</s>
<s>
Another	O
point	O
to	O
note	O
is	O
that	O
a	O
cache	B-General_Concept
cannot	O
update	O
its	O
local	O
copy	O
of	O
a	O
cache	B-General_Concept
block	O
and	O
then	O
request	O
the	O
bus	O
to	O
send	O
out	O
a	O
bus	O
update	O
.	O
</s>
<s>
If	O
this	O
does	O
happen	O
,	O
then	O
it	O
might	O
be	O
possible	O
that	O
two	O
caches	B-General_Concept
independently	O
update	O
their	O
local	O
copy	O
and	O
then	O
request	O
for	O
the	O
bus	O
.	O
</s>
<s>
They	O
would	O
then	O
see	O
the	O
two	O
writes	O
simultaneously	O
which	O
would	O
not	O
follow	O
Sequential	B-General_Concept
consistency	I-General_Concept
.	O
</s>
<s>
A	O
shared	O
line	O
is	O
also	O
required	O
to	O
indicate	O
whether	O
a	O
certain	O
cache	B-General_Concept
block	O
is	O
available	O
in	O
multiple	O
caches	B-General_Concept
.	O
</s>
<s>
This	O
is	O
required	O
because	O
one	O
of	O
the	O
caches	B-General_Concept
could	O
evict	O
the	O
block	O
without	O
needing	O
to	O
update	O
the	O
other	O
blocks	O
.	O
</s>
<s>
The	O
shared	O
line	O
helps	O
reduce	O
memory	O
and	O
bus	O
transactions	O
in	O
some	O
cases	O
where	O
the	O
block	O
is	O
available	O
in	O
only	O
one	O
cache	B-General_Concept
and	O
a	O
bus	O
update	O
is	O
hence	O
,	O
not	O
required	O
.	O
</s>
<s>
Such	O
a	O
dedicated	O
line	O
to	O
detect	O
sharing	O
is	O
seen	O
across	O
write-update	O
protocols	O
,	O
like	O
the	O
Firefly	B-Device
protocol	I-Device
and	O
implemented	O
based	O
on	O
bus	O
standards	O
such	O
as	O
Futurebus	B-Architecture
(	O
IEEE	O
standard	O
P896.1	O
)	O
.	O
</s>
<s>
Based	O
on	O
the	O
current	O
state	O
of	O
the	O
block	O
and	O
the	O
transaction	O
initiated	O
by	O
the	O
processor	O
,	O
the	O
cache	B-General_Concept
block	O
undergoes	O
one	O
of	O
the	O
following	O
state	O
transitions	O
:	O
</s>
<s>
When	O
a	O
processor	O
write-miss	O
(	O
PrWrMiss	O
)	O
occurs	O
,	O
and	O
the	O
cache	B-General_Concept
block	O
is	O
shared	O
,	O
the	O
state	O
transitions	O
to	O
Shared	O
Modified	O
and	O
the	O
processor	O
becomes	O
the	O
owner	O
.	O
</s>
<s>
When	O
there	O
is	O
a	O
processor	O
read	O
(	O
PrRd	O
)	O
hit	O
,	O
the	O
state	O
of	O
the	O
cache	B-General_Concept
block	O
does	O
not	O
change	O
,	O
and	O
retains	O
the	O
value	O
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
the	O
Modified	O
state	O
,	O
and	O
the	O
processor	O
writes	O
(	O
PrWr	O
)	O
the	O
block	O
,	O
there	O
is	O
no	O
transition	O
as	O
the	O
block	O
is	O
not	O
being	O
shared	O
.	O
</s>
<s>
When	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
Shared	O
Modified	O
state	O
,	O
and	O
a	O
processor	O
writes	O
(	O
PrWr	O
)	O
,	O
but	O
the	O
shared	O
line	O
is	O
not	O
asserted	O
,	O
the	O
state	O
transitions	O
to	O
Modified	O
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
the	O
Shared	O
Modified	O
state	O
when	O
a	O
write	O
(	O
PrWr	O
)	O
occurs	O
and	O
the	O
shared	O
line	O
is	O
asserted	O
,	O
a	O
bus	O
update	O
(	O
BusUpd	O
)	O
is	O
generated	O
to	O
update	O
the	O
other	O
cache	B-General_Concept
block	O
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
the	O
Shared	O
Clean	O
state	O
when	O
a	O
write	O
(	O
PrWr	O
)	O
occurs	O
and	O
the	O
shared	O
line	O
is	O
asserted	O
,	O
a	O
bus	O
update	O
(	O
BusUpd	O
)	O
is	O
generated	O
to	O
update	O
the	O
other	O
cache	B-General_Concept
block	O
and	O
the	O
state	O
changes	O
to	O
Shared	O
Modified	O
.	O
</s>
<s>
But	O
if	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
the	O
Shared	O
Clean	O
state	O
when	O
a	O
write	O
(	O
PrWr	O
)	O
occurs	O
,	O
but	O
the	O
shared	O
line	O
is	O
not	O
asserted	O
,	O
the	O
state	O
transitions	O
to	O
Modified	O
,	O
and	O
no	O
bus	O
transactions	O
are	O
generated	O
.	O
</s>
<s>
Based	O
on	O
the	O
current	O
state	O
of	O
the	O
block	O
and	O
the	O
transaction	O
initiated	O
by	O
the	O
bus	O
,	O
the	O
cache	B-General_Concept
block	O
undergoes	O
one	O
of	O
the	O
following	O
state	O
transitions	O
:	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
Modified	O
,	O
and	O
a	O
Bus	O
Read	O
(	O
BusRd	O
)	O
is	O
issued	O
,	O
a	O
Flush	O
is	O
issued	O
to	O
update	O
the	O
main	O
memory	O
and	O
the	O
state	O
transitions	O
to	O
Shared	O
Modified	O
,	O
as	O
the	O
block	O
is	O
now	O
in	O
multiple	O
caches	B-General_Concept
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
Shared	O
Modified	O
state	O
,	O
and	O
a	O
bus	O
read	O
(	O
BusRd	O
)	O
,	O
a	O
Flush	O
is	O
issued	O
to	O
update	O
the	O
main	O
memory	O
,	O
and	O
state	O
remains	O
the	O
same	O
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
Shared	O
Modified	O
state	O
,	O
and	O
a	O
bus	O
update	O
(	O
BusUpd	O
)	O
transaction	O
is	O
issued	O
,	O
the	O
state	O
transitions	O
to	O
Shared	O
Clean	O
,	O
all	O
the	O
caches	B-General_Concept
are	O
updated	O
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
block	O
is	O
in	O
Shared	O
Clean	O
state	O
,	O
and	O
it	O
receives	O
a	O
bus	O
read	O
(	O
BusRd	O
)	O
or	O
a	O
bus	O
update	O
(	O
BusUpd	O
)	O
it	O
continues	O
to	O
retain	O
its	O
state	O
as	O
the	O
value	O
is	O
still	O
shared	O
.	O
</s>
<s>
However	O
,	O
in	O
the	O
case	O
of	O
an	O
Update	O
,	O
it	O
will	O
update	O
the	O
value	O
in	O
the	O
cache	B-General_Concept
block	O
.	O
</s>
<s>
The	O
processor	O
with	O
the	O
cache	B-General_Concept
block	O
in	O
Sm	O
state	O
is	O
responsible	O
for	O
updating	O
memory	O
when	O
the	O
cache	B-General_Concept
block	O
is	O
replaced	O
.	O
</s>
<s>
However	O
,	O
this	O
causes	O
a	O
lot	O
more	O
memory	O
transactions	O
which	O
can	O
slow	O
down	O
the	O
system	O
,	O
especially	O
when	O
multiple	O
processors	O
are	O
writing	O
to	O
the	O
same	O
cache	B-General_Concept
block	O
.	O
</s>
<s>
The	O
protocol	O
allows	O
the	O
cache	B-General_Concept
blocks	O
in	O
the	O
Sc	O
state	O
to	O
be	O
replaced	O
silently	O
without	O
any	O
bus	O
activity	O
.	O
</s>
<s>
If	O
a	O
broadcast	O
was	O
made	O
to	O
let	O
other	O
caches	B-General_Concept
know	O
that	O
a	O
Sc	O
block	O
is	O
being	O
replaced	O
,	O
they	O
could	O
test	O
the	O
shared	O
line	O
and	O
move	O
to	O
state	O
E	O
if	O
there	O
were	O
no	O
other	O
sharers	O
.	O
</s>
<s>
And	O
since	O
broadcasting	O
replacements	O
is	O
not	O
time	O
critical	O
,	O
if	O
a	O
cache	B-General_Concept
is	O
not	O
required	O
to	O
process	O
the	O
replacement	O
right	O
away	O
,	O
there	O
is	O
no	O
downside	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
if	O
a	O
cache	B-General_Concept
does	O
not	O
process	O
an	O
update	O
right	O
away	O
,	O
it	O
may	O
lead	O
to	O
out-of-order	O
updates	O
.	O
</s>
<s>
In	O
such	O
cases	O
a	O
three	O
state	O
update	O
protocol	O
,	O
like	O
the	O
Firefly	B-Device
protocol	I-Device
,	O
may	O
have	O
performance	O
advantages	O
.	O
</s>
<s>
Write	O
Invalidate	O
is	O
another	O
set	O
of	O
cache	B-General_Concept
coherence	I-General_Concept
protocols	O
,	O
where	O
once	O
a	O
cache	B-General_Concept
block	O
is	O
modified	O
,	O
the	O
other	O
values	O
of	O
the	O
same	O
block	O
in	O
other	O
caches	B-General_Concept
are	O
not	O
updated	O
,	O
but	O
invalidated	O
.	O
</s>
<s>
Write	O
invalidate	O
protocols	O
are	O
more	O
efficient	O
in	O
cases	O
where	O
are	O
there	O
are	O
many	O
subsequent	O
writes	O
to	O
the	O
same	O
cache	B-General_Concept
block	O
,	O
as	O
the	O
invalidation	O
happens	O
once	O
and	O
further	O
bus	O
transactions	O
by	O
other	O
processors	O
are	O
avoided	O
.	O
</s>
<s>
Since	O
we	O
are	O
updating	O
the	O
other	O
cached	B-General_Concept
values	O
once	O
we	O
write	O
it	O
,	O
they	O
have	O
access	O
to	O
the	O
data	O
immediately	O
.	O
</s>
<s>
the	O
write	O
invalidate	O
protocol	O
is	O
highly	O
disadvantageous	O
because	O
every	O
time	O
a	O
cache	B-General_Concept
block	O
is	O
modified	O
in	O
another	O
cache	B-General_Concept
,	O
the	O
rest	O
of	O
the	O
caches	B-General_Concept
need	O
will	O
encounter	O
a	O
coherence	O
miss	O
,	O
and	O
initiate	O
a	O
bus	O
transaction	O
to	O
read	O
the	O
new	O
value	O
.	O
</s>
<s>
In	O
case	O
of	O
Firefly	B-Device
,	O
cache-to-cache	O
transfers	O
of	O
modified	O
blocks	O
are	O
also	O
written	O
back	O
to	O
main	O
memory	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
But	O
since	O
accesses	O
made	O
to	O
the	O
main	O
memory	O
are	O
slower	O
by	O
orders	O
of	O
magnitude	O
when	O
compared	O
to	O
caches	B-General_Concept
,	O
it	O
requires	O
added	O
complexity	O
of	O
performing	O
a	O
write	O
back	O
as	O
a	O
separate	O
bus	O
operation	O
.	O
</s>
<s>
This	O
problem	O
is	O
avoided	O
altogether	O
in	O
case	O
of	O
Dragon	B-General_Concept
protocol	I-General_Concept
,	O
since	O
the	O
shared	O
blocks	O
are	O
not	O
written	O
back	O
to	O
memory	O
at	O
all	O
.	O
</s>
