<s>
Domino	B-General_Concept
logic	I-General_Concept
is	O
a	O
CMOS-based	O
evolution	O
of	O
the	O
dynamic	B-General_Concept
logic	I-General_Concept
techniques	O
based	O
on	O
either	O
PMOS	O
or	O
NMOS	O
transistors	B-Application
.	O
</s>
<s>
It	O
was	O
developed	O
to	O
speed	O
up	O
circuits	O
,	O
solving	O
the	O
premature	O
cascade	O
problem	O
,	O
typically	O
by	O
inserting	O
small	O
and	O
fast	O
pFETs	B-Application
between	O
domino	O
stages	O
to	O
constrain	O
the	O
interstage	O
cascade	O
velocity	O
to	O
a	O
curtailed	O
maximum	O
—	O
a	O
curtailed	O
deterministic	O
maximum	O
—	O
without	O
requiring	O
other	O
circuit	O
design	O
interlocks	O
.	O
</s>
<s>
The	O
term	O
derives	O
from	O
the	O
fact	O
that	O
in	O
domino	B-General_Concept
logic	I-General_Concept
(	O
cascade	O
structure	O
consisting	O
of	O
several	O
stages	O
)	O
,	O
each	O
stage	O
ripples	O
the	O
next	O
stage	O
for	O
evaluation	O
,	O
similar	O
to	O
dominoes	O
falling	O
one	O
after	O
the	O
other	O
.	O
</s>
<s>
In	O
dynamic	B-General_Concept
logic	I-General_Concept
,	O
a	O
problem	O
arises	O
when	O
cascading	O
one	O
gate	O
to	O
the	O
next	O
.	O
</s>
<s>
In	O
order	O
to	O
cascade	O
dynamic	B-General_Concept
logic	I-General_Concept
gates	O
,	O
one	O
solution	O
is	O
domino	B-General_Concept
logic	I-General_Concept
,	O
which	O
inserts	O
an	O
ordinary	O
static	O
inverter	O
between	O
stages	O
.	O
</s>
<s>
While	O
this	O
might	O
seem	O
to	O
defeat	O
the	O
point	O
of	O
dynamic	B-General_Concept
logic	I-General_Concept
,	O
since	O
the	O
inverter	O
has	O
a	O
pFET	B-Application
(	O
one	O
of	O
the	O
main	O
goals	O
of	O
dynamic	B-General_Concept
logic	I-General_Concept
is	O
to	O
avoid	O
pFETs	B-Application
where	O
possible	O
,	O
due	O
to	O
speed	O
)	O
,	O
there	O
are	O
two	O
reasons	O
it	O
works	O
well	O
.	O
</s>
<s>
First	O
,	O
there	O
is	O
no	O
fan-out	B-General_Concept
to	O
multiple	O
pFETs	B-Application
;	O
the	O
dynamic	O
gate	O
connects	O
to	O
exactly	O
one	O
inverter	O
,	O
so	O
the	O
gate	O
is	O
still	O
very	O
fast	O
.	O
</s>
<s>
Furthermore	O
,	O
since	O
the	O
inverter	O
connects	O
to	O
only	O
nFETs	O
in	O
dynamic	B-General_Concept
logic	I-General_Concept
gates	O
,	O
it	O
too	O
is	O
very	O
fast	O
.	O
</s>
<s>
Second	O
,	O
the	O
pFET	B-Application
in	O
an	O
inverter	O
can	O
be	O
made	O
smaller	O
than	O
in	O
some	O
types	O
of	O
logic	O
gates	O
.	O
</s>
<s>
In	O
domino	B-General_Concept
logic	I-General_Concept
cascade	O
structure	O
of	O
several	O
stages	O
,	O
the	O
evaluation	O
of	O
each	O
stage	O
ripples	O
the	O
next	O
stage	O
evaluation	O
,	O
similar	O
to	O
dominoes	O
falling	O
one	O
after	O
the	O
other	O
.	O
</s>
<s>
Once	O
fallen	O
,	O
the	O
node	O
states	O
cannot	O
return	O
to	O
"	O
1	O
"	O
(	O
until	O
the	O
next	O
clock	O
cycle	O
)	O
just	O
as	O
dominoes	O
,	O
once	O
fallen	O
,	O
cannot	O
stand	O
up	O
,	O
justifying	O
the	O
name	O
domino	O
CMOS	B-Device
logic	O
.	O
</s>
