<s>
Direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
is	O
a	O
feature	O
of	O
computer	O
systems	O
that	O
allows	O
certain	O
hardware	O
subsystems	O
to	O
access	O
main	O
system	O
memory	B-General_Concept
independently	O
of	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-General_Concept
)	O
.	O
</s>
<s>
Without	O
DMA	O
,	O
when	O
the	O
CPU	B-General_Concept
is	O
using	O
programmed	B-General_Concept
input/output	I-General_Concept
,	O
it	O
is	O
typically	O
fully	O
occupied	O
for	O
the	O
entire	O
duration	O
of	O
the	O
read	O
or	O
write	O
operation	O
,	O
and	O
is	O
thus	O
unavailable	O
to	O
perform	O
other	O
work	O
.	O
</s>
<s>
With	O
DMA	O
,	O
the	O
CPU	B-General_Concept
first	O
initiates	O
the	O
transfer	O
,	O
then	O
it	O
does	O
other	O
operations	O
while	O
the	O
transfer	O
is	O
in	O
progress	O
,	O
and	O
it	O
finally	O
receives	O
an	O
interrupt	B-Application
from	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
(	O
DMAC	O
)	O
when	O
the	O
operation	O
is	O
done	O
.	O
</s>
<s>
This	O
feature	O
is	O
useful	O
at	O
any	O
time	O
that	O
the	O
CPU	B-General_Concept
cannot	O
keep	O
up	O
with	O
the	O
rate	O
of	O
data	O
transfer	O
,	O
or	O
when	O
the	O
CPU	B-General_Concept
needs	O
to	O
perform	O
work	O
while	O
waiting	O
for	O
a	O
relatively	O
slow	O
I/O	B-General_Concept
data	O
transfer	O
.	O
</s>
<s>
Many	O
hardware	O
systems	O
use	O
DMA	O
,	O
including	O
disk	B-Device
drive	I-Device
controllers	O
,	O
graphics	B-Device
cards	I-Device
,	O
network	B-Protocol
cards	I-Protocol
and	O
sound	B-Device
cards	I-Device
.	O
</s>
<s>
DMA	O
is	O
also	O
used	O
for	O
intra-chip	O
data	O
transfer	O
in	O
multi-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
Computers	O
that	O
have	O
DMA	O
channels	O
can	O
transfer	O
data	O
to	O
and	O
from	O
devices	O
with	O
much	O
less	O
CPU	B-General_Concept
overhead	O
than	O
computers	O
without	O
DMA	O
channels	O
.	O
</s>
<s>
Similarly	O
,	O
a	O
processing	O
circuitry	O
inside	O
a	O
multi-core	B-Architecture
processor	I-Architecture
can	O
transfer	O
data	O
to	O
and	O
from	O
its	O
local	O
memory	B-General_Concept
without	O
occupying	O
its	O
processor	O
time	O
,	O
allowing	O
computation	O
and	O
data	O
transfer	O
to	O
proceed	O
in	O
parallel	O
.	O
</s>
<s>
DMA	O
can	O
also	O
be	O
used	O
for	O
"	O
memory	B-General_Concept
to	O
memory	B-General_Concept
"	O
copying	O
or	O
moving	O
of	O
data	O
within	O
memory	B-General_Concept
.	O
</s>
<s>
DMA	O
can	O
offload	O
expensive	O
memory	B-General_Concept
operations	O
,	O
such	O
as	O
large	O
copies	O
or	O
scatter-gather	B-General_Concept
operations	O
,	O
from	O
the	O
CPU	B-General_Concept
to	O
a	O
dedicated	O
DMA	B-General_Concept
engine	I-General_Concept
.	O
</s>
<s>
An	O
implementation	O
example	O
is	O
the	O
I/O	B-Device
Acceleration	I-Device
Technology	I-Device
.	O
</s>
<s>
DMA	O
is	O
of	O
interest	O
in	O
network-on-chip	B-Architecture
and	O
in-memory	B-General_Concept
computing	I-General_Concept
architectures	O
.	O
</s>
<s>
Standard	O
DMA	O
,	O
also	O
called	O
third-party	O
DMA	O
,	O
uses	O
a	O
DMA	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
A	O
DMA	B-General_Concept
controller	I-General_Concept
can	O
generate	O
memory	B-General_Concept
addresses	O
and	O
initiate	O
memory	B-General_Concept
read	O
or	O
write	O
cycles	O
.	O
</s>
<s>
It	O
contains	O
several	O
hardware	B-General_Concept
registers	I-General_Concept
that	O
can	O
be	O
written	O
and	O
read	O
by	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
These	O
include	O
a	O
memory	B-General_Concept
address	I-General_Concept
register	O
,	O
a	O
byte	O
count	O
register	O
,	O
and	O
one	O
or	O
more	O
control	O
registers	O
.	O
</s>
<s>
Depending	O
on	O
what	O
features	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
provides	O
,	O
these	O
control	O
registers	O
might	O
specify	O
some	O
combination	O
of	O
the	O
source	O
,	O
the	O
destination	O
,	O
the	O
direction	O
of	O
the	O
transfer	O
(	O
reading	O
from	O
the	O
I/O	B-General_Concept
device	I-General_Concept
or	O
writing	O
to	O
the	O
I/O	B-General_Concept
device	I-General_Concept
)	O
,	O
the	O
size	O
of	O
the	O
transfer	O
unit	O
,	O
and/or	O
the	O
number	O
of	O
bytes	O
to	O
transfer	O
in	O
one	O
burst	O
.	O
</s>
<s>
To	O
carry	O
out	O
an	O
input	O
,	O
output	O
or	O
memory-to-memory	O
operation	O
,	O
the	O
host	O
processor	O
initializes	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
with	O
a	O
count	O
of	O
the	O
number	O
of	O
words	O
to	O
transfer	O
,	O
and	O
the	O
memory	B-General_Concept
address	I-General_Concept
to	O
use	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
then	O
commands	O
the	O
peripheral	O
device	O
to	O
initiate	O
a	O
data	O
transfer	O
.	O
</s>
<s>
The	O
DMA	B-General_Concept
controller	I-General_Concept
then	O
provides	O
addresses	O
and	O
read/write	O
control	O
lines	O
to	O
the	O
system	O
memory	B-General_Concept
.	O
</s>
<s>
Each	O
time	O
a	O
byte	O
of	O
data	O
is	O
ready	O
to	O
be	O
transferred	O
between	O
the	O
peripheral	O
device	O
and	O
memory	B-General_Concept
,	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
increments	O
its	O
internal	O
address	O
register	O
until	O
the	O
full	O
block	O
of	O
data	O
is	O
transferred	O
.	O
</s>
<s>
In	O
a	O
bus	B-Architecture
mastering	I-Architecture
system	O
,	O
also	O
known	O
as	O
a	O
first-party	B-Architecture
DMA	I-Architecture
system	O
,	O
the	O
CPU	B-General_Concept
and	O
peripherals	O
can	O
each	O
be	O
granted	O
control	O
of	O
the	O
memory	B-General_Concept
bus	O
.	O
</s>
<s>
Where	O
a	O
peripheral	O
can	O
become	O
a	O
bus	B-Architecture
master	I-Architecture
,	O
it	O
can	O
directly	O
write	O
to	O
system	O
memory	B-General_Concept
without	O
the	O
involvement	O
of	O
the	O
CPU	B-General_Concept
,	O
providing	O
memory	B-General_Concept
address	I-General_Concept
and	O
control	O
signals	O
as	O
required	O
.	O
</s>
<s>
In	O
burst	B-Architecture
mode	I-Architecture
,	O
an	O
entire	O
block	O
of	O
data	O
is	O
transferred	O
in	O
one	O
contiguous	O
sequence	O
.	O
</s>
<s>
Once	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
is	O
granted	O
access	O
to	O
the	O
system	O
bus	O
by	O
the	O
CPU	B-General_Concept
,	O
it	O
transfers	O
all	O
bytes	O
of	O
data	O
in	O
the	O
data	O
block	O
before	O
releasing	O
control	O
of	O
the	O
system	O
buses	O
back	O
to	O
the	O
CPU	B-General_Concept
,	O
but	O
renders	O
the	O
CPU	B-General_Concept
inactive	O
for	O
relatively	O
long	O
periods	O
of	O
time	O
.	O
</s>
<s>
The	O
cycle	B-General_Concept
stealing	I-General_Concept
mode	O
is	O
used	O
in	O
systems	O
in	O
which	O
the	O
CPU	B-General_Concept
should	O
not	O
be	O
disabled	O
for	O
the	O
length	O
of	O
time	O
needed	O
for	O
burst	B-Architecture
transfer	I-Architecture
modes	O
.	O
</s>
<s>
In	O
the	O
cycle	B-General_Concept
stealing	I-General_Concept
mode	O
,	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
obtains	O
access	O
to	O
the	O
system	O
bus	O
the	O
same	O
way	O
as	O
in	O
burst	B-Architecture
mode	I-Architecture
,	O
using	O
BR	O
(	O
Bus	O
Request	O
)	O
and	O
BG	O
(	O
Bus	O
Grant	O
)	O
signals	O
,	O
which	O
are	O
the	O
two	O
signals	O
controlling	O
the	O
interface	O
between	O
the	O
CPU	B-General_Concept
and	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
However	O
,	O
in	O
cycle	B-General_Concept
stealing	I-General_Concept
mode	O
,	O
after	O
one	O
unit	O
(	O
e.g.	O
</s>
<s>
byte	O
)	O
of	O
data	O
transfer	O
,	O
the	O
control	O
of	O
the	O
system	O
bus	O
is	O
deasserted	O
to	O
the	O
CPU	B-General_Concept
via	O
BG	O
.	O
</s>
<s>
By	O
continually	O
obtaining	O
and	O
releasing	O
the	O
control	O
of	O
the	O
system	O
bus	O
,	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
essentially	O
interleaves	O
instruction	O
and	O
data	O
transfers	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
processes	O
an	O
instruction	O
,	O
then	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
transfers	O
one	O
data	O
value	O
,	O
and	O
so	O
on	O
.	O
</s>
<s>
Data	O
is	O
not	O
transferred	O
as	O
quickly	O
,	O
but	O
CPU	B-General_Concept
is	O
not	O
idled	O
for	O
as	O
long	O
as	O
in	O
burst	B-Architecture
mode	I-Architecture
.	O
</s>
<s>
Cycle	B-General_Concept
stealing	I-General_Concept
mode	O
is	O
useful	O
for	O
controllers	O
that	O
monitor	O
data	O
in	O
real	O
time	O
.	O
</s>
<s>
In	O
transparent	O
mode	O
,	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
transfers	O
data	O
only	O
when	O
the	O
CPU	B-General_Concept
is	O
performing	O
operations	O
that	O
do	O
not	O
use	O
the	O
system	O
buses	O
.	O
</s>
<s>
The	O
primary	O
advantage	O
of	O
transparent	O
mode	O
is	O
that	O
the	O
CPU	B-General_Concept
never	O
stops	O
executing	O
its	O
programs	O
and	O
the	O
DMA	O
transfer	O
is	O
free	O
in	O
terms	O
of	O
time	O
,	O
while	O
the	O
disadvantage	O
is	O
that	O
the	O
hardware	O
needs	O
to	O
determine	O
when	O
the	O
CPU	B-General_Concept
is	O
not	O
using	O
the	O
system	O
buses	O
,	O
which	O
can	O
be	O
complex	O
.	O
</s>
<s>
DMA	O
can	O
lead	O
to	O
cache	B-General_Concept
coherency	I-General_Concept
problems	O
.	O
</s>
<s>
Imagine	O
a	O
CPU	B-General_Concept
equipped	O
with	O
a	O
cache	O
and	O
an	O
external	O
memory	B-General_Concept
that	O
can	O
be	O
accessed	O
directly	O
by	O
devices	O
using	O
DMA	O
.	O
</s>
<s>
When	O
the	O
CPU	B-General_Concept
accesses	O
location	O
X	O
in	O
the	O
memory	B-General_Concept
,	O
the	O
current	O
value	O
will	O
be	O
stored	O
in	O
the	O
cache	O
.	O
</s>
<s>
Subsequent	O
operations	O
on	O
X	O
will	O
update	O
the	O
cached	O
copy	O
of	O
X	O
,	O
but	O
not	O
the	O
external	O
memory	B-General_Concept
version	O
of	O
X	O
,	O
assuming	O
a	O
write-back	O
cache	O
.	O
</s>
<s>
If	O
the	O
cache	O
is	O
not	O
flushed	O
to	O
the	O
memory	B-General_Concept
before	O
the	O
next	O
time	O
a	O
device	O
tries	O
to	O
access	O
X	O
,	O
the	O
device	O
will	O
receive	O
a	O
stale	O
value	O
of	O
X	O
.	O
</s>
<s>
Similarly	O
,	O
if	O
the	O
cached	O
copy	O
of	O
X	O
is	O
not	O
invalidated	O
when	O
a	O
device	O
writes	O
a	O
new	O
value	O
to	O
the	O
memory	B-General_Concept
,	O
then	O
the	O
CPU	B-General_Concept
will	O
operate	O
on	O
a	O
stale	O
value	O
of	O
X	O
.	O
</s>
<s>
This	O
issue	O
can	O
be	O
addressed	O
in	O
one	O
of	O
two	O
ways	O
in	O
system	O
design	O
:	O
Cache-coherent	O
systems	O
implement	O
a	O
method	O
in	O
hardware	O
,	O
called	O
bus	B-General_Concept
snooping	I-General_Concept
,	O
whereby	O
external	O
writes	O
are	O
signaled	O
to	O
the	O
cache	O
controller	O
which	O
then	O
performs	O
a	O
cache	B-General_Concept
invalidation	I-General_Concept
for	O
DMA	O
writes	O
or	O
cache	B-General_Concept
flush	I-General_Concept
for	O
DMA	O
reads	O
.	O
</s>
<s>
Non-coherent	O
systems	O
leave	O
this	O
to	O
software	O
,	O
where	O
the	O
OS	O
must	O
then	O
ensure	O
that	O
the	O
cache	O
lines	O
are	O
flushed	O
before	O
an	O
outgoing	O
DMA	O
transfer	O
is	O
started	O
and	O
invalidated	O
before	O
a	O
memory	B-General_Concept
range	O
affected	O
by	O
an	O
incoming	O
DMA	O
transfer	O
is	O
accessed	O
.	O
</s>
<s>
The	O
OS	O
must	O
make	O
sure	O
that	O
the	O
memory	B-General_Concept
range	O
is	O
not	O
accessed	O
by	O
any	O
running	O
threads	O
in	O
the	O
meantime	O
.	O
</s>
<s>
Hybrids	O
also	O
exist	O
,	O
where	O
the	O
secondary	O
L2	O
cache	O
is	O
coherent	O
while	O
the	O
L1	O
cache	O
(	O
typically	O
on-CPU	O
)	O
is	O
managed	O
by	O
software	O
.	O
</s>
<s>
In	O
the	O
original	O
IBM	B-Device
PC	I-Device
(	O
and	O
the	O
follow-up	O
PC/XT	B-Device
)	O
,	O
there	O
was	O
only	O
one	O
Intel	B-Device
8237	I-Device
DMA	B-General_Concept
controller	I-General_Concept
capable	O
of	O
providing	O
four	O
DMA	O
channels	O
(	O
numbered	O
0	O
–	O
3	O
)	O
.	O
</s>
<s>
These	O
DMA	O
channels	O
performed	O
8-bit	O
transfers	O
(	O
as	O
the	O
8237	B-Device
was	O
an	O
8-bit	O
device	O
,	O
ideally	O
matched	O
to	O
the	O
PC	O
's	O
i8088	B-Device
CPU/bus	O
architecture	O
)	O
,	O
could	O
only	O
address	O
the	O
first	O
(	O
i8086/8088	O
-standard	O
)	O
megabyte	O
of	O
RAM	B-Architecture
,	O
and	O
were	O
limited	O
to	O
addressing	O
single	O
64kB	O
segments	O
within	O
that	O
space	O
(	O
although	O
the	O
source	O
and	O
destination	O
channels	O
could	O
address	O
different	O
segments	O
)	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
controller	O
could	O
only	O
be	O
used	O
for	O
transfers	O
to	O
,	O
from	O
or	O
between	O
expansion	O
bus	O
I/O	B-General_Concept
devices	I-General_Concept
,	O
as	O
the	O
8237	B-Device
could	O
only	O
perform	O
memory-to-memory	O
transfers	O
using	O
channels	O
0	O
&	O
1	O
,	O
of	O
which	O
channel	O
0	O
in	O
the	O
PC	O
( &	O
XT	O
)	O
was	O
dedicated	O
to	O
dynamic	B-General_Concept
memory	I-General_Concept
refresh	B-General_Concept
.	O
</s>
<s>
This	O
prevented	O
it	O
from	O
being	O
used	O
as	O
a	O
general-purpose	O
"	O
Blitter	B-General_Concept
"	O
,	O
and	O
consequently	O
block	O
memory	B-General_Concept
moves	O
in	O
the	O
PC	O
,	O
limited	O
by	O
the	O
general	O
PIO	B-General_Concept
speed	O
of	O
the	O
CPU	B-General_Concept
,	O
were	O
very	O
slow	O
.	O
</s>
<s>
With	O
the	O
IBM	B-Operating_System
PC/AT	I-Operating_System
,	O
the	O
enhanced	O
AT	B-Architecture
Bus	I-Architecture
(	O
more	O
familiarly	O
retronymed	O
as	O
the	O
ISA	B-Architecture
,	O
or	O
"	O
Industry	B-Architecture
Standard	I-Architecture
Architecture	I-Architecture
"	O
)	O
added	O
a	O
second	O
8237	B-Device
DMA	B-General_Concept
controller	I-General_Concept
to	O
provide	O
three	O
additional	O
,	O
and	O
as	O
highlighted	O
by	O
resource	O
clashes	O
with	O
the	O
XT	O
's	O
additional	O
expandability	O
over	O
the	O
original	O
PC	O
,	O
much-needed	O
channels	O
(	O
5	O
–	O
7	O
;	O
channel	O
4	O
is	O
used	O
as	O
a	O
cascade	O
to	O
the	O
first	O
8237	B-Device
)	O
.	O
</s>
<s>
The	O
page	O
register	O
was	O
also	O
rewired	O
to	O
address	O
the	O
full	O
16	O
MB	O
memory	B-General_Concept
address	I-General_Concept
space	O
of	O
the	O
80286	B-General_Concept
CPU	B-General_Concept
.	O
</s>
<s>
This	O
second	O
controller	O
was	O
also	O
integrated	O
in	O
a	O
way	O
capable	O
of	O
performing	O
16-bit	O
transfers	O
when	O
an	O
I/O	B-General_Concept
device	I-General_Concept
is	O
used	O
as	O
the	O
data	O
source	O
and/or	O
destination	O
(	O
as	O
it	O
actually	O
only	O
processes	O
data	O
itself	O
for	O
memory-to-memory	O
transfers	O
,	O
otherwise	O
simply	O
controlling	O
the	O
data	O
flow	O
between	O
other	O
parts	O
of	O
the	O
16-bit	O
system	O
,	O
making	O
its	O
own	O
data	O
bus	O
width	O
relatively	O
immaterial	O
)	O
,	O
doubling	O
data	O
throughput	O
when	O
the	O
upper	O
three	O
channels	O
are	O
used	O
.	O
</s>
<s>
For	O
compatibility	O
,	O
the	O
lower	O
four	O
DMA	O
channels	O
were	O
still	O
limited	O
to	O
8-bit	O
transfers	O
only	O
,	O
and	O
whilst	O
memory-to-memory	O
transfers	O
were	O
now	O
technically	O
possible	O
due	O
to	O
the	O
freeing	O
up	O
of	O
channel	O
0	O
from	O
having	O
to	O
handle	O
DRAM	B-General_Concept
refresh	I-General_Concept
,	O
from	O
a	O
practical	O
standpoint	O
they	O
were	O
of	O
limited	O
value	O
because	O
of	O
the	O
controller	O
's	O
consequent	O
low	O
throughput	O
compared	O
to	O
what	O
the	O
CPU	B-General_Concept
could	O
now	O
achieve	O
(	O
i.e.	O
,	O
a	O
16-bit	O
,	O
more	O
optimised	O
80286	B-General_Concept
running	O
at	O
a	O
minimum	O
of	O
6MHz	O
,	O
vs	O
an	O
8-bit	O
controller	O
locked	O
at	O
4.77MHz	O
)	O
.	O
</s>
<s>
In	O
both	O
cases	O
,	O
the	O
64kB	O
segment	B-Device
boundary	I-Device
issue	O
remained	O
,	O
with	O
individual	O
transfers	O
unable	O
to	O
cross	O
segments	O
(	O
instead	O
"	O
wrapping	O
around	O
"	O
to	O
the	O
start	O
of	O
the	O
same	O
segment	O
)	O
even	O
in	O
16-bit	O
mode	O
,	O
although	O
this	O
was	O
in	O
practice	O
more	O
a	O
problem	O
of	O
programming	O
complexity	O
than	O
performance	O
as	O
the	O
continued	O
need	O
for	O
DRAM	B-General_Concept
refresh	I-General_Concept
(	O
however	O
handled	O
)	O
to	O
monopolise	O
the	O
bus	O
approximately	O
every	O
15μs	O
prevented	O
use	O
of	O
large	O
(	O
and	O
fast	O
,	O
but	O
uninterruptible	O
)	O
block	O
transfers	O
.	O
</s>
<s>
Due	O
to	O
their	O
lagging	O
performance	O
(	O
1.6MB/s	O
maximum	O
8-bit	O
transfer	O
capability	O
at	O
5MHz	O
,	O
but	O
no	O
more	O
than	O
0.9MB/s	O
in	O
the	O
PC/XT	B-Device
and	O
1.6MB/s	O
for	O
16-bit	O
transfers	O
in	O
the	O
AT	O
due	O
to	O
ISA	B-Architecture
bus	I-Architecture
overheads	O
and	O
other	O
interference	O
such	O
as	O
memory	B-General_Concept
refresh	I-General_Concept
interruptions	O
)	O
and	O
unavailability	O
of	O
any	O
speed	O
grades	O
that	O
would	O
allow	O
installation	O
of	O
direct	O
replacements	O
operating	O
at	O
speeds	O
higher	O
than	O
the	O
original	O
PC	O
's	O
standard	O
4.77MHz	O
clock	O
,	O
these	O
devices	O
have	O
been	O
effectively	O
obsolete	O
since	O
the	O
late	O
1980s	O
.	O
</s>
<s>
Particularly	O
,	O
the	O
advent	O
of	O
the	O
80386	B-General_Concept
processor	O
in	O
1985	O
and	O
its	O
capacity	O
for	O
32-bit	O
transfers	O
(	O
although	O
great	O
improvements	O
in	O
the	O
efficiency	O
of	O
address	O
calculation	O
and	O
block	O
memory	B-General_Concept
moves	O
in	O
Intel	O
CPUs	O
after	O
the	O
80186	B-Device
meant	O
that	O
PIO	B-General_Concept
transfers	O
even	O
by	O
the	O
16-bit-bus	O
286	B-General_Concept
and	O
386SX	O
could	O
still	O
easily	O
outstrip	O
the	O
8237	B-Device
)	O
,	O
as	O
well	O
as	O
the	O
development	O
of	O
further	O
evolutions	O
to	O
(	O
EISA	B-Device
)	O
or	O
replacements	O
for	O
(	O
MCA	B-Device
,	O
VLB	O
and	O
PCI	B-Protocol
)	O
the	O
"	O
ISA	B-Architecture
"	O
bus	O
with	O
their	O
own	O
much	O
higher-performance	O
DMA	O
subsystems	O
(	O
up	O
to	O
a	O
maximum	O
of	O
33MB/s	O
for	O
EISA	B-Device
,	O
40MB/s	O
MCA	B-Device
,	O
typically	O
133MB/s	O
VLB/PCI	O
)	O
made	O
the	O
original	O
DMA	B-General_Concept
controllers	I-General_Concept
seem	O
more	O
of	O
a	O
performance	O
millstone	O
than	O
a	O
booster	O
.	O
</s>
<s>
The	O
pieces	O
of	O
legacy	O
hardware	O
that	O
continued	O
to	O
use	O
ISA	B-Architecture
DMA	O
after	O
32-bit	O
expansion	O
buses	O
became	O
common	O
were	O
Sound	B-Application
Blaster	I-Application
cards	I-Application
that	O
needed	O
to	O
maintain	O
full	O
hardware	O
compatibility	O
with	O
the	O
Sound	B-Application
Blaster	I-Application
standard	O
;	O
and	O
Super	B-Device
I/O	I-Device
devices	O
on	O
motherboards	B-Device
that	O
often	O
integrated	O
a	O
built-in	O
floppy	B-Device
disk	I-Device
controller	O
,	O
an	O
IrDA	O
infrared	O
controller	O
when	O
FIR	O
(	O
fast	O
infrared	O
)	O
mode	O
is	O
selected	O
,	O
and	O
an	O
IEEE	B-Device
1284	I-Device
parallel	O
port	O
controller	O
when	O
ECP	O
mode	O
is	O
selected	O
.	O
</s>
<s>
In	O
cases	O
where	O
an	O
original	O
8237s	B-Device
or	O
direct	O
compatibles	O
were	O
still	O
used	O
,	O
transfer	O
to	O
or	O
from	O
these	O
devices	O
may	O
still	O
be	O
limited	O
to	O
the	O
first	O
16MB	O
of	O
main	O
RAM	B-Architecture
regardless	O
of	O
the	O
system	O
's	O
actual	O
address	O
space	O
or	O
amount	O
of	O
installed	O
memory	B-General_Concept
.	O
</s>
<s>
When	O
the	O
transfer	O
is	O
complete	O
,	O
the	O
device	O
interrupts	B-Application
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Scatter-gather	B-General_Concept
or	O
vectored	B-General_Concept
I/O	I-General_Concept
DMA	O
allows	O
the	O
transfer	O
of	O
data	O
to	O
and	O
from	O
multiple	O
memory	B-General_Concept
areas	O
in	O
a	O
single	O
DMA	O
transaction	O
.	O
</s>
<s>
It	O
is	O
equivalent	O
to	O
the	O
chaining	O
together	O
of	O
multiple	O
simple	O
DMA	B-General_Concept
requests	I-General_Concept
.	O
</s>
<s>
The	O
motivation	O
is	O
to	O
off-load	O
multiple	O
input/output	B-General_Concept
interrupt	B-Application
and	O
data	O
copy	O
tasks	O
from	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
DRQ	B-General_Concept
stands	O
for	O
Data	O
request	O
;	O
DACK	O
for	O
Data	O
acknowledge	O
.	O
</s>
<s>
These	O
symbols	O
,	O
seen	O
on	O
hardware	O
schematics	B-Application
of	O
computer	O
systems	O
with	O
DMA	O
functionality	O
,	O
represent	O
electronic	O
signaling	O
lines	O
between	O
the	O
CPU	B-General_Concept
and	O
DMA	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
16-bit	O
ISA	B-Architecture
permitted	O
bus	B-Architecture
mastering	I-Architecture
.	O
</s>
<s>
Standard	O
ISA	B-Architecture
DMA	O
assignments	O
:	O
</s>
<s>
A	O
PCI	B-Protocol
architecture	O
has	O
no	O
central	O
DMA	B-General_Concept
controller	I-General_Concept
,	O
unlike	O
ISA	B-Architecture
.	O
</s>
<s>
Instead	O
,	O
A	O
PCI	B-Protocol
device	O
can	O
request	O
control	O
of	O
the	O
bus	O
(	O
"	O
become	O
the	O
bus	B-Architecture
master	I-Architecture
"	O
)	O
and	O
request	O
to	O
read	O
from	O
and	O
write	O
to	O
system	O
memory	B-General_Concept
.	O
</s>
<s>
More	O
precisely	O
,	O
a	O
PCI	B-Protocol
component	O
requests	O
bus	O
ownership	O
from	O
the	O
PCI	B-Protocol
bus	I-Protocol
controller	O
(	O
usually	O
PCI	B-Protocol
host	O
bridge	O
,	O
and	O
PCI	B-Protocol
to	O
PCI	B-Protocol
bridge	I-Protocol
)	O
,	O
which	O
will	O
arbitrate	O
if	O
several	O
devices	O
request	O
bus	O
ownership	O
simultaneously	O
,	O
since	O
there	O
can	O
only	O
be	O
one	O
bus	B-Architecture
master	I-Architecture
at	O
one	O
time	O
.	O
</s>
<s>
When	O
the	O
component	O
is	O
granted	O
ownership	O
,	O
it	O
will	O
issue	O
normal	O
read	O
and	O
write	O
commands	O
on	O
the	O
PCI	B-Protocol
bus	I-Protocol
,	O
which	O
will	O
be	O
claimed	O
by	O
the	O
PCI	B-Protocol
bus	I-Protocol
controller	O
.	O
</s>
<s>
As	O
an	O
example	O
,	O
on	O
an	O
Intel	O
Core-based	O
PC	O
,	O
the	O
southbridge	O
will	O
forward	O
the	O
transactions	O
to	O
the	O
memory	B-General_Concept
controller	I-General_Concept
(	O
which	O
is	O
integrated	O
on	O
the	O
CPU	B-General_Concept
die	O
)	O
using	O
DMI	B-Architecture
,	O
which	O
will	O
in	O
turn	O
convert	O
them	O
to	O
DDR	O
operations	O
and	O
send	O
them	O
out	O
on	O
the	O
memory	B-General_Concept
bus	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
there	O
are	O
quite	O
a	O
number	O
of	O
steps	O
involved	O
in	O
a	O
PCI	B-Protocol
DMA	O
transfer	O
;	O
however	O
,	O
that	O
poses	O
little	O
problem	O
,	O
since	O
the	O
PCI	B-Protocol
device	O
or	O
PCI	B-Protocol
bus	I-Protocol
itself	O
are	O
an	O
order	O
of	O
magnitude	O
slower	O
than	O
the	O
rest	O
of	O
the	O
components	O
(	O
see	O
list	B-Device
of	I-Device
device	I-Device
bandwidths	I-Device
)	O
.	O
</s>
<s>
A	O
modern	O
x86	O
CPU	B-General_Concept
may	O
use	O
more	O
than	O
4	O
GB	O
of	O
memory	B-General_Concept
,	O
either	O
utilizing	O
the	O
native	O
64-bit	O
mode	O
of	O
x86-64	B-Device
CPU	B-General_Concept
,	O
or	O
the	O
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
(	O
PAE	O
)	O
,	O
a	O
36-bit	O
addressing	O
mode	O
.	O
</s>
<s>
In	O
such	O
a	O
case	O
,	O
a	O
device	O
using	O
DMA	O
with	O
a	O
32-bit	O
address	O
bus	O
is	O
unable	O
to	O
address	B-General_Concept
memory	I-General_Concept
above	O
the	O
4	O
GB	O
line	O
.	O
</s>
<s>
The	O
new	O
Double	O
Address	O
Cycle	O
(	O
DAC	O
)	O
mechanism	O
,	O
if	O
implemented	O
on	O
both	O
the	O
PCI	B-Protocol
bus	I-Protocol
and	O
the	O
device	O
itself	O
,	O
enables	O
64-bit	O
DMA	O
addressing	O
.	O
</s>
<s>
Otherwise	O
,	O
the	O
operating	O
system	O
would	O
need	O
to	O
work	O
around	O
the	O
problem	O
by	O
either	O
using	O
costly	O
double	O
buffers	O
(	O
DOS/Windows	O
nomenclature	O
)	O
also	O
known	O
as	O
bounce	O
buffers	O
(	O
FreeBSD/Linux	O
)	O
,	O
or	O
it	O
could	O
use	O
an	O
IOMMU	B-General_Concept
to	O
provide	O
address	O
translation	O
services	O
if	O
one	O
is	O
present	O
.	O
</s>
<s>
As	O
an	O
example	O
of	O
DMA	B-General_Concept
engine	I-General_Concept
incorporated	O
in	O
a	O
general-purpose	O
CPU	B-General_Concept
,	O
some	O
Intel	B-Device
Xeon	I-Device
chipsets	O
include	O
a	O
DMA	B-General_Concept
engine	I-General_Concept
called	O
I/O	B-Device
Acceleration	I-Device
Technology	I-Device
(	O
I/OAT	B-Device
)	O
,	O
which	O
can	O
offload	O
memory	B-General_Concept
copying	O
from	O
the	O
main	O
CPU	B-General_Concept
,	O
freeing	O
it	O
to	O
do	O
other	O
work	O
.	O
</s>
<s>
In	O
2006	O
,	O
Intel	O
's	O
Linux	B-Operating_System
kernel	I-Operating_System
developer	O
Andrew	O
Grover	O
performed	O
benchmarks	O
using	O
I/OAT	B-Device
to	O
offload	O
network	O
traffic	O
copies	O
and	O
found	O
no	O
more	O
than	O
10%	O
improvement	O
in	O
CPU	B-General_Concept
utilization	O
with	O
receiving	O
workloads	O
.	O
</s>
<s>
Further	O
performance-oriented	O
enhancements	O
to	O
the	O
DMA	O
mechanism	O
have	O
been	O
introduced	O
in	O
Intel	B-Device
Xeon	I-Device
E5	O
processors	O
with	O
their	O
Data	O
Direct	O
I/O	B-General_Concept
(	O
DDIO	O
)	O
feature	O
,	O
allowing	O
the	O
DMA	O
"	O
windows	O
"	O
to	O
reside	O
within	O
CPU	B-General_Concept
caches	I-General_Concept
instead	O
of	O
system	O
RAM	B-Architecture
.	O
</s>
<s>
As	O
a	O
result	O
,	O
CPU	B-General_Concept
caches	I-General_Concept
are	O
used	O
as	O
the	O
primary	O
source	O
and	O
destination	O
for	O
I/O	B-General_Concept
,	O
allowing	O
network	B-Protocol
interface	I-Protocol
controllers	I-Protocol
(	O
NICs	O
)	O
to	O
DMA	O
directly	O
to	O
the	O
Last	O
level	O
cache	O
(	O
L3	O
cache	O
)	O
of	O
local	O
CPUs	O
and	O
avoid	O
costly	O
fetching	O
of	O
the	O
I/O	B-General_Concept
data	O
from	O
system	O
RAM	B-Architecture
.	O
</s>
<s>
As	O
a	O
result	O
,	O
DDIO	O
reduces	O
the	O
overall	O
I/O	B-General_Concept
processing	O
latency	O
,	O
allows	O
processing	O
of	O
the	O
I/O	B-General_Concept
to	O
be	O
performed	O
entirely	O
in-cache	O
,	O
prevents	O
the	O
available	O
RAM	B-Architecture
bandwidth/latency	O
from	O
becoming	O
a	O
performance	O
bottleneck	O
,	O
and	O
may	O
lower	O
the	O
power	O
consumption	O
by	O
allowing	O
RAM	B-Architecture
to	O
remain	O
longer	O
in	O
low-powered	O
state	O
.	O
</s>
<s>
In	O
systems-on-a-chip	B-Architecture
and	O
embedded	B-Architecture
systems	I-Architecture
,	O
typical	O
system	O
bus	O
infrastructure	O
is	O
a	O
complex	O
on-chip	O
bus	O
such	O
as	O
AMBA	O
High-performance	O
Bus	O
.	O
</s>
<s>
A	O
slave	O
interface	O
is	O
similar	O
to	O
programmed	B-General_Concept
I/O	I-General_Concept
through	O
which	O
the	O
software	O
(	O
running	O
on	O
embedded	O
CPU	B-General_Concept
,	O
e.g.	O
</s>
<s>
ARM	B-Architecture
)	O
can	O
write/read	O
I/O	B-General_Concept
registers	O
or	O
(	O
less	O
commonly	O
)	O
local	O
memory	B-General_Concept
blocks	O
inside	O
the	O
device	O
.	O
</s>
<s>
A	O
master	O
interface	O
can	O
be	O
used	O
by	O
the	O
device	O
to	O
perform	O
DMA	O
transactions	O
to/from	O
system	O
memory	B-General_Concept
without	O
heavily	O
loading	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
high	O
bandwidth	O
devices	O
such	O
as	O
network	B-Protocol
controllers	I-Protocol
that	O
need	O
to	O
transfer	O
huge	O
amounts	O
of	O
data	O
to/from	O
system	O
memory	B-General_Concept
will	O
have	O
two	O
interface	O
adapters	O
to	O
the	O
AHB	O
:	O
a	O
master	O
and	O
a	O
slave	O
interface	O
.	O
</s>
<s>
This	O
is	O
because	O
on-chip	O
buses	O
like	O
AHB	O
do	O
not	O
support	O
tri-stating	B-Device
the	O
bus	O
or	O
alternating	O
the	O
direction	O
of	O
any	O
line	O
on	O
the	O
bus	O
.	O
</s>
<s>
Like	O
PCI	B-Protocol
,	O
no	O
central	O
DMA	B-General_Concept
controller	I-General_Concept
is	O
required	O
since	O
the	O
DMA	O
is	O
bus-mastering	O
,	O
but	O
an	O
arbiter	O
is	O
required	O
in	O
case	O
of	O
multiple	O
masters	O
present	O
on	O
the	O
system	O
.	O
</s>
<s>
Internally	O
,	O
a	O
multichannel	O
DMA	B-General_Concept
engine	I-General_Concept
is	O
usually	O
present	O
in	O
the	O
device	O
to	O
perform	O
multiple	O
concurrent	O
scatter-gather	B-General_Concept
operations	O
as	O
programmed	O
by	O
the	O
software	O
.	O
</s>
<s>
As	O
an	O
example	O
usage	O
of	O
DMA	O
in	O
a	O
multiprocessor-system-on-chip	B-General_Concept
,	O
IBM/Sony/Toshiba	O
'	O
s	O
Cell	B-General_Concept
processor	I-General_Concept
incorporates	O
a	O
DMA	B-General_Concept
engine	I-General_Concept
for	O
each	O
of	O
its	O
9	O
processing	O
elements	O
including	O
one	O
Power	O
processor	O
element	O
(	O
PPE	O
)	O
and	O
eight	O
synergistic	O
processor	O
elements	O
(	O
SPEs	O
)	O
.	O
</s>
<s>
Since	O
the	O
SPE	O
's	O
load/store	O
instructions	O
can	O
read/write	O
only	O
its	O
own	O
local	O
memory	B-General_Concept
,	O
an	O
SPE	O
entirely	O
depends	O
on	O
DMAs	O
to	O
transfer	O
data	O
to	O
and	O
from	O
the	O
main	O
memory	B-General_Concept
and	O
local	O
memories	O
of	O
other	O
SPEs	O
.	O
</s>
<s>
Thus	O
the	O
DMA	O
acts	O
as	O
a	O
primary	O
means	O
of	O
data	O
transfer	O
among	O
cores	O
inside	O
this	O
CPU	B-General_Concept
(	O
in	O
contrast	O
to	O
cache-coherent	O
CMP	O
architectures	O
such	O
as	O
Intel	O
's	O
cancelled	O
general-purpose	B-Architecture
GPU	I-Architecture
,	O
Larrabee	B-Architecture
)	O
.	O
</s>
<s>
DMA	O
in	O
Cell	B-General_Concept
is	O
fully	O
cache	O
coherent	O
(	O
note	O
however	O
local	O
stores	O
of	O
SPEs	O
operated	O
upon	O
by	O
DMA	O
do	O
not	O
act	O
as	O
globally	O
coherent	B-General_Concept
cache	I-General_Concept
in	O
the	O
standard	B-General_Concept
sense	I-General_Concept
)	O
.	O
</s>
<s>
The	O
DMA	O
command	O
is	O
issued	O
by	O
specifying	O
a	O
pair	O
of	O
a	O
local	O
address	O
and	O
a	O
remote	O
address	O
:	O
for	O
example	O
when	O
a	O
SPE	O
program	O
issues	O
a	O
put	O
DMA	O
command	O
,	O
it	O
specifies	O
an	O
address	O
of	O
its	O
own	O
local	O
memory	B-General_Concept
as	O
the	O
source	O
and	O
a	O
virtual	O
memory	B-General_Concept
address	I-General_Concept
(	O
pointing	O
to	O
either	O
the	O
main	O
memory	B-General_Concept
or	O
the	O
local	O
memory	B-General_Concept
of	O
another	O
SPE	O
)	O
as	O
the	O
target	O
,	O
together	O
with	O
a	O
block	O
size	O
.	O
</s>
<s>
According	O
to	O
an	O
experiment	O
,	O
an	O
effective	O
peak	O
performance	O
of	O
DMA	O
in	O
Cell	B-General_Concept
(	O
3GHz	O
,	O
under	O
uniform	O
traffic	O
)	O
reaches	O
200	O
GB	O
per	O
second	O
.	O
</s>
<s>
Processors	O
with	O
scratchpad	B-General_Concept
memory	I-General_Concept
and	O
DMA	O
(	O
such	O
as	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
and	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
)	O
may	O
benefit	O
from	O
software	O
overlapping	O
DMA	O
memory	B-General_Concept
operations	O
with	O
processing	O
,	O
via	O
double	O
buffering	O
or	O
multibuffering	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
on-chip	O
memory	B-General_Concept
is	O
split	O
into	O
two	O
buffers	O
;	O
the	O
processor	O
may	O
be	O
operating	O
on	O
data	O
in	O
one	O
,	O
while	O
the	O
DMA	B-General_Concept
engine	I-General_Concept
is	O
loading	O
and	O
storing	O
data	O
in	O
the	O
other	O
.	O
</s>
<s>
This	O
allows	O
the	O
system	O
to	O
avoid	O
memory	B-General_Concept
latency	I-General_Concept
and	O
exploit	O
burst	B-Architecture
transfers	I-Architecture
,	O
at	O
the	O
expense	O
of	O
needing	O
a	O
predictable	O
memory	B-General_Concept
access	O
pattern	O
.	O
</s>
