<s>
In	O
computing	O
,	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	O
)	O
is	O
Intel	O
's	O
proprietary	O
link	O
between	O
the	O
northbridge	B-Device
and	O
southbridge	B-Device
on	O
a	O
computer	B-Device
motherboard	I-Device
.	O
</s>
<s>
It	O
was	O
first	O
used	O
between	O
the	O
9xx	O
chipsets	O
and	O
the	O
ICH6	B-Device
,	O
released	O
in	O
2004	O
.	O
</s>
<s>
Previous	O
Intel	O
chipsets	O
had	O
used	O
the	O
Intel	B-Architecture
Hub	I-Architecture
Architecture	I-Architecture
to	O
perform	O
the	O
same	O
function	O
,	O
and	O
server	O
chipsets	O
use	O
a	O
similar	O
interface	O
called	O
Enterprise	B-Architecture
Southbridge	I-Architecture
Interface	I-Architecture
(	O
ESI	O
)	O
.	O
</s>
<s>
While	O
the	O
"	O
DMI	O
"	O
name	O
dates	O
back	O
to	O
ICH6	B-Device
,	O
Intel	O
mandates	O
specific	O
combinations	O
of	O
compatible	O
devices	O
,	O
so	O
the	O
presence	O
of	O
a	O
DMI	O
interface	O
does	O
not	O
guarantee	O
by	O
itself	O
that	O
a	O
particular	O
northbridgesouthbridge	O
combination	O
is	O
allowed	O
.	O
</s>
<s>
915GMS	O
,	O
945GMS/GSE/GU	O
and	O
the	O
Atom	B-Device
N450	O
)	O
use	O
a	O
×2	O
link	O
,	O
halving	O
the	O
bandwidth	O
.	O
</s>
<s>
DMI	B-Architecture
2.0	I-Architecture
,	O
introduced	O
in	O
2011	O
,	O
doubles	O
the	O
data	O
transfer	O
rate	O
to	O
2GB/s	O
with	O
a	O
×4	O
link	O
.	O
</s>
<s>
It	O
is	O
used	O
to	O
link	O
an	O
Intel	O
CPU	B-Device
with	O
the	O
Intel	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
,	O
which	O
supersedes	O
the	O
historic	O
implementation	O
of	O
a	O
separate	O
northbridge	B-Device
and	O
southbridge	B-Device
.	O
</s>
<s>
DMI	B-Architecture
3.0	I-Architecture
,	O
released	O
in	O
August	O
2015	O
,	O
allows	O
the	O
8GT/s	O
transfer	O
rate	O
per	O
lane	O
,	O
for	O
a	O
total	O
of	O
four	O
lanes	O
and	O
3.93GB/s	O
for	O
the	O
CPUPCH	O
link	O
.	O
</s>
<s>
It	O
is	O
used	O
by	O
two-chip	O
variants	O
of	O
the	O
Intel	B-Architecture
Skylake	I-Architecture
microprocessors	O
,	O
which	O
are	O
used	O
in	O
conjunction	O
with	O
Intel	O
100	O
Series	O
chipsets	O
;	O
some	O
low	O
power	O
(	O
Skylake-U	O
onwards	O
)	O
and	O
ultra	O
low	O
power	O
(	O
Skylake-Y	O
onwards	O
)	O
mobile	O
Intel	O
processors	O
have	O
the	O
PCH	O
integrated	O
into	O
the	O
physical	O
package	O
as	O
a	O
separate	O
die	O
,	O
referred	O
to	O
as	O
OPI	O
(	O
On	O
Package	O
DMI	O
interconnect	O
Interface	O
)	O
and	O
effectively	O
following	O
the	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
design	O
layout	O
.	O
</s>
<s>
In	O
2021	O
,	O
with	O
the	O
release	O
of	O
500	O
series	O
chipsets	O
,	O
Intel	O
increased	O
the	O
amount	O
of	O
DMI	B-Architecture
3.0	I-Architecture
lanes	O
from	O
four	O
to	O
eight	O
,	O
doubling	O
the	O
bandwidth	O
.	O
</s>
<s>
DMI	O
4.0	O
,	O
released	O
on	O
November	O
4	O
,	O
2021	O
with	O
600	O
series	O
chipsets	O
,	O
doubles	O
the	O
bandwidth	O
each	O
lane	O
provides	O
and	O
is	O
two	O
times	O
faster	O
when	O
compared	O
to	O
DMI	B-Architecture
3.0	I-Architecture
.	O
</s>
<s>
Northbridge	B-Device
devices	O
supporting	O
a	O
northbridge	B-Device
DMI	O
are	O
the	O
Intel	O
915-series	O
,	O
925-series	O
,	O
945-series	O
,	O
955-series	O
,	O
965-series	O
,	O
975-series	O
,	O
G31/33	O
,	O
P35	B-Device
,	O
X38	O
,	O
X48	O
,	O
P45	B-Device
and	O
X58	B-Device
.	O
</s>
<s>
Processors	O
supporting	O
a	O
northbridge	B-Device
DMI	O
and	O
,	O
therefore	O
,	O
not	O
using	O
a	O
separate	O
northbridge	B-Device
,	O
are	O
the	O
Intel	B-Device
Atom	I-Device
,	O
Intel	O
Core	O
i3	O
,	O
Intel	O
Core	O
i5	O
,	O
and	O
Intel	O
Core	O
i7	O
(	O
8xx	O
,	O
7xx	O
and	O
6xx	O
,	O
but	O
not	O
9xx	O
)	O
.	O
</s>
<s>
Processors	O
supporting	O
a	O
northbridge	B-Device
DMI2.0	O
and	O
,	O
therefore	O
not	O
using	O
a	O
separate	O
northbridge	B-Device
,	O
are	O
the	O
2000	O
,	O
3000	O
,	O
4000	O
,	O
and	O
5000	O
series	O
of	O
the	O
Intel	O
Core	O
i3	O
,	O
Core	O
i5	O
and	O
Core	O
i7	O
.	O
</s>
<s>
Southbridge	B-Device
devices	O
supporting	O
a	O
southbridge	B-Device
DMI	O
are	O
the	O
ICH6	B-Device
,	O
ICH7	O
,	O
ICH8	O
,	O
ICH9	O
,	O
ICH10	O
,	O
NM10	O
,	O
P55	B-Device
,	O
H55	O
,	O
H57	O
,	O
Q57	O
,	O
PM55	O
,	O
HM55	O
,	O
HM57	O
,	O
QM57	O
and	O
QS57	O
.	O
</s>
<s>
PCH	O
devices	O
supporting	O
DMI2.0	O
are	O
the	O
Intel	O
B65	O
,	O
H61	O
,	O
H67	O
,	O
P67	O
,	O
Q65	O
,	O
Q67	O
,	O
Z68	O
,	O
HM65	O
,	O
HM67	O
,	O
QM67	O
,	O
QS67	O
,	O
B75	O
,	O
H77	O
,	O
Q75	O
,	O
Q77	O
,	O
Z75	O
,	O
Z77	O
,	O
X79	B-Device
,	O
HM75	O
,	O
HM76	O
,	O
HM77	O
,	O
QM77	O
,	O
QS77	O
,	O
UM77	O
,	O
H81	B-Device
,	I-Device
B85	I-Device
,	I-Device
Q85	I-Device
,	I-Device
Q87	I-Device
,	I-Device
H87	I-Device
,	I-Device
Z87	I-Device
,	I-Device
H97	I-Device
,	I-Device
Z97	I-Device
,	I-Device
C222	I-Device
,	I-Device
C224	I-Device
,	I-Device
C226	I-Device
,	O
X99	B-Device
,	O
H110	O
,	O
and	O
H310	O
.	O
</s>
<s>
The	O
Intel	B-Device
200	I-Device
series	I-Device
,	O
B360	O
,	O
H370	O
,	O
Q370	O
,	O
Z370	O
,	O
Z390	O
,	O
C246	O
,	O
and	O
Intel	B-Device
400	I-Device
series	I-Device
chipsets	O
also	O
support	O
DMI	B-Architecture
3.0	I-Architecture
.	O
</s>
