<s>
A	O
diode	B-General_Concept
matrix	I-General_Concept
is	O
a	O
two-dimensional	O
grid	O
of	O
wires	O
:	O
each	O
"	O
intersection	O
"	O
wherein	O
one-row	O
crosses	O
over	O
another	O
has	O
either	O
a	O
diode	O
connecting	O
them	O
,	O
or	O
the	O
wires	O
are	O
isolated	O
from	O
each	O
other	O
.	O
</s>
<s>
A	O
diode	B-General_Concept
matrix	I-General_Concept
is	O
used	O
as	O
the	O
control	B-General_Concept
store	I-General_Concept
or	O
microprogram	B-Device
in	O
many	O
early	O
computers	O
.	O
</s>
<s>
A	O
logically	O
equivalent	O
transistor	B-General_Concept
matrix	I-General_Concept
is	O
still	O
used	O
as	O
the	O
control	B-General_Concept
store	I-General_Concept
or	O
microprogram	B-Device
or	O
'	O
decode	O
ROM	O
 '	O
in	O
many	O
modern	O
microprocessors	O
.	O
</s>
<s>
A	O
single	O
row	O
of	O
the	O
diode	B-General_Concept
matrix	I-General_Concept
(	O
or	O
transistor	B-General_Concept
matrix	I-General_Concept
)	O
is	O
activated	O
at	O
any	O
one	O
instant	O
.	O
</s>
<s>
A	O
diode	B-General_Concept
matrix	I-General_Concept
ROM	O
was	O
used	O
in	O
many	O
computers	O
in	O
the	O
1960s	O
and	O
70s	O
,	O
as	O
well	O
as	O
electronic	O
desk	O
calculators	B-Application
and	O
keyboard	O
matrix	O
circuits	O
for	O
computer	B-General_Concept
terminals	I-General_Concept
.	O
</s>
<s>
The	O
microsequencer	B-General_Concept
of	O
many	O
early	O
computers	O
,	O
perhaps	O
starting	O
with	O
the	O
Whirlwind	B-Device
I	I-Device
,	O
simply	O
activated	O
each	O
row	O
of	O
the	O
diode	B-General_Concept
matrix	I-General_Concept
in	O
sequence	O
,	O
and	O
after	O
the	O
last	O
row	O
was	O
activated	O
,	O
started	O
over	O
again	O
with	O
the	O
first	O
row	O
.	O
</s>
<s>
The	O
technique	O
of	O
microprogramming	B-Device
as	O
first	O
described	O
by	O
Maurice	O
Wilkes	O
in	O
terms	O
of	O
a	O
second	O
diode	B-General_Concept
matrix	I-General_Concept
added	O
to	O
a	O
diode	B-General_Concept
matrix	I-General_Concept
control	B-General_Concept
store	I-General_Concept
.	O
</s>
<s>
Later	O
computers	O
used	O
a	O
variety	O
of	O
alternative	O
implementations	O
of	O
the	O
control	B-General_Concept
store	I-General_Concept
,	O
but	O
eventually	O
returned	O
to	O
a	O
diode	B-General_Concept
matrix	I-General_Concept
or	O
transistor	B-General_Concept
matrix	I-General_Concept
.	O
</s>
<s>
A	O
person	O
would	O
microprogram	B-Device
the	O
control	B-General_Concept
store	I-General_Concept
on	O
such	O
early	O
computers	O
by	O
manually	O
attaching	O
diodes	O
to	O
selected	O
intersections	O
of	O
the	O
word	O
lines	O
and	O
bit	O
lines	O
.	O
</s>
<s>
The	O
control	B-General_Concept
store	I-General_Concept
on	O
some	O
minicomputers	B-Architecture
was	O
one	O
or	O
more	O
programmable	O
logic	O
array	O
chips	O
.	O
</s>
<s>
The	O
"	O
blank	O
"	O
PLA	O
from	O
the	O
chip	O
manufacturer	O
came	O
with	O
a	O
diode	B-General_Concept
matrix	I-General_Concept
or	O
transistor	B-General_Concept
matrix	I-General_Concept
with	O
a	O
diode	O
(	O
or	O
transistor	O
)	O
at	O
every	O
intersection	O
.	O
</s>
<s>
A	O
person	O
would	O
microprogram	B-Device
the	O
control	B-General_Concept
store	I-General_Concept
on	O
these	O
computers	O
by	O
destroying	O
the	O
unwanted	O
connections	O
at	O
selected	O
intersections	O
.	O
</s>
<s>
Some	O
modern	O
microprocessors	O
and	O
ASICs	O
use	O
a	O
diode	B-General_Concept
matrix	I-General_Concept
or	O
transistor	B-General_Concept
matrix	I-General_Concept
control	B-General_Concept
store	I-General_Concept
.	O
</s>
<s>
Since	O
the	O
control	B-General_Concept
store	I-General_Concept
is	O
in	O
the	O
critical	O
path	O
of	O
computer	O
execution	O
,	O
a	O
fast	O
control	B-General_Concept
store	I-General_Concept
is	O
an	O
important	O
part	O
of	O
a	O
fast	O
computer	O
.	O
</s>
<s>
For	O
a	O
while	O
the	O
control	B-General_Concept
store	I-General_Concept
was	O
many	O
times	O
faster	O
than	O
program	O
memory	O
,	O
allowing	O
a	O
long	O
,	O
complicated	O
sequence	O
of	O
steps	O
through	O
the	O
control	B-General_Concept
store	I-General_Concept
per	O
instruction	O
fetch	O
,	O
leading	O
to	O
what	O
is	O
now	O
called	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
.	O
</s>
<s>
Later	O
techniques	O
for	O
fast	O
instruction	O
cache	O
sped	O
that	O
cache	O
up	O
to	O
the	O
point	O
that	O
the	O
control	B-General_Concept
store	I-General_Concept
was	O
only	O
a	O
few	O
times	O
faster	O
than	O
the	O
instruction	O
cache	O
,	O
leading	O
to	O
fewer	O
and	O
eventually	O
only	O
one	O
step	O
through	O
the	O
control	B-General_Concept
store	I-General_Concept
per	O
instruction	O
fetch	O
in	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
.	O
</s>
