<s>
A	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
is	O
a	O
specialized	O
microprocessor	B-Architecture
chip	O
,	O
with	O
its	O
architecture	O
optimized	O
for	O
the	O
operational	O
needs	O
of	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
.	O
</s>
<s>
DSPs	O
are	O
fabricated	B-Architecture
on	O
MOS	O
integrated	O
circuit	O
chips	O
.	O
</s>
<s>
They	O
are	O
widely	O
used	O
in	O
audio	B-Algorithm
signal	I-Algorithm
processing	I-Algorithm
,	O
telecommunications	O
,	O
digital	B-Algorithm
image	I-Algorithm
processing	I-Algorithm
,	O
radar	B-Application
,	O
sonar	B-Application
and	O
speech	B-Application
recognition	I-Application
systems	O
,	O
and	O
in	O
common	O
consumer	O
electronic	O
devices	O
such	O
as	O
mobile	O
phones	O
,	O
disk	B-Device
drives	I-Device
and	O
high-definition	B-Device
television	I-Device
(	O
HDTV	B-Device
)	O
products	O
.	O
</s>
<s>
Most	O
general-purpose	O
microprocessors	B-Architecture
can	O
also	O
execute	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
algorithms	O
successfully	O
,	O
but	O
may	O
not	O
be	O
able	O
to	O
keep	O
up	O
with	O
such	O
processing	O
continuously	O
in	O
real-time	O
.	O
</s>
<s>
DSPs	O
often	O
use	O
special	O
memory	B-General_Concept
architectures	I-General_Concept
that	O
are	O
able	O
to	O
fetch	O
multiple	O
data	O
or	O
instructions	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	O
)	O
algorithms	O
typically	O
require	O
a	O
large	O
number	O
of	O
mathematical	O
operations	O
to	O
be	O
performed	O
quickly	O
and	O
repeatedly	O
on	O
a	O
series	O
of	O
data	O
samples	O
.	O
</s>
<s>
Most	O
general-purpose	O
microprocessors	B-Architecture
and	O
operating	B-General_Concept
systems	I-General_Concept
can	O
execute	O
DSP	O
algorithms	O
successfully	O
,	O
but	O
are	O
not	O
suitable	O
for	O
use	O
in	O
portable	O
devices	O
such	O
as	O
mobile	O
phones	O
and	O
PDAs	O
because	O
of	O
power	O
efficiency	O
constraints	O
.	O
</s>
<s>
Such	O
performance	O
improvements	O
have	O
led	O
to	O
the	O
introduction	O
of	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
in	O
commercial	O
communications	O
satellites	O
where	O
hundreds	O
or	O
even	O
thousands	O
of	O
analog	O
filters	O
,	O
switches	O
,	O
frequency	O
converters	O
and	O
so	O
on	O
are	O
required	O
to	O
receive	O
and	O
process	O
the	O
uplinked	O
signals	O
and	O
ready	O
them	O
for	O
downlinking	O
,	O
and	O
can	O
be	O
replaced	O
with	O
specialised	O
DSPs	O
with	O
significant	O
benefits	O
to	O
the	O
satellites	O
 '	O
weight	O
,	O
power	O
consumption	O
,	O
complexity/cost	O
of	O
construction	O
,	O
reliability	O
and	O
flexibility	O
of	O
operation	O
.	O
</s>
<s>
The	O
architecture	O
of	O
a	O
DSP	O
is	O
optimized	O
specifically	O
for	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
.	O
</s>
<s>
Most	O
also	O
support	O
some	O
of	O
the	O
features	O
of	O
an	O
applications	O
processor	O
or	O
microcontroller	B-Architecture
,	O
since	O
signal	O
processing	O
is	O
rarely	O
the	O
only	O
task	O
of	O
a	O
system	O
.	O
</s>
<s>
By	O
the	O
standards	O
of	O
general-purpose	O
processors	O
,	O
DSP	O
instruction	O
sets	O
are	O
often	O
highly	O
irregular	O
;	O
while	O
traditional	O
instruction	O
sets	O
are	O
made	O
up	O
of	O
more	O
general	O
instructions	O
that	O
allow	O
them	O
to	O
perform	O
a	O
wider	O
variety	O
of	O
operations	O
,	O
instruction	O
sets	O
optimized	O
for	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
contain	O
instructions	O
for	O
common	O
mathematical	O
operations	O
that	O
occur	O
frequently	O
in	O
DSP	O
calculations	O
.	O
</s>
<s>
One	O
implication	O
for	O
software	O
architecture	O
is	O
that	O
hand-optimized	O
assembly-code	B-Language
routines	O
(	O
assembly	O
programs	O
)	O
are	O
commonly	O
packaged	O
into	O
libraries	O
for	O
re-use	O
,	O
instead	O
of	O
relying	O
on	O
advanced	O
compiler	O
technologies	O
to	O
handle	O
essential	O
algorithms	O
.	O
</s>
<s>
Even	O
with	O
modern	O
compiler	O
optimizations	O
hand-optimized	O
assembly	B-Language
code	I-Language
is	O
more	O
efficient	O
and	O
many	O
common	O
algorithms	O
involved	O
in	O
DSP	O
calculations	O
are	O
hand-written	O
in	O
order	O
to	O
take	O
full	O
advantage	O
of	O
the	O
architectural	O
optimizations	O
.	O
</s>
<s>
Multiple	O
arithmetic	O
units	O
may	O
require	O
memory	B-General_Concept
architectures	I-General_Concept
to	O
support	O
several	O
accesses	O
per	O
instruction	O
cycle	O
–	O
typically	O
supporting	O
reading	O
2	O
data	O
values	O
from	O
2	O
separate	O
data	O
buses	O
and	O
the	O
next	O
instruction	O
(	O
from	O
the	O
instruction	O
cache	O
,	O
or	O
a	O
3rd	O
program	O
memory	O
)	O
simultaneously	O
.	O
</s>
<s>
Special	O
loop	O
controls	O
,	O
such	O
as	O
architectural	O
support	O
for	O
executing	O
a	O
few	O
instruction	O
words	O
in	O
a	O
very	O
tight	B-Algorithm
loop	I-Algorithm
without	O
overhead	O
for	O
instruction	O
fetches	O
or	O
exit	O
testing	O
—	O
such	O
as	O
zero-overhead	B-Device
looping	I-Device
and	O
hardware	O
loop	O
buffers	O
.	O
</s>
<s>
Saturation	B-Algorithm
arithmetic	I-Algorithm
,	O
in	O
which	O
operations	O
that	O
produce	O
overflows	O
will	O
accumulate	O
at	O
the	O
maximum	O
(	O
or	O
minimum	O
)	O
values	O
that	O
the	O
register	O
can	O
hold	O
rather	O
than	O
wrapping	O
around	O
(	O
maximum+1	O
does	O
n't	O
overflow	O
to	O
minimum	O
as	O
in	O
many	O
general-purpose	O
CPUs	O
,	O
instead	O
it	O
stays	O
at	O
maximum	O
)	O
.	O
</s>
<s>
Single-cycle	O
operations	O
to	O
increase	O
the	O
benefits	O
of	O
pipelining	B-General_Concept
.	O
</s>
<s>
DSPs	O
are	O
usually	O
optimized	O
for	O
streaming	O
data	O
and	O
use	O
special	O
memory	B-General_Concept
architectures	I-General_Concept
that	O
are	O
able	O
to	O
fetch	O
multiple	O
data	O
or	O
instructions	O
at	O
the	O
same	O
time	O
,	O
such	O
as	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
or	O
Modified	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
,	O
which	O
use	O
separate	O
program	O
and	O
data	O
memories	O
(	O
sometimes	O
even	O
concurrent	O
access	O
on	O
multiple	O
data	O
buses	O
)	O
.	O
</s>
<s>
In	O
addition	O
,	O
extensive	O
use	O
of	O
DMA	B-General_Concept
is	O
employed	O
.	O
</s>
<s>
DSPs	O
frequently	O
use	O
multi-tasking	O
operating	B-General_Concept
systems	I-General_Concept
,	O
but	O
have	O
no	O
support	O
for	O
virtual	B-Architecture
memory	I-Architecture
or	O
memory	O
protection	O
.	O
</s>
<s>
Operating	B-General_Concept
systems	I-General_Concept
that	O
use	O
virtual	B-Architecture
memory	I-Architecture
require	O
more	O
time	O
for	O
context	B-Operating_System
switching	I-Operating_System
among	O
processes	B-Operating_System
,	O
which	O
increases	O
latency	O
.	O
</s>
<s>
In	O
1976	O
,	O
Richard	O
Wiggins	O
proposed	O
the	O
Speak	B-Application
&	I-Application
Spell	I-Application
concept	O
to	O
Paul	O
Breedlove	O
,	O
Larry	O
Brantingham	O
,	O
and	O
Gene	O
Frantz	O
at	O
Texas	O
Instruments	O
 '	O
Dallas	O
research	O
facility	O
.	O
</s>
<s>
Two	O
years	O
later	O
in	O
1978	O
,	O
they	O
produced	O
the	O
first	O
Speak	B-Application
&	I-Application
Spell	I-Application
,	O
with	O
the	O
technological	O
centerpiece	O
being	O
the	O
TMS5100	B-Application
,	O
the	O
industry	O
's	O
first	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
.	O
</s>
<s>
It	O
also	O
set	O
other	O
milestones	O
,	O
being	O
the	O
first	O
chip	O
to	O
use	O
linear	O
predictive	O
coding	O
to	O
perform	O
speech	B-Application
synthesis	I-Application
.	O
</s>
<s>
The	O
chip	O
was	O
made	O
possible	O
with	O
a	O
7µm	O
PMOS	B-Algorithm
fabrication	B-Architecture
process	I-Architecture
.	O
</s>
<s>
The	O
AMI	O
S2811	O
"	O
signal	O
processing	O
peripheral	O
"	O
,	O
like	O
many	O
later	O
DSPs	O
,	O
has	O
a	O
hardware	O
multiplier	O
that	O
enables	O
it	O
to	O
do	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
operation	I-Algorithm
in	O
a	O
single	O
instruction	O
.	O
</s>
<s>
The	O
S2281	O
was	O
the	O
first	O
integrated	O
circuit	O
chip	O
specifically	O
designed	O
as	O
a	O
DSP	O
,	O
and	O
fabricated	B-Architecture
using	O
VMOS	O
(	O
V-groove	O
MOS	O
)	O
,	O
a	O
technology	O
that	O
had	O
previously	O
not	O
been	O
mass-produced	O
.	O
</s>
<s>
It	O
was	O
designed	O
as	O
a	O
microprocessor	B-Architecture
peripheral	O
,	O
for	O
the	O
Motorola	B-Device
6800	I-Device
,	O
and	O
it	O
had	O
to	O
be	O
initialized	O
by	O
the	O
host	O
.	O
</s>
<s>
In	O
1980	O
,	O
the	O
first	O
stand-alone	O
,	O
complete	O
DSPs	O
–	O
Nippon	O
Electric	O
Corporation	O
's	O
NEC	B-Device
µPD7720	I-Device
and	O
T	O
's	O
DSP1	B-General_Concept
–	O
were	O
presented	O
at	O
the	O
International	O
Solid-State	O
Circuits	O
Conference	O
'	O
80	O
.	O
</s>
<s>
The	O
Altamira	O
DX-1	O
was	O
another	O
early	O
DSP	O
,	O
utilizing	O
quad	O
integer	O
pipelines	B-General_Concept
with	O
delayed	O
branches	O
and	O
branch	O
prediction	O
.	O
</s>
<s>
Another	O
DSP	O
produced	O
by	O
Texas	O
Instruments	O
(	O
TI	O
)	O
,	O
the	O
TMS32010	B-Architecture
presented	O
in	O
1983	O
,	O
proved	O
to	O
be	O
an	O
even	O
bigger	O
success	O
.	O
</s>
<s>
It	O
was	O
based	O
on	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
and	O
so	O
had	O
separate	O
instruction	O
and	O
data	O
memory	O
.	O
</s>
<s>
It	O
could	O
work	O
on	O
16-bit	O
numbers	O
and	O
needed	O
390ns	O
for	O
a	O
multiply	B-Algorithm
–	I-Algorithm
add	I-Algorithm
operation	O
.	O
</s>
<s>
They	O
had	O
3	O
memories	O
for	O
storing	O
two	O
operands	O
simultaneously	O
and	O
included	O
hardware	O
to	O
accelerate	O
tight	B-Algorithm
loops	I-Algorithm
;	O
they	O
also	O
had	O
an	O
addressing	O
unit	O
capable	O
of	O
loop-addressing	O
.	O
</s>
<s>
Members	O
of	O
this	O
generation	O
were	O
for	O
example	O
the	O
AT&T	O
DSP16A	O
or	O
the	O
Motorola	B-General_Concept
56000	I-General_Concept
.	O
</s>
<s>
These	O
units	O
allowed	O
direct	O
hardware	B-General_Concept
acceleration	I-General_Concept
of	O
very	O
specific	O
but	O
complex	O
mathematical	O
problems	O
,	O
like	O
the	O
Fourier-transform	O
or	O
matrix	B-Architecture
operations	O
.	O
</s>
<s>
SIMD	B-Device
extensions	O
were	O
added	O
,	O
and	O
VLIW	B-General_Concept
and	O
the	O
superscalar	O
architecture	O
appeared	O
.	O
</s>
<s>
Modern	O
signal	O
processors	O
yield	O
greater	O
performance	O
;	O
this	O
is	O
due	O
in	O
part	O
to	O
both	O
technological	O
and	O
architectural	O
advancements	O
like	O
lower	O
design	O
rules	O
,	O
fast-access	O
two-level	O
cache	O
,	O
(	O
E	O
)	O
DMA	B-General_Concept
circuitry	O
and	O
a	O
wider	O
bus	O
system	O
.	O
</s>
<s>
Texas	O
Instruments	O
produces	O
the	O
C6000	B-Architecture
series	O
DSPs	O
,	O
which	O
have	O
clock	O
speeds	O
of	O
1.2GHz	O
and	O
implement	O
separate	O
instruction	O
and	O
data	O
caches	O
.	O
</s>
<s>
The	O
top	O
models	O
are	O
capable	O
of	O
as	O
many	O
as	O
8000	O
MIPS	O
(	O
millions	O
of	O
instructions	O
per	O
second	O
)	O
,	O
use	O
VLIW	B-General_Concept
(	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
)	O
,	O
perform	O
eight	O
operations	O
per	O
clock-cycle	O
and	O
are	O
compatible	O
with	O
a	O
broad	O
range	O
of	O
external	O
peripherals	O
and	O
various	O
buses	O
(	O
PCI/serial/etc	O
)	O
.	O
</s>
<s>
TMS320C6474	O
chips	O
each	O
have	O
three	O
such	O
DSPs	O
,	O
and	O
the	O
newest	O
generation	O
C6000	B-Architecture
chips	O
support	O
floating	B-Algorithm
point	I-Algorithm
as	O
well	O
as	O
fixed	O
point	O
processing	O
.	O
</s>
<s>
Perhaps	O
the	O
best	O
known	O
and	O
most	O
widely	O
deployed	O
is	O
the	O
CEVA-TeakLite	O
DSP	O
family	O
,	O
a	O
classic	O
memory-based	O
architecture	O
,	O
with	O
16-bit	O
or	O
32-bit	O
word-widths	O
and	O
single	O
or	O
dual	O
MACs	B-Algorithm
.	O
</s>
<s>
The	O
CEVA-X	O
DSP	O
family	O
offers	O
a	O
combination	O
of	O
VLIW	B-General_Concept
and	O
SIMD	B-Device
architectures	O
,	O
with	O
different	O
members	O
of	O
the	O
family	O
offering	O
dual	O
or	O
quad	O
16-bit	O
MACs	B-Algorithm
.	O
</s>
<s>
The	O
CEVA-XC	O
DSP	O
family	O
targets	O
Software-defined	B-Architecture
Radio	I-Architecture
(	O
SDR	O
)	O
modem	O
designs	O
and	O
leverages	O
a	O
unique	O
combination	O
of	O
VLIW	B-General_Concept
and	O
Vector	O
architectures	O
with	O
32	O
16-bit	O
MACs	B-Algorithm
.	O
</s>
<s>
Analog	O
Devices	O
produce	O
the	O
SHARC-based	O
DSP	O
and	O
range	O
in	O
performance	O
from	O
66MHz/198	O
MFLOPS	O
(	O
million	O
floating-point	B-Algorithm
operations	O
per	O
second	O
)	O
to	O
400MHz/2400	O
MFLOPS	O
.	O
</s>
<s>
Some	O
models	O
support	O
multiple	O
multipliers	O
and	O
ALUs	O
,	O
SIMD	B-Device
instructions	O
and	O
audio	O
processing-specific	O
components	O
and	O
peripherals	O
.	O
</s>
<s>
The	O
Blackfin	B-General_Concept
family	O
of	O
embedded	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
combine	O
the	O
features	O
of	O
a	O
DSP	O
with	O
those	O
of	O
a	O
general	O
use	O
processor	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
these	O
processors	O
can	O
run	O
simple	O
operating	B-General_Concept
systems	I-General_Concept
like	O
μCLinux	B-Application
,	O
velocity	O
and	O
Nucleus	B-Operating_System
RTOS	I-Operating_System
while	O
operating	O
on	O
real-time	O
data	O
.	O
</s>
<s>
NXP	O
Semiconductors	O
produce	O
DSPs	O
based	O
on	O
TriMedia	B-General_Concept
VLIW	B-General_Concept
technology	O
,	O
optimized	O
for	O
audio	O
and	O
video	O
processing	O
.	O
</s>
<s>
In	O
some	O
products	O
the	O
DSP	O
core	O
is	O
hidden	O
as	O
a	O
fixed-function	O
block	O
into	O
a	O
SoC	B-Architecture
,	O
but	O
NXP	O
also	O
provides	O
a	O
range	O
of	O
flexible	O
single	O
core	O
media	O
processors	O
.	O
</s>
<s>
The	O
TriMedia	B-General_Concept
media	O
processors	O
support	O
both	O
fixed-point	O
arithmetic	O
as	O
well	O
as	O
floating-point	B-Algorithm
arithmetic	I-Algorithm
,	O
and	O
have	O
specific	O
instructions	O
to	O
deal	O
with	O
complex	O
filters	O
and	O
entropy	O
coding	O
.	O
</s>
<s>
Introduced	O
in	O
2004	O
,	O
the	O
dsPIC	O
is	O
designed	O
for	O
applications	O
needing	O
a	O
true	O
DSP	O
as	O
well	O
as	O
a	O
true	O
microcontroller	B-Architecture
,	O
such	O
as	O
motor	O
control	O
and	O
in	O
power	O
supplies	O
.	O
</s>
<s>
The	O
dsPIC	O
runs	O
at	O
up	O
to	O
40MIPS	O
,	O
and	O
has	O
support	O
for	O
16	O
bit	O
fixed	O
point	O
MAC	O
,	O
bit	O
reverse	O
and	O
modulo	O
addressing	O
,	O
as	O
well	O
as	O
DMA	B-General_Concept
.	O
</s>
<s>
Most	O
DSPs	O
use	O
fixed-point	O
arithmetic	O
,	O
because	O
in	O
real	O
world	O
signal	O
processing	O
the	O
additional	O
range	O
provided	O
by	O
floating	B-Algorithm
point	I-Algorithm
is	O
not	O
needed	O
,	O
and	O
there	O
is	O
a	O
large	O
speed	O
benefit	O
and	O
cost	O
benefit	O
due	O
to	O
reduced	O
hardware	O
complexity	O
.	O
</s>
<s>
Floating	B-Algorithm
point	I-Algorithm
DSPs	O
may	O
be	O
invaluable	O
in	O
applications	O
where	O
a	O
wide	O
dynamic	O
range	O
is	O
required	O
.	O
</s>
<s>
Product	O
developers	O
might	O
also	O
use	O
floating	B-Algorithm
point	I-Algorithm
DSPs	O
to	O
reduce	O
the	O
cost	O
and	O
complexity	O
of	O
software	O
development	O
in	O
exchange	O
for	O
more	O
expensive	O
hardware	O
,	O
since	O
it	O
is	O
generally	O
easier	O
to	O
implement	O
algorithms	O
in	O
floating	B-Algorithm
point	I-Algorithm
.	O
</s>
<s>
Generally	O
,	O
DSPs	O
are	O
dedicated	O
integrated	O
circuits	O
;	O
however	O
DSP	O
functionality	O
can	O
also	O
be	O
produced	O
by	O
using	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
chips	O
(	O
FPGAs	B-Architecture
)	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
OMAP3	B-Device
processors	O
include	O
an	O
ARM	B-Application
Cortex-A8	I-Application
and	O
C6000	B-Architecture
DSP	O
.	O
</s>
<s>
Such	O
Modem	O
processors	O
include	O
ASOCS	B-Application
ModemX	O
and	O
CEVA	O
's	O
XC4000	O
.	O
</s>
<s>
With	O
a	O
processing	O
speed	O
of	O
0.4	O
TFLOPS	O
,	O
the	O
chip	O
can	O
achieve	O
better	O
performance	O
than	O
current	O
mainstream	O
DSP	B-Architecture
chips	I-Architecture
.	O
</s>
<s>
The	O
design	O
team	O
has	O
begun	O
to	O
create	O
Huarui-3	O
,	O
which	O
has	O
a	O
processing	O
speed	O
in	O
TFLOPS	O
level	O
and	O
a	O
support	O
for	O
artificial	B-Application
intelligence	I-Application
.	I-Application
</s>
