<s>
In	O
computing	O
,	O
a	O
device	B-Architecture
control	I-Architecture
register	I-Architecture
is	O
a	O
hardware	B-General_Concept
register	I-General_Concept
that	O
controls	O
some	O
computer	B-Architecture
hardware	I-Architecture
device	O
,	O
for	O
example	O
a	O
peripheral	O
or	O
an	O
expansion	B-Device
card	I-Device
.	O
</s>
<s>
The	O
ISA	B-Device
PNP	I-Device
specification	O
divides	O
the	O
registers	O
of	O
a	O
device	O
in	O
two	O
categories	O
:	O
control	B-Operating_System
registers	I-Operating_System
and	O
configuration	O
registers	O
.	O
</s>
<s>
One	O
of	O
the	O
device	B-General_Concept
control	I-General_Concept
registers	I-General_Concept
defined	O
by	O
ISA	B-Device
PNP	I-Device
is	O
(	O
for	O
example	O
)	O
the	O
Activate	O
register	O
,	O
which	O
turns	O
the	O
card	O
on	O
or	O
off	O
.	O
</s>
<s>
The	O
Device	B-Architecture
Control	I-Architecture
Register	I-Architecture
is	O
also	O
the	O
name	O
of	O
a	O
specific	O
register	O
in	O
the	O
PCI	O
Express	O
architecture	O
.	O
</s>
<s>
Device	B-Architecture
Control	I-Architecture
Register	I-Architecture
(	O
DCR	O
)	O
is	O
also	O
the	O
name	O
of	O
an	O
IBM	O
proprietary	O
bus	B-General_Concept
.	O
</s>
<s>
Its	O
stated	O
design	O
goal	O
is	O
to	O
"	O
transfer	O
data	O
between	O
a	O
DCR	O
master	O
,	O
typically	O
a	O
CPU	O
’s	O
general	O
purpose	O
registers	O
,	O
and	O
the	O
DCR	O
slave	O
logic	O
’s	O
device	B-General_Concept
control	I-General_Concept
registers	I-General_Concept
"	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
IBM	O
MultiProcessor	B-Device
Interrupt	I-Device
Controller	I-Device
(	O
MPIC	O
)	O
is	O
connected	O
up	O
to	O
four	O
processors	O
via	O
a	O
shared	O
DCR	O
bus	B-General_Concept
,	O
and	O
in	O
turn	O
the	O
MPIC	O
handles	O
up	O
to	O
128	O
interrupt	B-Application
sources	O
.	O
</s>
