<s>
In	O
field-effect	O
transistors	O
(	O
FETs	O
)	O
,	O
depletion	B-Algorithm
mode	I-Algorithm
and	O
enhancement	B-Algorithm
mode	I-Algorithm
are	O
two	O
major	O
transistor	O
types	O
,	O
corresponding	O
to	O
whether	O
the	O
transistor	O
is	O
in	O
an	O
on	O
state	O
or	O
an	O
off	O
state	O
at	O
zero	O
gate	O
–	O
source	O
voltage	O
.	O
</s>
<s>
Enhancement-mode	B-Algorithm
MOSFETs	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
FETs	O
)	O
are	O
the	O
common	O
switching	O
elements	O
in	O
most	O
integrated	O
circuits	O
.	O
</s>
<s>
In	O
most	O
circuits	O
,	O
this	O
means	O
pulling	O
an	O
enhancement-mode	B-Algorithm
MOSFET	B-Architecture
's	O
gate	O
voltage	O
towards	O
its	O
drain	O
voltage	O
turns	O
it	O
on	O
.	O
</s>
<s>
In	O
a	O
depletion-mode	B-Algorithm
MOSFET	B-Architecture
,	O
the	O
device	O
is	O
normally	O
on	O
at	O
zero	O
gate	O
–	O
source	O
voltage	O
.	O
</s>
<s>
Such	O
devices	O
are	O
used	O
as	O
load	O
"	O
resistors	O
"	O
in	O
logic	O
circuits	O
(	O
in	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
logic	I-Algorithm
,	O
for	O
example	O
)	O
.	O
</s>
<s>
The	O
mode	O
can	O
be	O
determined	O
by	O
the	O
sign	O
of	O
the	O
threshold	O
voltage	O
(	O
gate	O
voltage	O
relative	O
to	O
source	O
voltage	O
at	O
the	O
point	O
where	O
an	O
inversion	O
layer	O
just	O
forms	O
in	O
the	O
channel	O
)	O
:	O
for	O
an	O
N-type	O
FET	O
,	O
enhancement-mode	B-Algorithm
devices	O
have	O
positive	O
thresholds	O
,	O
and	O
depletion-mode	B-Algorithm
devices	O
have	O
negative	O
thresholds	O
;	O
for	O
a	O
P-type	O
FET	O
,	O
enhancement-mode	B-Algorithm
have	O
negative	O
,	O
and	O
depletion-mode	B-Algorithm
have	O
positive	O
.	O
</s>
<s>
Junction	O
field-effect	O
transistors	O
(	O
JFETs	O
)	O
are	O
depletion-mode	B-Algorithm
,	O
since	O
the	O
gate	O
junction	O
would	O
forward	O
bias	O
if	O
the	O
gate	O
were	O
taken	O
more	O
than	O
a	O
little	O
from	O
source	O
toward	O
drain	O
voltage	O
.	O
</s>
<s>
Some	O
sources	O
say	O
"	O
depletion	B-Algorithm
type	I-Algorithm
"	O
and	O
"	O
enhancement	B-Algorithm
type	I-Algorithm
"	O
for	O
the	O
device	O
types	O
as	O
described	O
in	O
this	O
article	O
as	O
"	O
depletion	B-Algorithm
mode	I-Algorithm
"	O
and	O
"	O
enhancement	B-Algorithm
mode	I-Algorithm
"	O
,	O
and	O
apply	O
the	O
"	O
mode	O
"	O
terms	O
for	O
which	O
direction	O
the	O
gate	O
–	O
source	O
voltage	O
differs	O
from	O
zero	O
.	O
</s>
<s>
Moving	O
the	O
gate	O
voltage	O
toward	O
the	O
drain	O
voltage	O
"	O
enhances	O
"	O
the	O
conduction	O
in	O
the	O
channel	O
,	O
so	O
this	O
defines	O
the	O
enhancement	B-Algorithm
mode	I-Algorithm
of	O
operation	O
,	O
while	O
moving	O
the	O
gate	O
away	O
from	O
the	O
drain	O
depletes	O
the	O
channel	O
,	O
so	O
this	O
defines	O
depletion	B-Algorithm
mode	I-Algorithm
.	O
</s>
<s>
Depletion-load	B-Algorithm
NMOS	I-Algorithm
logic	I-Algorithm
refers	O
to	O
the	O
logic	O
family	O
that	O
became	O
dominant	O
in	O
silicon	O
VLSI	O
in	O
the	O
latter	O
half	O
of	O
the	O
1970s	O
;	O
the	O
process	O
supported	O
both	O
enhancement-mode	B-Algorithm
and	O
depletion-mode	B-Algorithm
transistors	O
,	O
and	O
typical	O
logic	O
circuits	O
used	O
enhancement-mode	B-Algorithm
devices	O
as	O
pull-down	O
switches	O
and	O
depletion-mode	B-Algorithm
devices	O
as	O
loads	O
,	O
or	O
pull-ups	O
.	O
</s>
<s>
Logic	O
families	O
built	O
in	O
older	O
processes	O
that	O
did	O
not	O
support	O
depletion-mode	B-Algorithm
transistors	O
were	O
retrospectively	O
referred	O
to	O
as	O
enhancement-load	O
logic	O
,	O
or	O
as	O
saturated-load	O
logic	O
,	O
since	O
the	O
enhancement-mode	B-Algorithm
transistors	O
were	O
typically	O
connected	O
with	O
gate	O
to	O
the	O
VDD	O
supply	O
and	O
operated	O
in	O
the	O
saturation	O
region	O
(	O
sometimes	O
the	O
gates	O
are	O
biased	O
to	O
a	O
higher	O
VGG	O
voltage	O
and	O
operated	O
in	O
the	O
linear	O
region	O
,	O
for	O
a	O
better	O
power	O
–	O
delay	O
product	O
(	O
PDP	O
)	O
,	O
but	O
the	O
loads	O
then	O
take	O
more	O
area	O
)	O
.	O
</s>
<s>
Alternatively	O
,	O
rather	O
than	O
static	B-General_Concept
logic	I-General_Concept
gates	O
,	O
dynamic	B-General_Concept
logic	I-General_Concept
such	O
as	O
four-phase	B-General_Concept
logic	I-General_Concept
was	O
sometimes	O
used	O
in	O
processes	O
that	O
did	O
not	O
have	O
depletion-mode	B-Algorithm
transistors	O
available	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
1971	O
Intel	B-General_Concept
4004	I-General_Concept
used	O
enhancement-load	O
silicon-gate	O
PMOS	B-Algorithm
logic	I-Algorithm
,	O
and	O
the	O
1976	O
Zilog	B-General_Concept
Z80	I-General_Concept
used	O
depletion-load	O
silicon-gate	O
NMOS	O
.	O
</s>
<s>
The	O
first	O
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
)	O
demonstrated	O
by	O
Egyptian	O
engineer	O
Mohamed	O
M	O
.	O
Atalla	O
and	O
Korean	O
engineer	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1960	O
was	O
an	O
enhancement-mode	B-Algorithm
silicon	O
semiconductor	O
device	O
.	O
</s>
<s>
In	O
1963	O
,	O
both	O
depletion	O
-	O
and	O
enhancement-mode	B-Algorithm
MOSFETs	B-Architecture
were	O
described	O
by	O
Steve	O
R.Hofstein	O
and	O
Fred	O
P.Heiman	O
at	O
RCA	O
Laboratories	O
.	O
</s>
<s>
Kunig	O
at	O
Westinghouse	O
Electric	O
fabricated	O
enhancement	O
-	O
and	O
depletion-mode	B-Algorithm
indium	O
arsenide	O
(	O
InAs	O
)	O
MOS	O
thin-film	O
transistors	O
(	O
TFTs	O
)	O
.	O
</s>
<s>
In	O
2022	O
,	O
the	O
first	O
dual-mode	O
organic	O
transistor	O
that	O
behaves	O
in	O
both	O
depletion	B-Algorithm
mode	I-Algorithm
and	O
enhancement	B-Algorithm
mode	I-Algorithm
was	O
reported	O
by	O
a	O
team	O
at	O
University	O
of	O
California-Santa	O
Barbara	O
.	O
</s>
