<s>
In	O
integrated	O
circuits	O
,	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
is	O
a	O
form	O
of	O
digital	O
logic	B-General_Concept
family	I-General_Concept
that	O
uses	O
only	O
a	O
single	O
power	O
supply	O
voltage	O
,	O
unlike	O
earlier	O
NMOS	B-Algorithm
(	O
n-type	O
metal-oxide	O
semiconductor	O
)	O
logic	B-General_Concept
families	I-General_Concept
that	O
needed	O
more	O
than	O
one	O
different	O
power	O
supply	O
voltage	O
.	O
</s>
<s>
Although	O
manufacturing	O
these	O
integrated	O
circuits	O
required	O
additional	O
processing	O
steps	O
,	O
improved	O
switching	O
speed	O
and	O
the	O
elimination	O
of	O
the	O
extra	O
power	O
supply	O
made	O
this	O
logic	B-General_Concept
family	I-General_Concept
the	O
preferred	O
choice	O
for	O
many	O
microprocessors	B-Architecture
and	O
other	O
logic	O
elements	O
.	O
</s>
<s>
Depletion-mode	B-Algorithm
n-type	O
MOSFETs	B-Architecture
as	O
load	O
transistors	O
allow	O
single	O
voltage	O
operation	O
and	O
achieve	O
greater	O
speed	O
than	O
possible	O
with	O
pure	O
enhancement-load	O
devices	O
.	O
</s>
<s>
This	O
is	O
partly	O
because	O
the	O
depletion-mode	B-Algorithm
MOSFETs	B-Architecture
can	O
be	O
a	O
better	O
current	O
source	O
approximation	O
than	O
the	O
simpler	O
enhancement-mode	B-Algorithm
transistor	O
can	O
,	O
especially	O
when	O
no	O
extra	O
voltage	O
is	O
available	O
(	O
one	O
of	O
the	O
reasons	O
early	O
PMOS	B-Algorithm
and	O
NMOS	B-Algorithm
chips	O
demanded	O
several	O
voltages	O
)	O
.	O
</s>
<s>
The	O
inclusion	O
of	O
depletion-mode	B-Algorithm
NMOS	B-Architecture
transistors	I-Architecture
in	O
the	O
manufacturing	B-Architecture
process	I-Architecture
demanded	O
additional	O
manufacturing	O
steps	O
compared	O
to	O
the	O
simpler	O
enhancement-load	O
circuits	O
;	O
this	O
is	O
because	O
depletion-load	O
devices	O
are	O
formed	O
by	O
increasing	O
the	O
amount	O
of	O
dopant	O
in	O
the	O
load	O
transistors	O
channel	O
region	O
,	O
in	O
order	O
to	O
adjust	O
their	O
threshold	O
voltage	O
.	O
</s>
<s>
Although	O
the	O
CMOS	B-Device
process	O
replaced	O
most	O
NMOS	B-Algorithm
designs	O
during	O
the	O
1980s	O
,	O
some	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
designs	O
are	O
still	O
produced	O
,	O
typically	O
in	O
parallel	O
with	O
newer	O
CMOS	B-Device
counterparts	O
.	O
</s>
<s>
One	O
example	O
of	O
this	O
is	O
the	O
Z84015	B-General_Concept
and	O
Z84C15	O
.	O
</s>
<s>
Following	O
the	O
invention	O
of	O
the	O
MOSFET	B-Architecture
by	O
Mohamed	O
Atalla	O
and	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
,	O
they	O
demonstrated	O
MOSFET	B-Architecture
technology	O
in	O
1960	O
.	O
</s>
<s>
They	O
fabricated	B-Architecture
both	O
PMOS	B-Algorithm
and	O
NMOS	B-Algorithm
devices	O
with	O
a	O
20µm	O
process	O
.	O
</s>
<s>
However	O
,	O
the	O
NMOS	B-Algorithm
devices	O
were	O
impractical	O
,	O
and	O
only	O
the	O
PMOS	B-Algorithm
type	O
were	O
practical	O
working	O
devices	O
.	O
</s>
<s>
In	O
1965	O
,	O
Chih-Tang	O
Sah	O
,	O
Otto	O
Leistiko	O
and	O
A.S.	O
Grove	O
at	O
Fairchild	O
Semiconductor	O
fabricated	B-Architecture
several	O
NMOS	B-Algorithm
devices	O
with	O
channel	O
lengths	O
between	O
8µm	O
and	O
65µm	O
.	O
</s>
<s>
Dale	O
L	O
.	O
Critchlow	O
and	O
Robert	O
H	O
.	O
Dennard	O
at	O
IBM	O
also	O
fabricated	B-Architecture
NMOS	B-Algorithm
devices	O
in	O
the	O
1960s	O
.	O
</s>
<s>
The	O
first	O
IBM	O
NMOS	B-Algorithm
product	O
was	O
a	O
memory	B-Architecture
chip	I-Architecture
with	O
1kb	O
data	O
and	O
50100	O
ns	O
access	B-General_Concept
time	I-General_Concept
,	O
which	O
entered	O
large-scale	O
manufacturing	O
in	O
the	O
early	O
1970s	O
.	O
</s>
<s>
This	O
led	O
to	O
MOS	O
semiconductor	B-Architecture
memory	I-Architecture
replacing	O
earlier	O
bipolar	B-General_Concept
and	O
ferrite-core	O
memory	O
technologies	O
in	O
the	O
1970s	O
.	O
</s>
<s>
In	O
the	O
late	O
1960s	O
,	O
bipolar	B-General_Concept
junction	O
transistors	O
were	O
faster	O
than	O
(	O
p-channel	O
)	O
MOS	B-Architecture
transistors	I-Architecture
then	O
used	O
and	O
were	O
more	O
reliable	O
,	O
but	O
they	O
also	O
consumed	O
much	O
more	O
power	O
,	O
required	O
more	O
area	O
,	O
and	O
demanded	O
a	O
more	O
complicated	O
manufacturing	B-Architecture
process	I-Architecture
.	O
</s>
<s>
MOS	O
ICs	O
were	O
considered	O
interesting	O
but	O
inadequate	O
for	O
supplanting	O
the	O
fast	O
bipolar	B-General_Concept
circuits	O
in	O
anything	O
but	O
niche	O
markets	O
,	O
such	O
as	O
low	O
power	O
applications	O
.	O
</s>
<s>
One	O
of	O
the	O
reasons	O
for	O
the	O
low	O
speed	O
was	O
that	O
MOS	B-Architecture
transistors	I-Architecture
had	O
gates	O
made	O
of	O
aluminum	O
which	O
led	O
to	O
considerable	O
parasitic	O
capacitances	O
using	O
the	O
manufacturing	O
processes	O
of	O
the	O
time	O
.	O
</s>
<s>
This	O
new	O
type	O
of	O
pMOS	B-Architecture
transistor	I-Architecture
was	O
3	O
–	O
5	O
times	O
as	O
fast	O
(	O
per	O
watt	O
)	O
as	O
the	O
aluminum-gate	O
pMOS	B-Architecture
transistor	I-Architecture
,	O
and	O
it	O
needed	O
less	O
area	O
,	O
had	O
much	O
lower	O
leakage	O
and	O
higher	O
reliability	O
.	O
</s>
<s>
The	O
same	O
year	O
,	O
Faggin	O
also	O
built	O
the	O
first	O
IC	O
using	O
the	O
new	O
transistor	O
type	O
,	O
the	O
Fairchild	O
3708	O
(	O
8-bit	O
analog	O
multiplexer	B-Protocol
with	O
decoder	O
)	O
,	O
which	O
demonstrated	O
a	O
substantially	O
improved	O
performance	O
over	O
its	O
metal-gate	O
counterpart	O
.	O
</s>
<s>
In	O
less	O
than	O
10	O
years	O
,	O
the	O
silicon	O
gate	O
MOS	B-Architecture
transistor	I-Architecture
replaced	O
bipolar	B-General_Concept
circuits	O
as	O
the	O
main	O
vehicle	O
for	O
complex	O
digital	O
ICs	O
.	O
</s>
<s>
There	O
are	O
a	O
couple	O
of	O
drawbacks	O
associated	O
with	O
PMOS	B-Algorithm
:	O
The	O
electron	O
holes	O
that	O
are	O
the	O
charge	O
(	O
current	O
)	O
carriers	O
in	O
PMOS	B-Architecture
transistors	I-Architecture
have	O
lower	O
mobility	O
than	O
the	O
electrons	O
that	O
are	O
the	O
charge	O
carriers	O
in	O
NMOS	B-Architecture
transistors	I-Architecture
(	O
a	O
ratio	O
of	O
approximately	O
2.5	O
)	O
,	O
furthermore	O
PMOS	B-Algorithm
circuits	O
do	O
not	O
interface	O
easily	O
with	O
low	O
voltage	O
positive	O
logic	O
such	O
as	O
DTL-logic	B-General_Concept
and	O
TTL-logic	B-General_Concept
(	O
the	O
7400-series	O
)	O
.	O
</s>
<s>
However	O
,	O
PMOS	B-Architecture
transistors	I-Architecture
are	O
relatively	O
easy	O
to	O
make	O
and	O
were	O
therefore	O
developed	O
first	O
—	O
ionic	O
contamination	O
of	O
the	O
gate	O
oxide	O
from	O
etching	B-Algorithm
chemicals	O
and	O
other	O
sources	O
can	O
very	O
easily	O
prevent	O
(	O
the	O
electron	O
based	O
)	O
NMOS	B-Architecture
transistors	I-Architecture
from	O
switching	O
off	O
,	O
while	O
the	O
effect	O
in	O
(	O
the	O
electron-hole	O
based	O
)	O
PMOS	B-Architecture
transistors	I-Architecture
is	O
much	O
less	O
severe	O
.	O
</s>
<s>
Fabrication	B-Architecture
of	O
NMOS	B-Architecture
transistors	I-Architecture
therefore	O
has	O
to	O
be	O
many	O
times	O
cleaner	O
than	O
bipolar	B-General_Concept
processing	O
in	O
order	O
to	O
produce	O
working	O
devices	O
.	O
</s>
<s>
Early	O
work	O
on	O
NMOS	B-Algorithm
integrated	O
circuit	O
(	O
IC	O
)	O
technology	O
was	O
presented	O
in	O
a	O
brief	O
IBM	O
paper	O
at	O
ISSCC	O
in	O
1969	O
.	O
</s>
<s>
Hewlett-Packard	O
then	O
started	O
to	O
develop	O
NMOS	B-Algorithm
IC	O
technology	O
to	O
get	O
the	O
promising	O
speed	O
and	O
easy	O
interfacing	O
for	O
its	O
calculator	O
business	O
.	O
</s>
<s>
Already	O
by	O
1970	O
,	O
HP	O
was	O
making	O
good	O
enough	O
nMOS	B-Algorithm
ICs	O
and	O
had	O
characterized	O
it	O
enough	O
so	O
that	O
Dave	O
Maitland	O
was	O
able	O
to	O
write	O
an	O
article	O
about	O
nMOS	B-Algorithm
in	O
the	O
December	O
,	O
1970	O
issue	O
of	O
Electronics	O
magazine	O
.	O
</s>
<s>
However	O
,	O
NMOS	B-Algorithm
remained	O
uncommon	O
in	O
the	O
rest	O
of	O
the	O
semiconductor	O
industry	O
until	O
1973	O
.	O
</s>
<s>
The	O
production-ready	O
NMOS	B-Algorithm
process	O
enabled	O
HP	O
to	O
develop	O
the	O
industry	O
’s	O
first	O
4-kbit	O
IC	O
ROM	B-Device
.	O
</s>
<s>
Motorola	O
eventually	O
served	O
as	O
a	O
second	O
source	O
for	O
these	O
products	O
and	O
so	O
became	O
one	O
of	O
the	O
first	O
commercial	O
semiconductor	O
vendors	O
to	O
master	O
the	O
NMOS	B-Algorithm
process	O
,	O
thanks	O
to	O
Hewlett-Packard	O
.	O
</s>
<s>
A	O
while	O
later	O
,	O
the	O
startup	O
company	O
Intel	O
announced	O
a	O
1-kbit	O
pMOS	B-Algorithm
DRAM	O
,	O
called	O
1102	O
,	O
developed	O
as	O
a	O
custom	O
product	O
for	O
Honeywell	O
(	O
an	O
attempt	O
to	O
replace	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
in	O
their	O
mainframe	B-Architecture
computers	I-Architecture
)	O
.	O
</s>
<s>
HP	O
’s	O
calculator	O
engineers	O
,	O
who	O
wanted	O
a	O
similar	O
but	O
more	O
robust	O
product	O
for	O
the	O
9800	B-Device
series	I-Device
calculators	O
,	O
contributed	O
IC	O
fabrication	B-Architecture
experience	O
from	O
their	O
4-kbit	O
ROM	B-Device
project	O
to	O
help	O
improve	O
Intel	O
DRAM	O
’s	O
reliability	O
,	O
operating-voltage	O
,	O
and	O
temperature	O
range	O
.	O
</s>
<s>
These	O
efforts	O
contributed	O
to	O
the	O
heavily	O
enhanced	O
Intel	O
1103	O
1-kbit	O
pMOS	B-Algorithm
DRAM	O
,	O
which	O
was	O
the	O
world	O
’s	O
first	O
commercially	O
available	O
DRAM	O
IC	O
.	O
</s>
<s>
Early	O
MOS	O
logic	O
had	O
one	O
transistor	O
type	O
,	O
which	O
is	O
enhancement	B-Algorithm
mode	I-Algorithm
so	O
that	O
it	O
can	O
act	O
as	O
a	O
logic	O
switch	O
.	O
</s>
<s>
Since	O
suitable	O
resistors	O
were	O
hard	O
to	O
make	O
,	O
the	O
logic	O
gates	O
used	O
saturated	O
loads	O
;	O
that	O
is	O
,	O
to	O
make	O
the	O
one	O
type	O
of	O
transistor	O
act	O
as	O
a	O
load	O
resistor	O
,	O
the	O
transistor	O
had	O
to	O
be	O
turned	O
always	O
on	O
by	O
tying	O
its	O
gate	O
to	O
the	O
power	O
supply	O
(	O
the	O
more	O
negative	O
rail	O
for	O
PMOS	B-Algorithm
logic	I-Algorithm
,	O
or	O
the	O
more	O
positive	O
rail	O
for	O
NMOS	B-Algorithm
logic	I-Algorithm
)	O
.	O
</s>
<s>
A	O
depletion-mode	B-Algorithm
device	O
with	O
gate	O
tied	O
to	O
the	O
opposite	O
supply	O
rail	O
is	O
a	O
much	O
better	O
load	O
than	O
an	O
enhancement-mode	B-Algorithm
device	O
,	O
acting	O
somewhere	O
between	O
a	O
resistor	O
and	O
a	O
current	O
source	O
.	O
</s>
<s>
The	O
first	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
circuits	O
were	O
pioneered	O
and	O
made	O
by	O
the	O
DRAM	O
manufacturer	O
Mostek	O
,	O
which	O
made	O
depletion-mode	B-Algorithm
transistors	O
available	O
for	O
the	O
design	O
of	O
the	O
original	O
Zilog	B-General_Concept
Z80	I-General_Concept
in	O
1975	O
–	O
76	O
.	O
</s>
<s>
Mostek	O
had	O
the	O
ion	O
implantation	O
equipment	O
needed	O
to	O
create	O
a	O
doping	B-Algorithm
profile	I-Algorithm
more	O
precise	O
than	O
possible	O
with	O
diffusion	O
methods	O
,	O
so	O
that	O
the	O
threshold	O
voltage	O
of	O
the	O
load	O
transistors	O
could	O
be	O
adjusted	O
reliably	O
.	O
</s>
<s>
Depletion-load	O
was	O
first	O
employed	O
for	O
a	O
redesign	O
of	O
one	O
of	O
Intel	O
's	O
most	O
important	O
products	O
at	O
the	O
time	O
,	O
a	O
+	O
5V-only	O
1Kbit	O
NMOS	B-Algorithm
SRAM	B-Architecture
called	O
the	O
2102	O
(	O
using	O
more	O
than	O
6000	O
transistors	O
)	O
.	O
</s>
<s>
The	O
result	O
of	O
this	O
redesign	O
was	O
the	O
significantly	O
faster	O
2102A	O
,	O
where	O
the	O
highest	O
performing	O
versions	O
of	O
the	O
chip	O
had	O
access	B-General_Concept
times	I-General_Concept
of	O
less	O
than	O
100ns	O
,	O
taking	O
MOS	B-Architecture
memories	I-Architecture
close	O
to	O
the	O
speed	O
of	O
bipolar	B-General_Concept
RAMs	O
for	O
the	O
first	O
time	O
.	O
</s>
<s>
Depletion-load	B-Algorithm
NMOS	I-Algorithm
processes	O
were	O
also	O
used	O
by	O
several	O
other	O
manufacturers	O
to	O
produce	O
many	O
incarnations	O
of	O
popular	O
8-bit	O
,	O
16-bit	O
,	O
and	O
32-bit	O
CPUs	O
.	O
</s>
<s>
Similarly	O
to	O
early	O
PMOS	B-Algorithm
and	O
NMOS	B-Algorithm
CPU	O
designs	O
using	O
enhancement	B-Algorithm
mode	I-Algorithm
MOSFETs	B-Architecture
as	O
loads	O
,	O
depletion-load	B-Algorithm
nMOS	I-Algorithm
designs	O
typically	O
employed	O
various	O
types	O
of	O
dynamic	B-General_Concept
logic	I-General_Concept
(	O
rather	O
than	O
just	O
static	B-Device
gates	O
)	O
or	O
pass	O
transistors	O
used	O
as	O
dynamic	B-General_Concept
clocked	O
latches	B-General_Concept
.	O
</s>
<s>
Processors	O
built	O
with	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
circuitry	O
include	O
the	O
6800	B-Device
(	O
in	O
later	O
versions	O
)	O
,	O
the	O
6502	B-General_Concept
,	O
Signetics	B-General_Concept
2650	I-General_Concept
,	O
8085	B-General_Concept
,	O
6809	B-Device
,	O
8086	B-General_Concept
,	O
Z8000	B-Device
,	O
NS32016	O
,	O
and	O
many	O
others	O
(	O
whether	O
or	O
not	O
the	O
HMOS	O
processors	O
below	O
are	O
included	O
,	O
as	O
special	O
cases	O
)	O
.	O
</s>
<s>
A	O
large	O
number	O
of	O
support	O
and	O
peripheral	O
ICs	O
were	O
also	O
implemented	O
using	O
(	O
often	O
static	B-Device
)	O
depletion-load	O
based	O
circuitry	O
.	O
</s>
<s>
there	O
were	O
never	O
any	O
standardized	O
logic	B-General_Concept
families	I-General_Concept
in	O
NMOS	B-Algorithm
,	O
such	O
as	O
the	O
bipolar	B-General_Concept
7400	O
series	O
and	O
the	O
CMOS	B-Device
4000	O
series	O
,	O
although	O
designs	O
with	O
several	O
second	O
source	O
manufacturers	O
often	O
achieved	O
something	O
of	O
a	O
de	O
facto	O
standard	O
component	O
status	O
.	O
</s>
<s>
One	O
example	O
of	O
this	O
is	O
the	O
NMOS	B-Algorithm
8255	B-Device
PIO	I-Device
design	O
,	O
originally	O
intended	O
as	O
an	O
8085	B-General_Concept
peripheral	O
chip	O
,	O
that	O
has	O
been	O
used	O
in	O
Z80	B-General_Concept
and	O
x86	O
embedded	B-Architecture
systems	I-Architecture
and	O
many	O
other	O
contexts	O
for	O
several	O
decades	O
.	O
</s>
<s>
Modern	O
low	O
power	O
versions	O
are	O
available	O
as	O
CMOS	B-Device
or	O
BiCMOS	B-General_Concept
implementations	O
,	O
similar	O
to	O
the	O
7400-series	O
.	O
</s>
<s>
Intel	O
's	O
own	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
process	O
was	O
known	O
as	O
HMOS	O
,	O
for	O
High	O
density	O
,	O
short	O
channel	O
MOS	O
.	O
</s>
<s>
The	O
first	O
version	O
was	O
introduced	O
in	O
late	O
1976	O
and	O
first	O
used	O
for	O
their	O
static	B-Architecture
RAM	I-Architecture
products	O
,	O
it	O
was	O
soon	O
being	O
used	O
for	O
faster	O
and/or	O
less	O
power	O
hungry	O
versions	O
of	O
the	O
8085	B-General_Concept
,	O
8086	B-General_Concept
,	O
and	O
other	O
chips	O
.	O
</s>
<s>
According	O
to	O
Intel	O
,	O
HMOS	O
II	O
(	O
1979	O
)	O
provided	O
twice	O
the	O
density	O
and	O
four	O
times	O
the	O
speed/power	O
product	O
over	O
other	O
typical	O
contemporary	O
depletion-load	B-Algorithm
NMOS	I-Algorithm
processes	O
.	O
</s>
<s>
This	O
version	O
was	O
widely	O
licensed	O
by	O
3rd	O
parties	O
,	O
including	O
(	O
among	O
others	O
)	O
Motorola	O
who	O
used	O
it	O
for	O
their	O
Motorola	B-Device
68000	I-Device
,	O
and	O
Commodore	O
Semiconductor	O
Group	O
,	O
who	O
used	O
it	O
for	O
their	O
MOS	B-General_Concept
Technology	I-General_Concept
8502	I-General_Concept
die-shrunk	O
MOS	B-General_Concept
6502	I-General_Concept
.	O
</s>
<s>
By	O
the	O
time	O
HMOS	O
III	O
was	O
introduced	O
in	O
1982	O
,	O
Intel	O
had	O
begun	O
a	O
switch	O
to	O
their	O
CHMOS	O
process	O
,	O
a	O
CMOS	B-Device
process	O
using	O
design	O
elements	O
of	O
the	O
HMOS	O
lines	O
.	O
</s>
<s>
HMOS	O
,	O
HMOS	O
II	O
,	O
HMOS	O
III	O
,	O
and	O
HMOS	O
IV	O
were	O
together	O
used	O
for	O
many	O
different	O
kinds	O
of	O
processors	O
;	O
the	O
8085	B-General_Concept
,	O
8048	B-Device
,	O
8051	B-Architecture
,	O
8086	B-General_Concept
,	O
80186	B-Device
,	O
80286	B-General_Concept
,	O
and	O
many	O
others	O
,	O
but	O
also	O
for	O
several	O
generations	O
of	O
the	O
same	O
basic	O
design	O
,	O
see	O
datasheets	O
.	O
</s>
<s>
In	O
the	O
mid-1980s	O
,	O
faster	O
CMOS	B-Device
variants	O
,	O
using	O
similar	O
HMOS	O
process	O
technology	O
,	O
such	O
as	O
Intel	O
's	O
CHMOS	O
I	O
,	O
II	O
,	O
III	O
,	O
IV	O
,	O
etc	O
.	O
</s>
<s>
started	O
to	O
supplant	O
n-channel	O
HMOS	O
for	O
applications	O
such	O
as	O
the	O
Intel	B-General_Concept
80386	I-General_Concept
and	O
certain	O
microcontrollers	B-Architecture
.	O
</s>
<s>
A	O
few	O
years	O
later	O
,	O
in	O
the	O
late	O
1980s	O
,	O
BiCMOS	B-General_Concept
was	O
introduced	O
for	O
high-performance	O
microprocessors	B-Architecture
as	O
well	O
as	O
for	O
high	O
speed	O
analog	O
circuits	O
.	O
</s>
<s>
Today	O
,	O
most	O
digital	O
circuits	O
,	O
including	O
the	O
ubiquitous	O
7400	O
series	O
,	O
are	O
manufactured	O
using	O
various	O
CMOS	B-Device
processes	O
with	O
a	O
range	O
of	O
different	O
topologies	O
employed	O
.	O
</s>
<s>
This	O
means	O
that	O
,	O
in	O
order	O
to	O
enhance	O
speed	O
and	O
save	O
die	O
area	O
(	O
transistors	O
and	O
wiring	O
)	O
,	O
high	O
speed	O
CMOS	B-Device
designs	O
often	O
employ	O
other	O
elements	O
than	O
just	O
the	O
complementary	O
static	B-Device
gates	O
and	O
the	O
transmission	O
gates	O
of	O
typical	O
slow	O
low-power	O
CMOS	B-Device
circuits	O
(	O
the	O
only	O
CMOS	B-Device
type	O
during	O
the	O
1960s	O
and	O
1970s	O
)	O
.	O
</s>
<s>
These	O
methods	O
use	O
significant	O
amounts	O
of	O
dynamic	B-General_Concept
circuitry	O
in	O
order	O
to	O
construct	O
the	O
larger	O
building	O
blocks	O
on	O
the	O
chip	O
,	O
such	O
as	O
latches	B-General_Concept
,	O
decoders	O
,	O
multiplexers	B-Protocol
,	O
and	O
so	O
on	O
,	O
and	O
evolved	O
from	O
the	O
various	O
dynamic	B-General_Concept
methodologies	O
developed	O
for	O
NMOS	B-Algorithm
and	O
PMOS	B-Algorithm
circuits	O
during	O
the	O
1970s	O
.	O
</s>
<s>
Compared	O
to	O
static	B-Device
CMOS	B-Device
,	O
all	O
variants	O
of	O
NMOS	B-Algorithm
(	O
and	O
PMOS	B-Algorithm
)	O
are	O
relatively	O
power	O
hungry	O
in	O
steady	O
state	O
.	O
</s>
<s>
This	O
contrasts	O
to	O
the	O
power	O
consumption	O
characteristics	O
of	O
static	B-Device
CMOS	B-Device
circuits	O
,	O
which	O
is	O
due	O
only	O
to	O
the	O
transient	O
power	O
draw	O
when	O
the	O
output	O
state	O
is	O
changed	O
and	O
the	O
p	O
-	O
and	O
n-transistors	O
thereby	O
briefly	O
conduct	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
However	O
,	O
this	O
is	O
a	O
simplified	O
view	O
,	O
and	O
a	O
more	O
complete	O
picture	O
has	O
to	O
also	O
include	O
the	O
fact	O
that	O
even	O
purely	O
static	B-Device
CMOS	B-Device
circuits	O
have	O
significant	O
leakage	O
in	O
modern	O
tiny	O
geometries	O
,	O
as	O
well	O
as	O
the	O
fact	O
that	O
modern	O
CMOS	B-Device
chips	O
often	O
contain	O
dynamic	B-General_Concept
and/or	O
domino	B-General_Concept
logic	I-General_Concept
with	O
a	O
certain	O
amount	O
of	O
pseudo	O
nMOS	B-Algorithm
circuitry	O
.	O
</s>
<s>
In	O
both	O
technologies	O
,	O
each	O
gate	O
contains	O
one	O
NMOS	B-Architecture
transistor	I-Architecture
which	O
is	O
permanently	O
turned	O
on	O
and	O
connected	O
to	O
Vdd	O
.	O
</s>
<s>
In	O
standard	O
NMOS	B-Algorithm
,	O
the	O
pull-up	O
is	O
the	O
same	O
kind	O
of	O
transistor	O
as	O
is	O
used	O
for	O
logic	O
switches	O
.	O
</s>
<s>
Depletion-load	O
processes	O
replace	O
this	O
transistor	O
with	O
a	O
depletion-mode	B-Algorithm
NMOS	B-Algorithm
at	O
a	O
constant	O
gate	O
bias	O
,	O
with	O
the	O
gate	O
tied	O
directly	O
to	O
the	O
source	O
.	O
</s>
<s>
This	O
results	O
in	O
high	O
static	B-Device
power	O
consumption	O
.	O
</s>
<s>
Both	O
(	O
enhancement-mode	B-Algorithm
)	O
saturated-load	O
and	O
depletion-mode	B-Algorithm
pull-up	O
transistors	O
use	O
greatest	O
power	O
when	O
the	O
output	O
is	O
stable	O
at	O
0	O
,	O
so	O
this	O
loss	O
is	O
considerable	O
.	O
</s>
<s>
Because	O
the	O
strength	O
of	O
a	O
depletion-mode	B-Algorithm
transistor	O
falls	O
off	O
less	O
on	O
the	O
approach	O
to	O
1	O
,	O
they	O
may	O
reach	O
1	O
faster	O
despite	O
starting	O
slower	O
,	O
i.e.	O
</s>
