<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
delay	B-General_Concept
slot	I-General_Concept
is	O
an	O
instruction	O
slot	O
being	O
executed	O
without	O
the	O
effects	O
of	O
a	O
preceding	O
instruction	O
.	O
</s>
<s>
The	O
most	O
common	O
form	O
is	O
a	O
single	O
arbitrary	O
instruction	O
located	O
immediately	O
after	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
on	O
a	O
RISC	B-Architecture
or	O
DSP	B-Architecture
architecture	O
;	O
this	O
instruction	O
will	O
execute	O
even	O
if	O
the	O
preceding	O
branch	B-General_Concept
is	O
taken	O
.	O
</s>
<s>
It	O
is	O
typical	O
for	O
assemblers	B-Language
to	O
automatically	O
reorder	O
instructions	O
by	O
default	O
,	O
hiding	O
the	O
awkwardness	O
from	O
assembly	O
developers	O
and	O
compilers	O
.	O
</s>
<s>
When	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
is	O
involved	O
,	O
the	O
location	O
of	O
the	O
following	O
delay	B-General_Concept
slot	I-General_Concept
instruction	O
in	O
the	O
pipeline	B-General_Concept
may	O
be	O
called	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
Branch	B-General_Concept
delay	I-General_Concept
slots	I-General_Concept
are	O
found	O
mainly	O
in	O
DSP	B-Architecture
architectures	O
and	O
older	O
RISC	B-Architecture
architectures	I-Architecture
.	O
</s>
<s>
MIPS	B-Device
,	O
PA-RISC	B-Device
,	O
ETRAX	B-Device
CRIS	I-Device
,	O
SuperH	O
,	O
and	O
SPARC	B-Architecture
are	O
RISC	B-Architecture
architectures	I-Architecture
that	O
each	O
have	O
a	O
single	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
;	O
PowerPC	B-Architecture
,	O
ARM	B-Architecture
,	O
Alpha	B-Device
,	O
and	O
RISC-V	B-Device
do	O
not	O
have	O
any	O
.	O
</s>
<s>
DSP	B-Architecture
architectures	O
that	O
each	O
have	O
a	O
single	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
include	O
the	O
VS	O
DSP	B-Architecture
,	O
μPD77230	O
and	O
TMS320C3x	B-Architecture
.	O
</s>
<s>
The	O
SHARC	B-General_Concept
DSP	B-Architecture
and	O
MIPS-X	B-General_Concept
use	O
a	O
double	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
;	O
such	O
a	O
processor	O
will	O
execute	O
a	O
pair	O
of	O
instructions	O
following	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
before	O
the	O
branch	B-General_Concept
takes	O
effect	O
.	O
</s>
<s>
The	O
TMS320C4x	B-Architecture
uses	O
a	O
triple	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
The	O
following	O
example	O
shows	O
delayed	O
branches	O
in	O
assembly	B-Language
language	I-Language
for	O
the	O
SHARC	B-General_Concept
DSP	B-Architecture
including	O
a	O
pair	O
after	O
the	O
RTS	O
instruction	O
.	O
</s>
<s>
To	O
maintain	O
this	O
rate	O
,	O
the	O
pipeline	B-General_Concept
must	O
be	O
full	O
of	O
instructions	O
at	O
all	O
times	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
is	O
a	O
side	O
effect	O
of	O
pipelined	O
architectures	O
due	O
to	O
the	O
branch	B-General_Concept
hazard	I-General_Concept
,	O
i.e.	O
</s>
<s>
the	O
fact	O
that	O
the	O
branch	B-General_Concept
would	O
not	O
be	O
resolved	O
until	O
the	O
instruction	O
has	O
worked	O
its	O
way	O
through	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
A	O
simple	O
design	O
would	O
insert	O
stalls	O
into	O
the	O
pipeline	B-General_Concept
after	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
until	O
the	O
new	O
branch	B-General_Concept
target	O
address	O
is	O
computed	O
and	O
loaded	O
into	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Each	O
cycle	O
where	O
a	O
stall	O
is	O
inserted	O
is	O
considered	O
one	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
A	O
more	O
sophisticated	O
design	O
would	O
execute	O
program	O
instructions	O
that	O
are	O
not	O
dependent	O
on	O
the	O
result	O
of	O
the	O
branch	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
This	O
optimization	O
can	O
be	O
performed	O
in	O
software	O
at	O
compile	B-Application
time	I-Application
by	O
moving	O
instructions	O
into	O
branch	B-General_Concept
delay	I-General_Concept
slots	I-General_Concept
in	O
the	O
in-memory	O
instruction	O
stream	O
,	O
if	O
the	O
hardware	O
supports	O
this	O
.	O
</s>
<s>
Another	O
side	O
effect	O
is	O
that	O
special	O
handling	O
is	O
needed	O
when	O
managing	O
breakpoints	O
on	O
instructions	O
as	O
well	O
as	O
stepping	O
while	O
debugging	O
within	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
The	O
ideal	O
number	O
of	O
branch	B-General_Concept
delay	I-General_Concept
slots	I-General_Concept
in	O
a	O
particular	O
pipeline	B-General_Concept
implementation	O
is	O
dictated	O
by	O
the	O
number	O
of	O
pipeline	B-General_Concept
stages	O
,	O
the	O
presence	O
of	O
register	O
forwarding	O
,	O
what	O
stage	O
of	O
the	O
pipeline	B-General_Concept
the	O
branch	B-General_Concept
conditions	O
are	O
computed	O
,	O
whether	O
or	O
not	O
a	O
branch	B-General_Concept
target	O
buffer	O
(	O
BTB	O
)	O
is	O
used	O
and	O
many	O
other	O
factors	O
.	O
</s>
<s>
Software	O
compatibility	O
requirements	O
dictate	O
that	O
an	O
architecture	O
may	O
not	O
change	O
the	O
number	O
of	O
delay	B-General_Concept
slots	I-General_Concept
from	O
one	O
generation	O
to	O
the	O
next	O
.	O
</s>
<s>
A	O
load	O
delay	B-General_Concept
slot	I-General_Concept
is	O
an	O
instruction	O
which	O
executes	O
immediately	O
after	O
a	O
load	O
(	O
of	O
a	O
register	O
from	O
memory	O
)	O
but	O
does	O
not	O
see	O
,	O
and	O
need	O
not	O
wait	O
for	O
,	O
the	O
result	O
of	O
the	O
load	O
.	O
</s>
<s>
Load	O
delay	B-General_Concept
slots	I-General_Concept
are	O
very	O
uncommon	O
because	O
load	O
delays	O
are	O
highly	O
unpredictable	O
on	O
modern	O
hardware	O
.	O
</s>
<s>
Load	O
delays	O
were	O
seen	O
on	O
very	O
early	O
RISC	B-Architecture
processor	I-Architecture
designs	O
.	O
</s>
<s>
The	O
MIPS	B-Device
I	O
ISA	O
(	O
implemented	O
in	O
the	O
R2000	B-Device
and	O
R3000	B-Device
microprocessors	O
)	O
suffers	O
from	O
this	O
problem	O
.	O
</s>
<s>
The	O
following	O
example	O
is	O
MIPS	B-Device
I	O
assembly	B-Language
code	I-Language
,	O
showing	O
both	O
a	O
load	O
delay	B-General_Concept
slot	I-General_Concept
and	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
