<s>
A	O
delay-insensitive	B-General_Concept
circuit	O
is	O
a	O
type	O
of	O
asynchronous	B-Application
circuit	I-Application
which	O
performs	O
a	O
digital	O
logic	O
operation	O
often	O
within	O
a	O
computing	O
processor	O
chip	O
.	O
</s>
<s>
Instead	O
of	O
using	O
clock	O
signals	O
or	O
other	O
global	O
control	O
signals	O
,	O
the	O
sequencing	O
of	O
computation	O
in	O
delay-insensitive	B-General_Concept
circuit	O
is	O
determined	O
by	O
the	O
data	O
flow	O
.	O
</s>
<s>
In	O
a	O
delay-insensitive	B-General_Concept
circuit	O
,	O
there	O
is	O
therefore	O
no	O
need	O
to	O
provide	O
a	O
clock	O
signal	O
to	O
determine	O
a	O
starting	O
time	O
for	O
a	O
computation	O
.	O
</s>
<s>
An	O
example	O
of	O
a	O
process	O
with	O
a	O
variable	O
time	O
for	O
completion	O
would	O
be	O
mathematical	O
division	O
or	O
recovery	O
of	O
data	O
where	O
such	O
data	O
might	O
be	O
in	O
a	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
Delay-Insensitive	B-General_Concept
(	O
DI	O
)	O
class	O
is	O
the	O
most	O
robust	O
of	O
all	O
asynchronous	B-Application
circuit	I-Application
delay	O
models	O
.	O
</s>
<s>
Instead	O
the	O
Quasi-Delay-Insensitive	O
model	O
is	O
the	O
smallest	O
compromise	O
model	O
yet	O
capable	O
of	O
generating	O
useful	O
computing	O
circuits	O
.	O
</s>
<s>
For	O
this	O
reason	O
circuits	O
are	O
often	O
incorrectly	O
referred	O
to	O
as	O
Delay-Insensitive	B-General_Concept
when	O
they	O
are	O
Quasi	O
Delay-Insensitive	B-General_Concept
.	O
</s>
