<s>
In	O
computer	O
engineering	O
,	O
out-of-order	O
execution	O
(	O
or	O
more	O
formally	O
dynamic	O
execution	O
)	O
is	O
a	O
paradigm	O
used	O
in	O
most	O
high-performance	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
to	O
make	O
use	O
of	O
instruction	B-General_Concept
cycles	I-General_Concept
that	O
would	O
otherwise	O
be	O
wasted	O
.	O
</s>
<s>
In	O
this	O
paradigm	O
,	O
a	O
processor	O
executes	O
instructions	B-General_Concept
in	O
an	O
order	O
governed	O
by	O
the	O
availability	O
of	O
input	O
data	O
and	O
execution	B-General_Concept
units	I-General_Concept
,	O
rather	O
than	O
by	O
their	O
original	O
order	O
in	O
a	O
program	O
.	O
</s>
<s>
In	O
doing	O
so	O
,	O
the	O
processor	O
can	O
avoid	O
being	O
idle	O
while	O
waiting	O
for	O
the	O
preceding	O
instruction	O
to	O
complete	O
and	O
can	O
,	O
in	O
the	O
meantime	O
,	O
process	O
the	O
next	O
instructions	B-General_Concept
that	O
are	O
able	O
to	O
run	O
immediately	O
and	O
independently	O
.	O
</s>
<s>
Out-of-order	O
execution	O
is	O
a	O
restricted	O
form	O
of	O
data	B-General_Concept
flow	I-General_Concept
computation	O
,	O
which	O
was	O
a	O
major	O
research	O
area	O
in	O
computer	B-General_Concept
architecture	I-General_Concept
in	O
the	O
1970s	O
and	O
early	O
1980s	O
.	O
</s>
<s>
The	O
first	O
machine	O
to	O
use	O
out-of-order	O
execution	O
was	O
the	O
CDC	B-Device
6600	I-Device
(	O
1964	O
)	O
,	O
designed	O
by	O
James	O
E	O
.	O
Thornton	O
,	O
which	O
uses	O
a	O
scoreboard	B-General_Concept
to	O
avoid	O
conflicts	O
.	O
</s>
<s>
The	O
6600	O
lacks	O
the	O
means	O
to	O
avoid	O
stalling	O
an	O
execution	B-General_Concept
unit	I-General_Concept
on	O
false	O
dependencies	O
(	O
write	O
after	O
write	O
(	O
WAW	O
)	O
and	O
write	O
after	O
read	O
(	O
WAR	O
)	O
conflicts	O
,	O
respectively	O
termed	O
"	O
first	O
order	O
conflict	O
"	O
and	O
"	O
third	O
order	O
conflict	O
"	O
by	O
Thornton	O
,	O
who	O
termed	O
true	O
dependencies	O
(	O
read	O
after	O
write	O
(	O
RAW	O
)	O
)	O
as	O
"	O
second	O
order	O
conflict	O
"	O
)	O
because	O
each	O
address	O
has	O
only	O
a	O
single	O
location	O
referable	O
by	O
it	O
.	O
</s>
<s>
The	O
WAW	O
is	O
worse	O
than	O
WAR	O
for	O
the	O
6600	O
,	O
because	O
when	O
an	O
execution	B-General_Concept
unit	I-General_Concept
encounters	O
a	O
WAR	O
,	O
the	O
other	O
execution	B-General_Concept
units	I-General_Concept
still	O
receive	O
and	O
execute	O
instructions	B-General_Concept
,	O
but	O
upon	O
a	O
WAW	O
the	O
assignment	O
of	O
instructions	B-General_Concept
to	O
execution	B-General_Concept
units	I-General_Concept
stops	O
,	O
and	O
they	O
can	O
not	O
receive	O
any	O
further	O
instructions	B-General_Concept
until	O
the	O
WAW-causing	O
instruction	O
's	O
destination	O
register	O
has	O
been	O
written	O
to	O
by	O
earlier	O
instruction	O
.	O
</s>
<s>
About	O
two	O
years	O
later	O
,	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
(	O
1966	O
)	O
introduced	O
register	B-Architecture
renaming	I-Architecture
with	O
Tomasulo	B-General_Concept
's	I-General_Concept
algorithm	I-General_Concept
,	O
which	O
dissolves	O
false	O
dependencies	O
(	O
WAW	O
and	O
WAR	O
)	O
,	O
making	O
full	O
out-of-order	O
execution	O
possible	O
.	O
</s>
<s>
An	O
instruction	O
addressing	O
a	O
write	O
into	O
a	O
register	O
rn	O
can	O
be	O
executed	O
before	O
an	O
earlier	O
instruction	O
using	O
the	O
register	O
rn	O
is	O
executed	O
,	O
by	O
actually	O
writing	O
into	O
an	O
alternative	O
(	O
renamed	O
)	O
register	O
alt-rn	O
,	O
which	O
is	O
turned	O
into	O
a	O
normal	O
(	O
"	O
architectural	O
"	O
)	O
register	O
rn	O
only	O
when	O
all	O
the	O
earlier	O
instructions	B-General_Concept
addressing	O
rn	O
have	O
been	O
executed	O
,	O
but	O
until	O
then	O
rn	O
is	O
given	O
for	O
earlier	O
instructions	B-General_Concept
and	O
alt-rn	O
for	O
later	O
ones	O
addressing	O
rn	O
.	O
</s>
<s>
In	O
the	O
Model	O
91	O
the	O
register	B-Architecture
renaming	I-Architecture
is	O
implemented	O
by	O
a	O
bypass	B-General_Concept
termed	O
Common	O
Data	O
Bus	O
(	O
CDB	O
)	O
and	O
memory	B-General_Concept
source	O
operand	O
buffers	B-General_Concept
,	O
leaving	O
the	O
physical	O
architectural	O
registers	O
unused	O
for	O
many	O
cycles	O
as	O
the	O
oldest	O
state	O
of	O
registers	O
addressed	O
by	O
any	O
unexecuted	O
instruction	O
is	O
found	O
on	O
the	O
CDB	O
.	O
</s>
<s>
Another	O
advantage	O
the	O
Model	O
91	O
has	O
over	O
the	O
6600	O
is	O
the	O
ability	O
to	O
execute	O
out-of-order	O
the	O
instructions	B-General_Concept
at	O
the	O
same	O
execution	B-General_Concept
unit	I-General_Concept
,	O
not	O
just	O
between	O
the	O
units	O
like	O
the	O
6600	O
.	O
</s>
<s>
This	O
is	O
accomplished	O
by	O
reservation	B-General_Concept
stations	I-General_Concept
,	O
from	O
which	O
instructions	B-General_Concept
go	O
to	O
the	O
execution	B-General_Concept
unit	I-General_Concept
when	O
ready	O
,	O
as	O
opposed	O
to	O
the	O
FIFO	B-Operating_System
queue	O
of	O
each	O
execution	B-General_Concept
unit	I-General_Concept
of	O
the	O
6600	O
.	O
</s>
<s>
Only	O
the	O
floating-point	O
registers	O
of	O
the	O
Model	O
91	O
are	O
renamed	O
,	O
making	O
it	O
subject	O
to	O
the	O
same	O
WAW	O
and	O
WAR	O
limitations	O
as	O
the	O
CDC	B-Device
6600	I-Device
when	O
running	O
fixed-point	O
code	O
.	O
</s>
<s>
The	O
CDC	O
Cyber	O
205	O
was	O
a	O
precursor	O
,	O
as	O
upon	O
a	O
virtual	B-Architecture
memory	I-Architecture
interrupt	O
the	O
entire	O
state	O
of	O
the	O
processor	O
(	O
including	O
the	O
information	O
on	O
the	O
partially	O
executed	O
instructions	B-General_Concept
)	O
is	O
saved	O
into	O
an	O
invisible	O
exchange	O
package	O
,	O
so	O
that	O
it	O
can	O
resume	O
at	O
the	O
same	O
state	O
of	O
execution	O
.	O
</s>
<s>
However	O
to	O
make	O
all	O
exceptions	O
precise	O
,	O
there	O
has	O
to	O
be	O
a	O
way	O
to	O
cancel	O
the	O
effects	O
of	O
instructions	B-General_Concept
.	O
</s>
<s>
The	O
CDC	O
Cyber	O
990	O
(	O
1984	O
)	O
implements	O
precise	O
interrupts	O
by	O
using	O
a	O
history	O
buffer	B-General_Concept
,	O
which	O
holds	O
the	O
old	O
(	O
overwritten	O
)	O
values	O
of	O
registers	O
that	O
are	O
restored	O
when	O
an	O
exception	O
necessitates	O
the	O
reverting	O
of	O
instructions	B-General_Concept
.	O
</s>
<s>
Smith	O
simulated	O
that	O
adding	O
a	O
reorder	B-General_Concept
buffer	I-General_Concept
(	O
or	O
history	O
buffer	B-General_Concept
or	O
equivalent	O
)	O
to	O
Cray-1S	B-Device
would	O
reduce	O
the	O
performance	O
of	O
executing	O
the	O
first	O
14	O
Livermore	B-Operating_System
loops	I-Operating_System
(	O
unvectorized	O
)	O
by	O
only	O
3%	O
.	O
</s>
<s>
In	O
the	O
1980s	O
many	O
early	O
RISC	B-Architecture
microprocessors	B-Architecture
,	O
like	O
the	O
Motorola	B-General_Concept
88100	I-General_Concept
,	O
had	O
out-of-order	O
writeback	O
to	O
the	O
registers	O
,	O
resulting	O
in	O
imprecise	O
exceptions	O
.	O
</s>
<s>
Instructions	B-General_Concept
started	O
execution	O
in	O
order	O
,	O
but	O
some	O
(	O
e.g.	O
</s>
<s>
However	O
the	O
single-cycle	O
execution	O
of	O
the	O
most	O
basic	O
instructions	B-General_Concept
greatly	O
reduced	O
the	O
scope	O
of	O
the	O
problem	O
compared	O
to	O
the	O
CDC	B-Device
6600	I-Device
.	O
</s>
<s>
Smith	O
also	O
researched	O
how	O
to	O
make	O
different	O
execution	B-General_Concept
units	I-General_Concept
operate	O
more	O
independently	O
of	O
each	O
other	O
and	O
of	O
the	O
memory	B-General_Concept
,	O
front-end	O
,	O
and	O
branching	O
.	O
</s>
<s>
He	O
implemented	O
those	O
ideas	O
in	O
the	O
Astronautics	O
ZS-1	O
(	O
1988	O
)	O
,	O
featuring	O
a	O
decoupling	O
of	O
the	O
integer/load/store	O
pipeline	B-General_Concept
from	O
the	O
floating-point	O
pipeline	B-General_Concept
,	O
allowing	O
inter-pipeline	O
re-ordering	O
.	O
</s>
<s>
In	O
his	O
1984	O
paper	O
he	O
opined	O
that	O
enforcing	O
the	O
precise	O
exceptions	O
only	O
on	O
the	O
integer/memory	O
pipeline	B-General_Concept
should	O
be	O
sufficient	O
for	O
many	O
usecases	O
,	O
as	O
it	O
even	O
permits	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Each	O
pipeline	B-General_Concept
had	O
an	O
instruction	O
buffer	B-General_Concept
to	O
decouple	O
it	O
from	O
the	O
instruction	O
decoder	O
,	O
to	O
prevent	O
the	O
stalling	O
of	O
the	O
front-end	O
.	O
</s>
<s>
To	O
further	O
decouple	O
the	O
memory	B-General_Concept
access	O
from	O
execution	O
,	O
each	O
of	O
the	O
two	O
pipelines	B-General_Concept
was	O
associated	O
with	O
two	O
addressable	O
queues	B-Operating_System
that	O
effectively	O
performed	O
limited	O
register	B-Architecture
renaming	I-Architecture
.	O
</s>
<s>
A	O
similar	O
decoupled	B-General_Concept
architecture	I-General_Concept
had	O
been	O
used	O
a	O
bit	O
earlier	O
in	O
the	O
Culler	O
7	O
.	O
</s>
<s>
With	O
the	O
POWER1	B-General_Concept
(	O
1990	O
)	O
IBM	O
returned	O
to	O
out-of-order	O
execution	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
processor	O
to	O
combine	O
register	B-Architecture
renaming	I-Architecture
(	O
though	O
again	O
only	O
floating-point	O
registers	O
)	O
with	O
precise	O
exceptions	O
.	O
</s>
<s>
It	O
uses	O
a	O
physical	B-General_Concept
register	I-General_Concept
file	I-General_Concept
(	O
i.e.	O
</s>
<s>
a	O
dynamically	O
remapped	O
file	O
with	O
both	O
uncommitted	O
and	O
committed	O
values	O
)	O
instead	O
of	O
a	O
datafull	O
reorder	B-General_Concept
buffer	I-General_Concept
,	O
but	O
the	O
ability	O
to	O
cancel	O
instructions	B-General_Concept
is	O
needed	O
only	O
in	O
the	O
branch	O
unit	O
,	O
which	O
implements	O
a	O
history	O
buffer	B-General_Concept
(	O
named	O
program	O
counter	O
stack	O
by	O
IBM	O
)	O
to	O
undo	O
changes	O
to	O
count	O
,	O
link	O
,	O
and	O
condition	O
registers	O
.	O
</s>
<s>
The	O
reordering	O
capability	O
of	O
even	O
the	O
floating-point	O
instructions	B-General_Concept
is	O
still	O
very	O
limited	O
;	O
due	O
to	O
POWER1	B-General_Concept
's	O
inability	O
to	O
reorder	O
floating-point	O
arithmetic	O
instructions	B-General_Concept
(	O
results	O
became	O
available	O
in-order	O
)	O
,	O
their	O
destination	O
registers	O
are	O
n't	O
renamed	O
.	O
</s>
<s>
POWER1	B-General_Concept
also	O
does	O
n't	O
have	O
reservation	B-General_Concept
stations	I-General_Concept
needed	O
for	O
out-of-order	O
use	O
of	O
a	O
same	O
execution	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
next	O
year	O
IBM	O
's	O
ES/9000	B-Device
model	O
900	O
had	O
register	B-Architecture
renaming	I-Architecture
also	O
for	O
the	O
general-purpose	O
registers	O
.	O
</s>
<s>
It	O
also	O
has	O
reservation	B-General_Concept
stations	I-General_Concept
with	O
six	O
entries	O
for	O
the	O
dual	O
integer	O
unit	O
(	O
each	O
cycle	O
,	O
from	O
the	O
six	O
instructions	B-General_Concept
up	O
to	O
two	O
can	O
be	O
selected	O
and	O
then	O
executed	O
)	O
and	O
six	O
entries	O
for	O
the	O
FPU	O
.	O
</s>
<s>
Other	O
units	O
have	O
simple	O
FIFO	B-Operating_System
queues	B-Operating_System
.	O
</s>
<s>
The	O
re-ordering	O
distance	O
is	O
up	O
to	O
32	O
instructions	B-General_Concept
.	O
</s>
<s>
The	O
A19	O
of	O
Unisys	O
 '	O
A-series	B-Device
of	I-Device
mainframes	I-Device
was	O
also	O
released	O
in	O
1991	O
and	O
was	O
claimed	O
to	O
have	O
out-of-order	O
execution	O
,	O
and	O
one	O
analyst	O
called	O
the	O
A19	O
's	O
technology	O
three	O
to	O
five	O
years	O
ahead	O
of	O
the	O
competition	O
.	O
</s>
<s>
The	O
first	O
superscalar	B-General_Concept
single-chip	B-Architecture
processors	I-Architecture
(	O
Intel	O
i960CA	O
in	O
1989	O
)	O
used	O
a	O
simple	O
scoreboarding	B-General_Concept
scheduling	O
like	O
the	O
CDC	B-Device
6600	I-Device
had	O
quarter	O
of	O
a	O
century	O
earlier	O
,	O
but	O
in	O
1992-1996	O
a	O
rapid	O
advancement	O
of	O
techniques	O
,	O
enabled	O
by	O
increasing	O
transistor	O
counts	O
,	O
saw	O
proliferation	O
down	O
to	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
Motorola	B-Device
88110	I-Device
(	O
1992	O
)	O
used	O
a	O
history	O
buffer	B-General_Concept
to	O
revert	O
instructions	B-General_Concept
.	O
</s>
<s>
While	O
stores	O
and	O
branches	O
were	O
waiting	O
to	O
start	O
execution	O
,	O
subsequent	O
instructions	B-General_Concept
of	O
other	O
types	O
could	O
keep	O
flowing	O
through	O
all	O
the	O
pipeline	B-General_Concept
stages	O
,	O
including	O
writeback	O
.	O
</s>
<s>
The	O
12-entry	O
capacity	O
of	O
the	O
history	O
buffer	B-General_Concept
placed	O
a	O
limit	O
on	O
the	O
reorder	O
distance	O
.	O
</s>
<s>
PowerPC	B-Architecture
601	O
(	O
1993	O
)	O
was	O
an	O
evolution	O
of	O
the	O
RISC	B-Device
Single	I-Device
Chip	I-Device
,	O
itself	O
a	O
simplification	O
of	O
POWER1	B-General_Concept
.	O
</s>
<s>
The	O
601	O
permitted	O
branch	O
and	O
floating-point	O
instructions	B-General_Concept
to	O
overtake	O
the	O
integer	O
instructions	B-General_Concept
already	O
in	O
the	O
fetched-instruction-queue	O
,	O
the	O
lowest	O
four	O
entries	O
of	O
which	O
were	O
scanned	O
for	O
dispatchability	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	O
cache	B-General_Concept
miss	O
,	O
loads	O
and	O
stores	O
could	O
be	O
reordered	O
.	O
</s>
<s>
NexGen	O
's	O
Nx586	O
was	O
the	O
first	O
x86	B-Operating_System
processor	O
capable	O
of	O
out-of-order	O
execution	O
,	O
accomplished	O
with	O
micro-OPs	B-General_Concept
.	O
</s>
<s>
The	O
re-ordering	O
distance	O
is	O
up	O
to	O
14	O
micro-OPs	B-General_Concept
.	O
</s>
<s>
PowerPC	B-Architecture
603	O
renamed	O
both	O
the	O
general-purpose	O
and	O
FP	O
registers	O
.	O
</s>
<s>
Each	O
of	O
the	O
four	O
non-branch	O
execution	B-General_Concept
units	I-General_Concept
can	O
have	O
one	O
instruction	O
wait	O
in	O
front	O
of	O
it	O
without	O
blocking	O
the	O
instruction	O
flow	O
to	O
the	O
other	O
units	O
.	O
</s>
<s>
A	O
five-entry	O
re-order	B-General_Concept
buffer	I-General_Concept
lets	O
no	O
more	O
than	O
four	O
instructions	B-General_Concept
to	O
overtake	O
an	O
unexecuted	O
instruction	O
.	O
</s>
<s>
Due	O
to	O
a	O
store	O
buffer	B-General_Concept
,	O
a	O
load	O
can	O
access	O
cache	B-General_Concept
ahead	O
of	O
a	O
preceding	O
store	O
.	O
</s>
<s>
PowerPC	B-Architecture
604	O
(	O
1995	O
)	O
was	O
the	O
first	O
single-chip	O
processor	O
with	O
execution	O
unit-level	O
re-ordering	O
,	O
as	O
three	O
out	O
of	O
its	O
six	O
units	O
each	O
had	O
a	O
two-entry	O
reservation	B-General_Concept
station	I-General_Concept
permitting	O
the	O
newer	O
entry	O
to	O
execute	O
before	O
the	O
older	O
.	O
</s>
<s>
The	O
re-order	B-General_Concept
buffer	I-General_Concept
capacity	O
is	O
16	O
instructions	B-General_Concept
.	O
</s>
<s>
A	O
four-entry	O
load	O
queue	O
and	O
a	O
six-entry	O
store	O
queue	O
track	O
the	O
re-ordering	O
of	O
loads	O
and	O
stores	O
upon	O
cache	B-General_Concept
misses	O
.	O
</s>
<s>
HAL	B-General_Concept
SPARC64	I-General_Concept
(	O
1995	O
)	O
exceeded	O
the	O
re-ordering	O
capacity	O
of	O
the	O
ES/9000	B-Device
model	O
900	O
by	O
having	O
three	O
8-entry	O
reservation	B-General_Concept
stations	I-General_Concept
for	O
integer	O
,	O
floating-point	O
,	O
and	O
address	B-General_Concept
generation	I-General_Concept
unit	I-General_Concept
,	O
and	O
a	O
12-entry	O
reservation	B-General_Concept
station	I-General_Concept
for	O
load/store	O
,	O
which	O
permits	O
greater	O
reordering	O
of	O
cache/memory	O
access	O
than	O
preceding	O
processors	O
.	O
</s>
<s>
Up	O
to	O
64	O
instructions	B-General_Concept
can	O
be	O
in	O
a	O
re-ordered	O
state	O
at	O
a	O
time	O
Pentium	B-Device
Pro	I-Device
(	O
1995	O
)	O
introduced	O
a	O
unified	B-General_Concept
reservation	I-General_Concept
station	I-General_Concept
,	O
which	O
at	O
the	O
20	O
micro-OP	B-General_Concept
capacity	O
permitted	O
very	O
flexible	O
re-ordering	O
,	O
backed	O
by	O
a	O
40-entry	O
re-order	B-General_Concept
buffer	I-General_Concept
.	O
</s>
<s>
The	O
practically	O
attainable	O
per-cycle	O
rate	O
of	O
execution	O
rose	O
more	O
as	O
full	O
out-of-order	O
execution	O
was	O
further	O
adopted	O
by	O
SGI/MIPS	O
(	O
R10000	B-General_Concept
)	O
and	O
HP	B-Device
PA-RISC	I-Device
(	O
PA-8000	B-General_Concept
)	O
in	O
1996	O
.	O
</s>
<s>
The	O
same	O
year	O
Cyrix	B-General_Concept
6x86	I-General_Concept
and	O
AMD	O
K5	O
brought	O
advanced	O
re-ordering	O
techniques	O
into	O
mainstream	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
Since	O
DEC	B-Device
Alpha	I-Device
gained	O
out-of-order	O
execution	O
in	O
1998	O
(	O
Alpha	B-General_Concept
21264	I-General_Concept
)	O
,	O
the	O
top-performing	O
out-of-order	O
processor	O
cores	O
have	O
been	O
unmatched	O
by	O
in-order	O
cores	O
other	O
than	O
HP/Intel	O
Itanium	O
2	O
and	O
IBM	O
POWER6	B-Device
,	O
though	O
the	O
latter	O
had	O
an	O
out-of-order	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
other	O
high-end	O
in-order	O
processors	O
fell	O
far	O
behind	O
,	O
namely	O
Sun	O
's	O
UltraSPARC	O
III/IV	O
,	O
and	O
IBM	O
's	O
mainframes	B-Architecture
which	O
had	O
lost	O
the	O
out-of-order	O
execution	O
capability	O
for	O
the	O
second	O
time	O
,	O
remaining	O
in-order	O
into	O
the	O
z10	B-Device
generation	O
.	O
</s>
<s>
Later	O
big	O
in-order	O
processors	O
were	O
focused	O
on	O
multithreaded	O
performance	O
,	O
but	O
eventually	O
the	O
SPARC	B-Architecture
T	I-Architecture
series	I-Architecture
and	O
Xeon	B-General_Concept
Phi	I-General_Concept
changed	O
to	O
out-of-order	O
execution	O
in	O
2011	O
and	O
2016	O
respectively	O
.	O
</s>
<s>
First	O
,	O
Qualcomm	O
's	O
Scorpion	B-Application
(	O
re-ordering	O
distance	O
of	O
32	O
)	O
shipped	O
in	O
Snapdragon	B-Architecture
,	O
and	O
a	O
bit	O
later	O
Arm	O
's	O
A9	B-Application
succeeded	O
A8	B-Application
.	O
</s>
<s>
For	O
low-end	O
x86	B-Operating_System
personal	B-Device
computers	I-Device
in-order	B-Device
early	I-Device
Intel	I-Device
Atoms	I-Device
were	O
first	O
challenged	O
by	O
AMD	O
's	O
Bobcat	O
,	O
and	O
in	O
2013	O
were	O
succeeded	O
by	O
an	O
out-of-order	O
Silvermont	B-Device
.	O
</s>
<s>
Because	O
the	O
complexity	O
of	O
out-of-order	O
execution	O
precludes	O
achieving	O
the	O
lowest	O
minimum	O
power	O
consumption	O
,	O
cost	O
and	O
size	O
,	O
in-order	O
execution	O
is	O
still	O
prevalent	O
in	O
microcontrollers	B-Architecture
and	O
embedded	B-Architecture
systems	I-Architecture
,	O
as	O
well	O
as	O
in	O
phone-class	O
cores	O
such	O
as	O
Arm	O
's	O
A55	O
and	O
A510	O
in	O
big.LITTLE	B-Architecture
configurations	O
.	O
</s>
<s>
Instructions	B-General_Concept
cannot	O
be	O
completed	O
instantaneously	O
:	O
they	O
take	O
time	O
(	O
multiple	O
cycles	O
)	O
.	O
</s>
<s>
In	O
earlier	O
processors	O
,	O
the	O
processing	O
of	O
instructions	B-General_Concept
is	O
performed	O
in	O
an	O
instruction	B-General_Concept
cycle	I-General_Concept
normally	O
consisting	O
of	O
the	O
following	O
steps	O
:	O
</s>
<s>
Instruction	O
fetch	B-General_Concept
.	O
</s>
<s>
If	O
input	O
operands	O
are	O
available	O
(	O
in	O
processor	O
registers	O
,	O
for	O
instance	O
)	O
,	O
the	O
instruction	O
is	O
dispatched	O
to	O
the	O
appropriate	O
functional	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
If	O
one	O
or	O
more	O
operands	O
are	O
unavailable	O
during	O
the	O
current	O
clock	O
cycle	O
(	O
generally	O
because	O
they	O
are	O
being	O
fetched	O
from	O
memory	B-General_Concept
)	O
,	O
the	O
processor	O
stalls	O
until	O
they	O
are	O
available	O
.	O
</s>
<s>
The	O
instruction	O
is	O
executed	O
by	O
the	O
appropriate	O
functional	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
functional	B-General_Concept
unit	I-General_Concept
writes	O
the	O
results	O
back	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
Often	O
,	O
an	O
in-order	O
processor	O
has	O
a	O
"	O
bit	B-Data_Structure
vector	I-Data_Structure
"	O
recording	O
which	O
registers	O
will	O
be	O
written	O
to	O
by	O
a	O
pipeline	B-General_Concept
.	O
</s>
<s>
This	O
new	O
paradigm	O
breaks	O
up	O
the	O
processing	O
of	O
instructions	B-General_Concept
into	O
these	O
steps	O
:	O
</s>
<s>
Instruction	O
fetch	B-General_Concept
.	O
</s>
<s>
Instruction	O
dispatch	O
to	O
an	O
instruction	O
queue	O
(	O
also	O
called	O
instruction	O
buffer	B-General_Concept
or	O
reservation	B-General_Concept
stations	I-General_Concept
)	O
.	O
</s>
<s>
The	O
instruction	O
can	O
leave	O
the	O
queue	O
before	O
older	O
instructions	B-General_Concept
.	O
</s>
<s>
The	O
instruction	O
is	O
issued	O
to	O
the	O
appropriate	O
functional	B-General_Concept
unit	I-General_Concept
and	O
executed	O
by	O
that	O
unit	O
.	O
</s>
<s>
Only	O
after	O
all	O
older	O
instructions	B-General_Concept
have	O
their	O
results	O
written	O
back	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
,	O
then	O
this	O
result	O
is	O
written	O
back	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
OoOE	O
processors	O
fill	O
these	O
"	O
slots	O
"	O
in	O
time	O
with	O
other	O
instructions	B-General_Concept
that	O
are	O
ready	O
,	O
then	O
re-order	O
the	O
results	O
at	O
the	O
end	O
to	O
make	O
it	O
appear	O
that	O
the	O
instructions	B-General_Concept
were	O
processed	O
as	O
normal	O
.	O
</s>
<s>
The	O
way	O
the	O
instructions	B-General_Concept
are	O
ordered	O
in	O
the	O
original	O
computer	O
code	O
is	O
known	O
as	O
program	O
order	O
,	O
in	O
the	O
processor	O
they	O
are	O
handled	O
in	O
data	O
order	O
,	O
the	O
order	O
in	O
which	O
the	O
data	O
,	O
operands	O
,	O
become	O
available	O
in	O
the	O
processor	O
's	O
registers	O
.	O
</s>
<s>
Fairly	O
complex	O
circuitry	O
is	O
needed	O
to	O
convert	O
from	O
one	O
ordering	O
to	O
the	O
other	O
and	O
maintain	O
a	O
logical	O
ordering	O
of	O
the	O
output	O
;	O
the	O
processor	O
itself	O
runs	O
the	O
instructions	B-General_Concept
in	O
seemingly	O
random	O
order	O
.	O
</s>
<s>
The	O
benefit	O
of	O
OoOE	O
processing	O
grows	O
as	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
deepens	O
and	O
the	O
speed	O
difference	O
between	O
main	O
memory	B-General_Concept
(	O
or	O
cache	B-General_Concept
memory	I-General_Concept
)	O
and	O
the	O
processor	O
widens	O
.	O
</s>
<s>
On	O
modern	O
machines	O
,	O
the	O
processor	O
runs	O
many	O
times	O
faster	O
than	O
the	O
memory	B-General_Concept
,	O
so	O
during	O
the	O
time	O
an	O
in-order	O
processor	O
spends	O
waiting	O
for	O
data	O
to	O
arrive	O
,	O
it	O
could	O
have	O
processed	O
a	O
large	O
number	O
of	O
instructions	B-General_Concept
.	O
</s>
<s>
One	O
of	O
the	O
differences	O
created	O
by	O
the	O
new	O
paradigm	O
is	O
the	O
creation	O
of	O
queues	B-Operating_System
that	O
allows	O
the	O
dispatch	O
step	O
to	O
be	O
decoupled	O
from	O
the	O
issue	O
step	O
and	O
the	O
graduation	O
stage	O
to	O
be	O
decoupled	O
from	O
the	O
execute	O
stage	O
.	O
</s>
<s>
An	O
early	O
name	O
for	O
the	O
paradigm	O
was	O
decoupled	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
In	O
the	O
earlier	O
in-order	O
processors	O
,	O
these	O
stages	O
operated	O
in	O
a	O
fairly	O
lock-step	B-General_Concept
,	O
pipelined	B-General_Concept
fashion	O
.	O
</s>
<s>
The	O
instructions	B-General_Concept
of	O
the	O
program	O
may	O
not	O
be	O
run	O
in	O
the	O
originally	O
specified	O
order	O
,	O
as	O
long	O
as	O
the	O
end	O
result	O
is	O
correct	O
.	O
</s>
<s>
It	O
separates	O
the	O
fetch	B-General_Concept
and	I-General_Concept
decode	I-General_Concept
stages	I-General_Concept
from	O
the	O
execute	O
stage	O
in	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
by	O
using	O
a	O
buffer	B-General_Concept
.	O
</s>
<s>
The	O
buffer	B-General_Concept
's	O
purpose	O
is	O
to	O
partition	O
the	O
memory	B-General_Concept
access	O
and	O
execute	O
functions	O
in	O
a	O
computer	O
program	O
and	O
achieve	O
high-performance	O
by	O
exploiting	O
the	O
fine-grain	O
parallelism	B-Operating_System
between	O
the	O
two	O
.	O
</s>
<s>
In	O
doing	O
so	O
,	O
it	O
effectively	O
hides	O
all	O
memory	B-General_Concept
latency	I-General_Concept
from	O
the	O
processor	O
's	O
perspective	O
.	O
</s>
<s>
A	O
larger	O
buffer	B-General_Concept
can	O
,	O
in	O
theory	O
,	O
increase	O
throughput	O
.	O
</s>
<s>
However	O
,	O
if	O
the	O
processor	O
has	O
a	O
branch	B-General_Concept
misprediction	I-General_Concept
then	O
the	O
entire	O
buffer	B-General_Concept
may	O
need	O
to	O
be	O
flushed	O
,	O
wasting	O
a	O
lot	O
of	O
clock	O
cycles	O
and	O
reducing	O
the	O
effectiveness	O
.	O
</s>
<s>
Furthermore	O
,	O
larger	O
buffers	B-General_Concept
create	O
more	O
heat	O
and	O
use	O
more	O
die	O
space	O
.	O
</s>
<s>
For	O
this	O
reason	O
processor	O
designers	O
today	O
favour	O
a	O
multi-threaded	B-Operating_System
design	O
approach	O
.	O
</s>
<s>
Decoupled	B-General_Concept
architectures	I-General_Concept
are	O
generally	O
thought	O
of	O
as	O
not	O
useful	O
for	O
general	O
purpose	O
computing	O
as	O
they	O
do	O
not	O
handle	O
control	O
intensive	O
code	O
well	O
.	O
</s>
<s>
Control	O
intensive	O
code	O
include	O
such	O
things	O
as	O
nested	O
branches	O
that	O
occur	O
frequently	O
in	O
operating	B-Operating_System
system	I-Operating_System
kernels	I-Operating_System
.	O
</s>
<s>
Decoupled	B-General_Concept
architectures	I-General_Concept
play	O
an	O
important	O
role	O
in	O
scheduling	O
in	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
architectures	O
.	O
</s>
<s>
To	O
avoid	O
false	O
operand	O
dependencies	O
,	O
which	O
would	O
decrease	O
the	O
frequency	O
when	O
instructions	B-General_Concept
could	O
be	O
issued	O
out	O
of	O
order	O
,	O
a	O
technique	O
called	O
register	B-Architecture
renaming	I-Architecture
is	O
used	O
.	O
</s>
<s>
The	O
queue	O
for	O
results	O
is	O
necessary	O
to	O
resolve	O
issues	O
such	O
as	O
branch	B-General_Concept
mispredictions	I-General_Concept
and	O
exceptions/traps	O
.	O
</s>
<s>
The	O
results	O
queue	O
allows	O
programs	O
to	O
be	O
restarted	O
after	O
an	O
exception	O
,	O
which	O
requires	O
the	O
instructions	B-General_Concept
to	O
be	O
completed	O
in	O
program	O
order	O
.	O
</s>
<s>
The	O
queue	O
allows	O
results	O
to	O
be	O
discarded	O
due	O
to	O
mispredictions	O
on	O
older	O
branch	O
instructions	B-General_Concept
and	O
exceptions	O
taken	O
on	O
older	O
instructions	B-General_Concept
.	O
</s>
<s>
The	O
ability	O
to	O
issue	O
instructions	B-General_Concept
past	O
branches	O
that	O
are	O
yet	O
to	O
resolve	O
is	O
known	O
as	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
Are	O
the	O
instructions	B-General_Concept
dispatched	O
to	O
a	O
centralized	O
queue	O
or	O
to	O
multiple	O
distributed	O
queues	B-Operating_System
?	O
</s>
<s>
IBM	B-Architecture
PowerPC	I-Architecture
processors	O
use	O
queues	B-Operating_System
that	O
are	O
distributed	O
among	O
the	O
different	O
functional	B-General_Concept
units	I-General_Concept
while	O
other	O
out-of-order	O
processors	O
use	O
a	O
centralized	O
queue	O
.	O
</s>
<s>
IBM	O
uses	O
the	O
term	O
reservation	B-General_Concept
stations	I-General_Concept
for	O
their	O
distributed	O
queues	B-Operating_System
.	O
</s>
<s>
Is	O
there	O
an	O
actual	O
results	O
queue	O
or	O
are	O
the	O
results	O
written	O
directly	O
into	O
a	O
register	B-General_Concept
file	I-General_Concept
?	O
</s>
<s>
For	O
the	O
latter	O
,	O
the	O
queueing	O
function	O
is	O
handled	O
by	O
register	O
maps	O
that	O
hold	O
the	O
register	B-Architecture
renaming	I-Architecture
information	O
for	O
each	O
instruction	O
in	O
flight	O
.	O
</s>
<s>
Early	O
Intel	O
out-of-order	O
processors	O
use	O
a	O
results	O
queue	O
called	O
a	O
re-order	B-General_Concept
buffer	I-General_Concept
,	O
while	O
most	O
later	O
out-of-order	O
processors	O
use	O
register	O
maps	O
.	O
</s>
<s>
More	O
precisely	O
:	O
Intel	B-Device
P6	I-Device
family	O
microprocessors	B-Architecture
have	O
both	O
a	O
re-order	B-General_Concept
buffer	I-General_Concept
(	O
ROB	O
)	O
and	O
a	O
register	B-Architecture
alias	I-Architecture
table	I-Architecture
(	O
RAT	O
)	O
.	O
</s>
<s>
The	O
ROB	O
was	O
motivated	O
mainly	O
by	O
branch	B-General_Concept
misprediction	I-General_Concept
recovery	O
.	O
</s>
<s>
The	O
Intel	B-Device
P6	I-Device
family	O
is	O
among	O
the	O
earliest	O
OoOE	O
microprocessors	B-Architecture
but	O
were	O
supplanted	O
by	O
the	O
NetBurst	B-Device
architecture	O
.	O
</s>
<s>
Years	O
later	O
,	O
NetBurst	B-Device
proved	O
to	O
be	O
a	O
dead	O
end	O
due	O
to	O
its	O
long	O
pipeline	B-General_Concept
that	O
assumed	O
the	O
possibility	O
of	O
much	O
higher	O
operating	O
frequencies	O
.	O
</s>
<s>
Materials	O
were	O
not	O
able	O
to	O
match	O
the	O
design	O
's	O
ambitious	O
clock	O
targets	O
due	O
to	O
thermal	O
issues	O
and	O
later	O
designs	O
based	O
on	O
NetBurst	B-Device
,	O
namely	O
Tejas	O
and	O
Jayhawk	O
,	O
were	O
cancelled	O
.	O
</s>
<s>
Intel	O
reverted	O
to	O
the	O
P6	B-Device
design	O
as	O
the	O
basis	O
of	O
the	O
Core	B-Device
and	O
Nehalem	B-Device
microarchitectures	I-Device
.	O
</s>
<s>
The	O
succeeding	O
Sandy	B-Device
Bridge	I-Device
,	O
Ivy	B-Device
Bridge	I-Device
,	O
and	O
Haswell	B-Device
microarchitectures	I-Device
are	O
a	O
departure	O
from	O
the	O
reordering	O
techniques	O
used	O
in	O
P6	B-Device
and	O
employ	O
re-ordering	O
techniques	O
from	O
the	O
EV6	B-General_Concept
and	O
the	O
P4	B-General_Concept
but	O
with	O
a	O
somewhat	O
shorter	O
pipeline	B-General_Concept
.	O
</s>
