<s>
The	O
Data	O
General	O
Nova	O
is	O
a	O
series	O
of	O
16-bit	B-Device
minicomputers	B-Architecture
released	O
by	O
the	O
American	O
company	O
Data	O
General	O
.	O
</s>
<s>
The	O
Nova	O
was	O
packaged	O
into	O
a	O
single	O
3U	O
rack-mount	B-Application
case	O
and	O
had	O
enough	O
computing	O
power	O
to	O
handle	O
most	O
simple	O
tasks	O
.	O
</s>
<s>
Fairchild	O
Semiconductor	O
also	O
introduced	O
a	O
microprocessor	O
version	O
of	O
the	O
Nova	O
in	O
1977	O
,	O
the	O
Fairchild	B-General_Concept
9440	I-General_Concept
,	O
but	O
it	O
also	O
saw	O
limited	O
use	O
in	O
the	O
market	O
.	O
</s>
<s>
The	O
Nova	O
line	O
was	O
succeeded	O
by	O
the	O
Data	B-Device
General	I-Device
Eclipse	I-Device
,	O
which	O
was	O
similar	O
in	O
most	O
ways	O
but	O
added	O
virtual	B-Architecture
memory	I-Architecture
support	O
and	O
other	O
features	O
required	O
by	O
modern	O
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
A	O
32-bit	O
upgrade	O
of	O
the	O
Eclipse	B-Device
resulted	O
in	O
the	O
Eclipse	B-Device
MV	I-Device
series	I-Device
of	O
the	O
1980s	O
.	O
</s>
<s>
Edson	O
de	O
Castro	O
was	O
the	O
Product	O
Manager	O
of	O
the	O
pioneering	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
PDP-8	B-Device
,	O
a	O
12-bit	O
computer	O
widely	O
referred	O
to	O
as	O
the	O
first	O
true	O
minicomputer	B-Architecture
.	O
</s>
<s>
He	O
also	O
led	O
the	O
design	O
of	O
the	O
upgraded	O
PDP-8/I	O
,	O
which	O
used	O
early	O
integrated	O
circuits	O
in	O
place	O
of	O
individual	O
transistors	O
.	O
</s>
<s>
During	O
the	O
PDP-8/I	O
process	O
,	O
de	O
Castro	O
had	O
been	O
visiting	O
circuit	O
board	O
manufacturers	O
who	O
were	O
making	O
rapid	O
advances	O
in	O
the	O
complexity	O
of	O
the	O
boards	O
they	O
could	O
assemble	O
.	O
</s>
<s>
For	O
the	O
8/I	O
,	O
the	O
decision	O
was	O
made	O
to	O
stay	O
with	O
small	O
boards	O
,	O
using	O
the	O
new	O
"	O
flip-chip	B-Device
"	O
packaging	O
for	O
a	O
modest	O
improvement	O
in	O
density	O
.	O
</s>
<s>
During	O
the	O
period	O
when	O
the	O
PDP-8	B-Device
was	O
being	O
developed	O
,	O
the	O
introduction	O
of	O
ASCII	B-Protocol
and	O
its	O
major	O
update	O
in	O
1967	O
led	O
to	O
a	O
new	O
generation	O
of	O
designs	O
with	O
word	O
lengths	O
that	O
were	O
multiples	O
of	O
8	O
bits	O
rather	O
than	O
multiples	O
of	O
6	O
bits	O
as	O
in	O
most	O
previous	O
designs	O
.	O
</s>
<s>
This	O
led	O
to	O
mid-range	O
designs	O
working	O
at	O
16-bit	B-Device
word	O
lengths	O
instead	O
of	O
DEC	O
's	O
current	O
12	O
-	O
and	O
18-bit	O
lineups	O
.	O
</s>
<s>
de	O
Castro	O
was	O
convinced	O
that	O
it	O
was	O
possible	O
to	O
improve	O
upon	O
the	O
PDP-8	B-Device
by	O
building	O
a	O
16-bit	B-Device
minicomputer	B-Architecture
CPU	O
on	O
a	O
single	O
15-inch	O
square	O
board	O
.	O
</s>
<s>
Ken	O
Olsen	O
was	O
not	O
supportive	O
of	O
this	O
project	O
,	O
feeling	O
it	O
did	O
not	O
offer	O
sufficient	O
advantages	O
over	O
the	O
12-bit	O
PDP-8	B-Device
and	O
the	O
18-bit	O
PDP-9	B-Device
.	O
</s>
<s>
The	O
group	O
began	O
talking	O
with	O
Herbert	O
Richman	O
,	O
a	O
salesman	O
for	O
Fairchild	O
Semiconductor	O
who	O
knew	O
the	O
others	O
through	O
his	O
contacts	O
with	O
DEC	O
.	O
At	O
the	O
time	O
,	O
Fairchild	O
was	O
battling	O
with	O
Texas	O
Instruments	O
and	O
Signetics	O
in	O
the	O
rapidly	O
growing	O
TTL	B-General_Concept
market	O
and	O
were	O
introducing	O
new	O
fabs	B-Architecture
that	O
allowed	O
more	O
complex	O
designs	O
.	O
</s>
<s>
Fairchild	O
's	O
latest	O
9300	O
series	O
allowed	O
up	O
to	O
96	O
gates	O
per	O
chip	O
,	O
and	O
they	O
had	O
used	O
this	O
to	O
implement	O
a	O
number	O
of	O
4-bit	O
chips	O
like	O
binary	O
counters	O
and	O
shift	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
Using	O
these	O
ICs	O
reduced	O
the	O
total	O
IC	O
count	O
needed	O
to	O
implement	O
a	O
complete	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	B-General_Concept
)	O
,	O
the	O
core	O
mathematical	O
component	O
of	O
a	O
CPU	O
,	O
allowing	O
the	O
expansion	O
from	O
an	O
8-bit	O
design	O
to	O
16-bit	B-Device
.	O
</s>
<s>
This	O
did	O
require	O
the	O
expansion	O
of	O
the	O
CPU	O
from	O
a	O
single	O
printed	O
circuit	O
board	O
to	O
two	O
,	O
but	O
such	O
a	O
design	O
would	O
still	O
be	O
significantly	O
cheaper	O
to	O
produce	O
than	O
the	O
8/I	O
while	O
still	O
being	O
more	O
powerful	O
and	O
ASCII-based	O
.	O
</s>
<s>
A	O
third	O
board	O
held	O
the	O
input/output	B-General_Concept
circuitry	O
and	O
a	O
complete	O
system	O
typically	O
included	O
another	O
board	O
with	O
4kB	O
of	O
random-access	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
A	O
complete	O
four-card	O
system	O
fit	O
in	O
a	O
single	O
rackmount	B-Application
chassis	O
.	O
</s>
<s>
The	O
boards	O
were	O
designed	O
so	O
they	O
could	O
be	O
connected	O
together	O
using	O
a	O
printed	O
circuit	O
backplane	B-Architecture
,	O
with	O
minimal	O
manual	O
wiring	O
,	O
allowing	O
all	O
the	O
boards	O
to	O
be	O
built	O
in	O
an	O
automated	O
fashion	O
.	O
</s>
<s>
This	O
greatly	O
reduced	O
costs	O
over	O
8/I	O
,	O
which	O
consisted	O
of	O
many	O
smaller	O
boards	O
that	O
had	O
to	O
be	O
wired	O
together	O
at	O
the	O
backplane	B-Architecture
,	O
which	O
was	O
itself	O
connected	O
together	O
using	O
wire	O
wrap	O
.	O
</s>
<s>
The	O
new	O
design	O
used	O
a	O
simple	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
which	O
would	O
reemerge	O
in	O
the	O
RISC	B-Architecture
designs	O
in	O
the	O
1980s	O
.	O
</s>
<s>
Because	O
the	O
complexity	O
of	O
a	O
flip-flop	B-General_Concept
was	O
being	O
rapidly	O
reduced	O
as	O
they	O
were	O
implemented	O
in	O
chips	O
,	O
the	O
design	O
offset	O
the	O
lack	O
of	O
addressing	B-Language
modes	I-Language
of	O
the	O
load	O
–	O
store	O
design	O
by	O
adding	O
four	O
general-purpose	O
accumulators	B-General_Concept
,	O
instead	O
of	O
the	O
single	O
register	O
that	O
would	O
be	O
found	O
in	O
similar	O
low-cost	O
offerings	O
like	O
the	O
PDP	O
series	O
.	O
</s>
<s>
They	O
had	O
a	O
bit	O
of	O
luck	O
because	O
the	O
Fall	O
Joint	O
Computer	O
Conference	O
had	O
been	O
delayed	O
until	O
December	O
that	O
year	O
,	O
so	O
they	O
were	O
able	O
to	O
bring	O
a	O
working	O
unit	O
to	O
the	O
Moscone	O
Center	O
where	O
they	O
ran	O
a	O
version	O
of	O
Spacewar	B-Application
!	I-Application
.	O
</s>
<s>
The	O
basic	O
model	O
was	O
not	O
very	O
useful	O
out	O
of	O
the	O
box	O
,	O
and	O
adding	O
(	O
)	O
RAM	B-Architecture
in	O
the	O
form	O
of	O
core	B-General_Concept
memory	I-General_Concept
typically	O
brought	O
the	O
price	O
up	O
to	O
.	O
</s>
<s>
By	O
this	O
time	O
a	O
number	O
of	O
other	O
companies	O
were	O
talking	O
about	O
introducing	O
16-bit	B-Device
designs	O
as	O
well	O
.	O
</s>
<s>
Olsen	O
decided	O
these	O
presented	O
a	O
threat	O
to	O
their	O
18-bit	O
line	O
as	O
well	O
as	O
12-bit	O
,	O
and	O
began	O
a	O
new	O
16-bit	B-Device
design	O
effort	O
.	O
</s>
<s>
This	O
emerged	O
in	O
1970	O
as	O
the	O
PDP-11	B-Device
,	O
a	O
much	O
more	O
complex	O
design	O
that	O
was	O
as	O
different	O
from	O
the	O
PDP-X	O
as	O
the	O
Nova	O
was	O
.	O
</s>
<s>
Another	O
was	O
that	O
Intel	O
was	O
aggressively	O
talking	O
up	O
semiconductor-based	O
memories	O
,	O
promising	O
1024	O
bits	O
on	O
a	O
single	O
chip	O
and	O
running	O
at	O
much	O
higher	O
speeds	O
than	O
core	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
To	O
start	O
,	O
the	O
new	O
ICs	O
allowed	O
the	O
ALU	B-General_Concept
to	O
be	O
expanded	O
to	O
full	O
16-bit	B-Device
width	O
on	O
the	O
same	O
two	O
cards	O
,	O
allowing	O
it	O
to	O
carry	B-Algorithm
out	O
math	O
and	O
logic	O
operations	O
in	O
a	O
single	O
cycle	O
and	O
thereby	O
making	O
the	O
new	O
design	O
four	O
times	O
as	O
fast	O
as	O
the	O
original	O
.	O
</s>
<s>
In	O
addition	O
,	O
new	O
smaller	O
core	B-General_Concept
memory	I-General_Concept
was	O
used	O
that	O
improved	O
the	O
cycle	O
time	O
from	O
the	O
original	O
's	O
1,200	O
ns	O
to	O
800ns	O
,	O
offering	O
a	O
further	O
improvement	O
.	O
</s>
<s>
Performance	O
could	O
be	O
further	O
improved	O
by	O
replacing	O
the	O
core	O
with	O
read-only	B-Device
memory	I-Device
;	O
lacking	O
core	O
's	O
read	O
–	O
write	O
cycle	O
,	O
this	O
could	O
be	O
accessed	O
in	O
300ns	O
for	O
a	O
dramatic	O
performance	O
boost	O
.	O
</s>
<s>
This	O
made	O
it	O
the	O
fastest	O
available	O
minicomputer	B-Architecture
for	O
many	O
years	O
.	O
</s>
<s>
As	O
a	O
demonstration	O
of	O
the	O
power	O
of	O
their	O
Micromatrix	O
gate	O
array	O
technology	O
,	O
in	O
1968	O
Fairchild	O
prototyped	O
the	O
4711	O
,	O
a	O
single-chip	O
4-bit	O
ALU	B-General_Concept
.	O
</s>
<s>
The	O
introduction	O
of	O
the	O
Signetics	O
8260	O
in	O
1969	O
forced	O
their	O
hand	O
;	O
both	O
Texas	O
Instruments	O
and	O
Fairchild	O
introduced	O
4-bit	O
ALUs	B-General_Concept
of	O
their	O
own	O
in	O
1970	O
,	O
the	O
74181	O
and	O
9341	O
,	O
respectively	O
.	O
</s>
<s>
Gruner	O
's	O
low-cost	O
model	O
launched	O
in	O
1970	O
as	O
the	O
Nova	O
1200	O
,	O
the	O
1200	O
referring	O
to	O
the	O
use	O
of	O
the	O
original	O
Nova	O
's	O
1,200	O
ns	O
core	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
It	O
featured	O
a	O
4-bit	O
ALU	B-General_Concept
based	O
on	O
a	O
single	O
74181	O
chip	O
,	O
and	O
was	O
thus	O
essentially	O
a	O
repackaged	O
Nova	O
.	O
</s>
<s>
Seligman	O
's	O
repackaged	O
four-ALU	O
SuperNOVA	O
was	O
released	O
in	O
1971	O
as	O
the	O
Nova	O
800	O
,	O
resulting	O
in	O
the	O
somewhat	O
confusing	O
naming	O
where	O
the	O
lower-numbered	O
model	O
has	O
higher	O
performance	O
.	O
</s>
<s>
By	O
this	O
time	O
the	O
PDP-11	B-Device
was	O
finally	O
shipping	O
.	O
</s>
<s>
It	O
offered	O
a	O
much	O
richer	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
than	O
the	O
deliberately	O
simple	O
one	O
in	O
the	O
Nova	O
.	O
</s>
<s>
This	O
concept	O
shipped	O
as	O
the	O
Data	B-Device
General	I-Device
Eclipse	I-Device
series	O
,	O
which	O
offered	O
the	O
ability	O
to	O
add	O
additional	O
circuitry	O
to	O
tailor	O
the	O
instruction	B-General_Concept
set	I-General_Concept
for	O
scientific	O
or	O
data	O
processing	O
workloads	O
.	O
</s>
<s>
The	O
Eclipse	B-Device
was	O
successful	O
in	O
competing	O
with	O
the	O
PDP-11	B-Device
at	O
the	O
higher	O
end	O
of	O
the	O
market	O
.	O
</s>
<s>
ROM	B-Device
was	O
used	O
to	O
store	O
the	O
boot	O
code	O
,	O
which	O
was	O
then	O
copied	O
into	O
core	O
when	O
the	O
"	O
program	O
load	O
"	O
switch	O
was	O
flipped	O
.	O
</s>
<s>
The	O
processor	O
was	O
also	O
re-implemented	O
using	O
TTL	B-General_Concept
components	O
,	O
further	O
increasing	O
the	O
performance	O
of	O
the	O
system	O
.	O
</s>
<s>
It	O
appears	O
that	O
Data	O
General	O
originally	O
intended	O
the	O
Nova	O
3	O
to	O
be	O
the	O
last	O
of	O
its	O
line	O
,	O
planning	O
to	O
replace	O
the	O
Nova	O
with	O
the	O
later	O
Eclipse	B-Device
machines	O
.	O
</s>
<s>
However	O
,	O
continued	O
demand	O
led	O
to	O
a	O
Nova	O
4	O
machine	O
,	O
this	O
time	O
based	O
on	O
four	O
AMD	B-General_Concept
Am2901	I-General_Concept
bit-slice	B-General_Concept
ALUs	I-General_Concept
.	O
</s>
<s>
This	O
machine	O
was	O
designed	O
from	O
the	O
start	O
to	O
be	O
both	O
the	O
Nova	O
4	O
and	O
the	O
Eclipse	B-Device
S/140	O
,	O
with	O
different	O
microcode	B-Device
for	O
each	O
.	O
</s>
<s>
An	O
additional	O
option	O
allowed	O
for	O
memory	O
mapping	O
,	O
allowing	O
programs	O
to	O
access	O
up	O
to	O
128kwords	O
of	O
memory	O
using	O
bank	B-General_Concept
switching	I-General_Concept
.	O
</s>
<s>
Unlike	O
the	O
earlier	O
machines	O
,	O
the	O
Nova	O
4	O
did	O
not	O
include	O
a	O
front	B-Device
panel	I-Device
console	I-Device
and	O
instead	O
relied	O
on	O
the	O
terminal	B-General_Concept
to	O
emulate	O
a	O
console	O
when	O
needed	O
.	O
</s>
<s>
There	O
were	O
three	O
different	O
versions	O
of	O
the	O
Nova	O
4	O
,	O
the	O
Nova	O
4/C	O
,	O
the	O
Nova	O
4/S	O
and	O
the	O
Nova	O
4/X	O
.	O
</s>
<s>
The	O
Nova	O
4/C	O
was	O
a	O
single-board	O
implementation	O
that	O
included	O
all	O
of	O
the	O
memory	O
(	O
16	O
or	O
32kwords	O
)	O
.	O
</s>
<s>
The	O
Nova	O
4/X	O
had	O
the	O
on-board	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
enabled	O
to	O
allow	O
up	O
to	O
128kwords	O
of	O
memory	O
to	O
be	O
used	O
.	O
</s>
<s>
To	O
allow	O
it	O
to	O
fit	O
into	O
a	O
40-pin	O
dual	B-Algorithm
in-line	I-Algorithm
package	I-Algorithm
(	O
DIP	B-Algorithm
)	O
chip	O
,	O
the	O
address	B-Architecture
bus	I-Architecture
and	O
data	B-General_Concept
bus	I-General_Concept
shared	O
a	O
set	O
of	O
16	O
pins	O
.	O
</s>
<s>
This	O
was	O
sold	O
both	O
as	O
a	O
CPU	O
for	O
other	O
users	O
,	O
a	O
complete	O
chipset	O
for	O
those	O
wanting	O
to	O
implement	O
a	O
computer	O
,	O
a	O
complete	O
computer	O
on	O
a	O
single	O
board	O
with	O
4kB	O
of	O
RAM	B-Architecture
,	O
and	O
as	O
a	O
complete	O
low-end	O
model	O
of	O
the	O
Nova	O
.	O
</s>
<s>
The	O
microNOVA	O
was	O
later	O
re-packaged	O
with	O
a	O
monitor	O
in	O
a	O
PC-style	O
case	O
with	O
two	O
floppy	B-Device
disks	I-Device
as	O
the	O
Enterprise	O
.	O
</s>
<s>
Enterprise	O
shipped	O
in	O
1981	O
,	O
running	O
RDOS	B-Operating_System
,	O
but	O
the	O
introduction	O
of	O
the	O
IBM	B-Device
PC	I-Device
the	O
same	O
year	O
made	O
most	O
other	O
machines	O
disappear	O
under	O
the	O
radar	O
.	O
</s>
<s>
The	O
Nova	O
influenced	O
the	O
design	O
of	O
both	O
the	O
Xerox	B-Device
Alto	I-Device
(	O
1973	O
)	O
and	O
Apple	B-Device
I	I-Device
(	O
1976	O
)	O
computers	O
,	O
and	O
its	O
architecture	O
was	O
the	O
basis	O
for	O
the	O
Computervision	O
CGP	O
(	O
Computervision	O
Graphics	O
Processor	O
)	O
series	O
.	O
</s>
<s>
Its	O
external	O
design	O
has	O
been	O
reported	O
to	O
be	O
the	O
direct	O
inspiration	O
for	O
the	O
front	B-Device
panel	I-Device
of	O
the	O
MITS	B-Architecture
Altair	I-Architecture
(	O
1975	O
)	O
microcomputer	O
.	O
</s>
<s>
The	O
Eclipse	B-Device
family	O
of	O
systems	O
was	O
later	O
introduced	O
with	O
an	O
extended	O
upwardly	O
compatible	O
instruction	B-General_Concept
set	I-General_Concept
,	O
and	O
the	O
MV-series	O
further	O
extended	O
the	O
Eclipse	B-Device
into	O
a	O
32-bit	O
architecture	O
to	O
compete	O
with	O
the	O
DEC	B-Device
VAX	I-Device
.	O
</s>
<s>
there	O
are	O
still	O
16-bit	B-Device
Novas	O
and	O
Eclipses	O
running	O
in	O
a	O
variety	O
of	O
applications	O
worldwide	O
,	O
including	O
air	O
traffic	O
control	O
.	O
</s>
<s>
There	O
is	O
a	O
diverse	O
but	O
ardent	O
group	O
of	O
people	O
worldwide	O
who	O
restore	O
and	O
preserve	O
original	O
16-bit	B-Device
Data	O
General	O
systems	O
.	O
</s>
<s>
The	O
Nova	O
,	O
unlike	O
the	O
PDP-8	B-Device
,	O
was	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
.	O
</s>
<s>
It	O
had	O
four	O
16-bit	B-Device
accumulator	B-General_Concept
registers	O
,	O
two	O
of	O
which	O
(	O
2	O
and	O
3	O
)	O
could	O
be	O
used	O
as	O
index	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
There	O
was	O
a	O
15-bit	O
program	B-General_Concept
counter	I-General_Concept
and	O
a	O
single-bit	O
carry	B-Algorithm
register	O
.	O
</s>
<s>
As	O
with	O
the	O
PDP-8	B-Device
,	O
current	O
+	O
zero	B-General_Concept
page	I-General_Concept
addressing	O
was	O
central	O
.	O
</s>
<s>
There	O
was	O
no	O
stack	B-General_Concept
register	I-General_Concept
,	O
but	O
later	O
Eclipse	B-Device
designs	O
would	O
utilize	O
a	O
dedicated	O
hardware	O
memory	O
address	O
for	O
this	O
function	O
.	O
</s>
<s>
The	O
earliest	O
models	O
of	O
the	O
Nova	O
processed	O
math	O
serially	O
in	O
4-bit	O
packets	O
,	O
using	O
a	O
single	O
74181	O
bitslice	B-General_Concept
ALU	B-General_Concept
.	O
</s>
<s>
A	O
year	O
after	O
its	O
introduction	O
,	O
this	O
design	O
was	O
improved	O
to	O
include	O
a	O
full	O
16-bit	B-Device
parallel	O
math	O
unit	O
using	O
four	O
74181s	O
,	O
this	O
design	O
being	O
referred	O
to	O
as	O
the	O
SuperNova	O
.	O
</s>
<s>
The	O
Nova	O
4	O
/	O
Eclipse	B-Device
S/140	O
was	O
based	O
on	O
four	O
AMD	B-General_Concept
2901	I-General_Concept
bit-slice	B-General_Concept
ALUs	I-General_Concept
,	O
with	O
microcode	B-Device
in	O
read-only	B-Device
memory	I-Device
,	O
and	O
was	O
the	O
first	O
Nova	O
designed	O
for	O
DRAM	O
main	O
memory	O
only	O
,	O
without	O
provision	O
for	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
first	O
models	O
were	O
available	O
with	O
8	O
K	O
words	O
of	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
as	O
an	O
option	O
,	O
one	O
that	O
practically	O
everyone	O
had	O
to	O
buy	O
,	O
bringing	O
the	O
system	O
cost	O
up	O
to	O
$	O
7,995	O
.	O
</s>
<s>
This	O
core	B-General_Concept
memory	I-General_Concept
board	O
was	O
organized	O
in	O
planar	O
fashion	O
as	O
four	O
groups	O
of	O
four	O
banks	O
,	O
each	O
bank	O
carrying	O
two	O
sets	O
of	O
core	O
in	O
a	O
64	O
by	O
64	O
matrix	O
;	O
thus	O
there	O
were	O
64	O
x	O
64	O
=	O
4096	O
bits	O
per	O
set	O
,	O
x	O
2	O
sets	O
giving	O
8,192	O
bits	O
,	O
x	O
4	O
banks	O
giving	O
32,768	O
bits	O
,	O
x	O
4	O
groups	O
giving	O
a	O
total	O
of	O
131,072	O
bits	O
,	O
and	O
this	O
divided	O
by	O
the	O
machine	O
word	O
size	O
of	O
16	B-Device
bits	I-Device
gave	O
8,192	O
words	O
of	O
memory	O
.	O
</s>
<s>
The	O
core	O
on	O
this	O
8K	O
word	O
memory	O
board	O
occupied	O
a	O
centrally	O
located	O
"	O
board-on-a-board	O
"	O
,	O
5.25	B-Device
"	I-Device
wide	O
by	O
6.125	O
"	O
high	O
,	O
and	O
was	O
covered	O
by	O
a	O
protective	O
plate	O
.	O
</s>
<s>
Up	O
to	O
32K	O
of	O
such	O
core	O
RAM	B-Architecture
could	O
be	O
supported	O
in	O
one	O
external	O
expansion	O
box	O
.	O
</s>
<s>
Semiconductor	O
ROM	B-Device
was	O
already	O
available	O
at	O
the	O
time	O
,	O
and	O
RAM-less	O
systems	O
(	O
i.e.	O
</s>
<s>
with	O
ROM	B-Device
only	O
)	O
became	O
popular	O
in	O
many	O
industrial	O
settings	O
.	O
</s>
<s>
The	O
standardized	O
backplane	B-Architecture
and	O
I/O	B-General_Concept
signals	O
created	O
a	O
simple	O
,	O
efficient	O
I/O	B-General_Concept
design	O
that	O
made	O
interfacing	O
programmed	O
I/O	B-General_Concept
and	O
Data	O
Channel	O
devices	O
to	O
the	O
Nova	O
simple	O
compared	O
to	O
competing	O
machines	O
.	O
</s>
<s>
In	O
addition	O
to	O
its	O
dedicated	O
I/O	B-General_Concept
bus	I-General_Concept
structure	O
,	O
the	O
Nova	O
backplane	B-Architecture
had	O
wire	O
wrap	O
pins	O
that	O
could	O
be	O
used	O
for	O
non-standard	O
connectors	O
or	O
other	O
special	O
purposes	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
format	I-General_Concept
could	O
be	O
broadly	O
categorized	O
into	O
one	O
of	O
three	O
functions	O
:	O
1	O
)	O
register-to-register	O
manipulation	O
,	O
2	O
)	O
memory	O
reference	O
,	O
and	O
3	O
)	O
input/output	B-General_Concept
.	O
</s>
<s>
The	O
register-to-register	O
manipulation	O
was	O
almost	O
RISC-like	O
in	O
its	O
bit-efficiency	O
;	O
and	O
an	O
instruction	O
that	O
manipulated	O
register	O
data	O
could	O
also	O
perform	O
tests	O
,	O
shifts	O
and	O
even	O
elect	O
to	O
discard	O
the	O
result	O
.	O
</s>
<s>
Hardware	O
options	O
included	O
an	O
integer	O
multiply	O
and	O
divide	O
unit	O
,	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
single	O
and	O
double	O
precision	O
)	O
,	O
and	O
memory	B-General_Concept
management	I-General_Concept
.	O
</s>
<s>
As	O
the	O
product	O
grew	O
,	O
Data	O
General	O
developed	O
many	O
languages	O
for	O
the	O
Nova	O
computers	O
,	O
running	O
under	O
a	O
range	O
of	O
consistent	O
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
FORTRAN	O
IV	O
,	O
ALGOL	B-Language
,	O
Extended	O
BASIC	O
,	O
Data	B-Language
General	I-Language
Business	I-Language
Basic	I-Language
,	O
Interactive	O
COBOL	B-Application
,	O
and	O
several	O
assemblers	O
were	O
available	O
from	O
Data	O
General	O
.	O
</s>
<s>
Third	O
party	O
vendors	O
and	O
the	O
user	O
community	O
expanded	O
the	O
offerings	O
with	O
Forth	B-Application
,	O
Lisp	B-Language
,	O
BCPL	B-Language
,	O
C	B-Language
,	O
ALGOL	B-Language
,	O
and	O
other	O
proprietary	O
versions	O
of	O
COBOL	B-Application
and	O
BASIC	O
.	O
</s>
<s>
All	O
arithmetic	O
instructions	O
operated	O
between	O
accumulators	B-General_Concept
.	O
</s>
<s>
For	O
operations	O
requiring	O
two	O
operands	O
,	O
one	O
was	O
taken	O
from	O
the	O
source	O
accumulator	B-General_Concept
,	O
and	O
one	O
from	O
the	O
destination	O
accumulator	B-General_Concept
,	O
and	O
the	O
result	O
was	O
deposited	O
in	O
the	O
destination	O
accumulator	B-General_Concept
.	O
</s>
<s>
For	O
all	O
single-operand	O
opcodes	O
,	O
it	O
was	O
permissible	O
for	O
the	O
source	O
and	O
destination	O
accumulators	B-General_Concept
to	O
be	O
the	O
same	O
,	O
and	O
the	O
operation	O
functioned	O
as	O
expected	O
.	O
</s>
<s>
The	O
CPU	O
contained	O
a	O
single-bit	O
register	O
called	O
the	O
carry	B-Algorithm
bit	I-Algorithm
,	O
which	O
after	O
an	O
arithmetic	O
operation	O
would	O
contain	O
the	O
carry	B-Algorithm
out	O
of	O
the	O
most	O
significant	O
bit	O
.	O
</s>
<s>
The	O
carry	B-Algorithm
bit	I-Algorithm
could	O
be	O
set	O
to	O
a	O
desired	O
value	O
prior	O
to	O
performing	O
the	O
operation	O
using	O
a	O
two-bit	O
field	O
in	O
the	O
instruction	O
.	O
</s>
<s>
In	O
assembly	O
language	O
,	O
these	O
options	O
were	O
specified	O
by	O
adding	O
a	O
letter	O
to	O
the	O
opcode	O
:	O
'	O
O	O
 '	O
—	O
set	O
the	O
carry	B-Algorithm
bit	I-Algorithm
;	O
'	O
Z	O
 '	O
—	O
clear	O
the	O
carry	B-Algorithm
bit	I-Algorithm
,	O
'	O
C	B-Language
 '	O
—	O
complement	O
the	O
carry	B-Algorithm
bit	I-Algorithm
,	O
nothing	O
—	O
leave	O
the	O
carry	B-Algorithm
bit	I-Algorithm
alone	O
.	O
</s>
<s>
If	O
the	O
no-load	O
bit	O
was	O
also	O
specified	O
,	O
the	O
specified	O
carry	B-Algorithm
value	O
would	O
be	O
used	O
for	O
the	O
computation	O
,	O
but	O
the	O
actual	O
carry	B-Algorithm
register	O
would	O
remain	O
unaltered	O
.	O
</s>
<s>
Shifts	O
were	O
17-bit	O
circular	O
,	O
with	O
the	O
carry	B-Algorithm
bit	I-Algorithm
"	O
to	O
the	O
left	O
"	O
of	O
the	O
most	O
significant	O
bit	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
when	O
a	O
left	O
shift	O
was	O
performed	O
,	O
the	O
most	O
significant	O
bit	O
of	O
the	O
result	O
was	O
shifted	O
into	O
the	O
carry	B-Algorithm
bit	I-Algorithm
,	O
and	O
the	O
previous	O
contents	O
of	O
the	O
carry	B-Algorithm
bit	I-Algorithm
were	O
shifted	O
into	O
the	O
least	O
significant	O
bit	O
of	O
the	O
result	O
.	O
</s>
<s>
Byte	O
swaps	O
did	O
not	O
affect	O
the	O
carry	B-Algorithm
bit	I-Algorithm
.	O
</s>
<s>
If	O
the	O
test	O
evaluated	O
to	O
true	O
,	O
the	O
next	B-General_Concept
instruction	I-General_Concept
in	O
line	O
was	O
skipped	O
.	O
</s>
<s>
This	O
decoded	O
as	O
:	O
clear	O
the	O
carry	B-Algorithm
bit	I-Algorithm
;	O
add	O
the	O
contents	O
of	O
AC2	O
(	O
accumulator	B-General_Concept
2	O
)	O
to	O
AC0	O
;	O
circularly	O
shift	O
the	O
result	O
one	O
bit	O
to	O
the	O
right	O
;	O
test	O
the	O
result	O
to	O
see	O
if	O
the	O
carry	B-Algorithm
bit	I-Algorithm
is	O
set	O
and	O
skip	O
the	O
next	B-General_Concept
instruction	I-General_Concept
if	O
so	O
.	O
</s>
<s>
The	O
Nova	O
instruction	B-General_Concept
set	I-General_Concept
contained	O
a	O
pair	O
of	O
instructions	O
that	O
transferred	O
memory	O
contents	O
to	O
accumulators	B-General_Concept
and	O
vice	O
versa	O
,	O
two	O
transfer-of-control	O
instructions	O
,	O
and	O
two	O
instructions	O
that	O
tested	O
the	O
contents	O
of	O
a	O
memory	O
location	O
.	O
</s>
<s>
The	O
contents	O
of	O
the	O
address	O
field	O
of	O
the	O
instruction	O
is	O
sign	O
extended	O
to	O
the	O
left	O
and	O
added	O
to	O
the	O
current	O
value	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
(	O
which	O
,	O
by	O
the	O
time	O
the	O
instruction	O
executes	O
,	O
points	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
)	O
.	O
</s>
<s>
Mode	O
2	O
—	O
indexed	B-Language
addressing	I-Language
.	O
</s>
<s>
The	O
contents	O
of	O
the	O
address	O
field	O
of	O
the	O
instruction	O
is	O
sign	O
extended	O
to	O
the	O
left	O
and	O
added	O
to	O
the	O
current	O
value	O
of	O
accumulator	B-General_Concept
2	O
.	O
</s>
<s>
Mode	O
3	O
—	O
indexed	B-Language
addressing	I-Language
.	O
</s>
<s>
The	O
contents	O
of	O
the	O
address	O
field	O
of	O
the	O
instruction	O
is	O
sign	O
extended	O
to	O
the	O
left	O
and	O
added	O
to	O
the	O
current	O
value	O
of	O
accumulator	B-General_Concept
3	O
.	O
</s>
<s>
This	O
portion	O
of	O
memory	O
was	O
referred	O
to	O
as	O
"	O
page	B-General_Concept
zero	I-General_Concept
"	O
.	O
</s>
<s>
Page	B-General_Concept
zero	I-General_Concept
memory	O
words	O
were	O
considered	O
precious	O
to	O
Nova	O
assembly	O
language	O
programmers	O
because	O
of	O
the	O
small	O
number	O
available	O
;	O
only	O
page	B-General_Concept
zero	I-General_Concept
locations	O
could	O
be	O
addressed	O
from	O
anywhere	O
in	O
the	O
program	O
without	O
resorting	O
to	O
indexed	B-Language
addressing	I-Language
,	O
which	O
required	O
tying	O
up	O
accumulator	B-General_Concept
2	O
or	O
3	O
to	O
use	O
as	O
an	O
index	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
In	O
assembly	O
language	O
,	O
a	O
"	O
.ZREL	O
"	O
directive	O
caused	O
the	O
assembler	O
to	O
place	O
the	O
instructions	O
and	O
data	O
words	O
that	O
followed	O
it	O
in	O
page	B-General_Concept
zero	I-General_Concept
;	O
an	O
"	O
.NREL	O
"	O
directive	O
placed	O
the	O
following	O
instructions	O
and	O
data	O
words	O
in	O
"	O
normal	O
"	O
memory	O
.	O
</s>
<s>
If	O
a	O
memory	O
reference	O
instruction	O
referenced	O
a	O
memory	O
address	O
in	O
.NREL	O
space	O
but	O
no	O
mode	O
specifier	O
,	O
mode	O
1	O
was	O
assumed	O
and	O
the	O
assembler	O
calculated	O
the	O
offset	O
between	O
the	O
current	B-General_Concept
instruction	I-General_Concept
and	O
the	O
referenced	O
location	O
,	O
and	O
placed	O
this	O
in	O
the	O
instruction	O
's	O
address	O
field	O
(	O
provided	O
that	O
the	O
resulting	O
value	O
fit	O
into	O
the	O
8-bit	O
field	O
)	O
.	O
</s>
<s>
The	O
two	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
were	O
:	O
</s>
<s>
—	O
load	O
the	O
contents	O
of	O
a	O
memory	O
location	O
into	O
the	O
specified	O
accumulator	B-General_Concept
.	O
</s>
<s>
—	O
store	O
the	O
contents	O
of	O
the	O
specified	O
accumulator	B-General_Concept
into	O
a	O
memory	O
location	O
.	O
</s>
<s>
(	O
"	O
jump	O
subroutine	O
"	O
)	O
—	O
Does	O
the	O
same	O
as	O
the	O
JMP	O
instruction	O
,	O
but	O
additionally	O
loads	O
the	O
return	B-Language
address	I-Language
(	O
the	O
instruction	O
following	O
the	O
JSR	O
instruction	O
in	O
line	O
)	O
into	O
accumulator	B-General_Concept
3	O
before	O
jumping	O
.	O
</s>
<s>
As	O
in	O
the	O
case	O
of	O
the	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
,	O
the	O
jump	O
instructions	O
contained	O
an	O
indirect	O
bit	O
,	O
which	O
likewise	O
was	O
specified	O
in	O
assembly	O
using	O
the	O
'	O
@	O
 '	O
character	O
.	O
</s>
<s>
However	O
,	O
unlike	O
the	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
,	O
if	O
the	O
indirect	B-Language
address	I-Language
had	O
the	O
most	O
significant	O
bit	O
set	O
,	O
it	O
would	O
perform	O
a	O
further	O
cycle	O
of	O
indirection	O
.	O
</s>
<s>
On	O
the	O
Nova	O
series	O
processors	O
prior	O
to	O
the	O
Nova	O
3	O
,	O
there	O
was	O
no	O
limit	O
on	O
the	O
number	O
of	O
indirection	O
cycles	O
;	O
an	O
indirect	B-Language
address	I-Language
that	O
referenced	O
itself	O
would	O
result	O
in	O
an	O
infinite	O
indirect	B-Language
addressing	I-Language
loop	O
,	O
with	O
the	O
instruction	O
never	O
completing	O
.	O
</s>
<s>
(	O
This	O
could	O
be	O
alarming	O
to	O
users	O
,	O
since	O
when	O
in	O
this	O
condition	O
,	O
pressing	O
the	O
STOP	O
switch	O
on	O
the	O
front	B-Device
panel	I-Device
did	O
nothing	O
.	O
</s>
<s>
—	O
increment	O
the	O
memory	O
location	O
,	O
and	O
skip	O
the	O
next	B-General_Concept
instruction	I-General_Concept
if	O
the	O
result	O
is	O
zero	O
.	O
</s>
<s>
—	O
decrement	O
the	O
memory	O
location	O
,	O
and	O
skip	O
the	O
next	B-General_Concept
instruction	I-General_Concept
if	O
the	O
result	O
is	O
zero	O
.	O
</s>
<s>
As	O
in	O
the	O
case	O
of	O
the	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
,	O
there	O
was	O
an	O
indirect	O
bit	O
that	O
would	O
perform	O
a	O
single	O
level	O
of	O
indirect	B-Language
addressing	I-Language
.	O
</s>
<s>
These	O
instructions	O
were	O
odd	O
in	O
that	O
,	O
on	O
the	O
Novas	O
with	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
,	O
the	O
instruction	O
was	O
executed	O
within	O
the	O
memory	O
board	O
itself	O
.	O
</s>
<s>
As	O
was	O
common	O
at	O
the	O
time	O
,	O
the	O
memory	O
boards	O
contained	O
a	O
"	O
write-back	O
"	O
circuit	O
to	O
solve	O
the	O
destructive-read	O
problem	O
inherent	O
to	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
These	O
instructions	O
were	O
useful	O
because	O
they	O
allowed	O
a	O
memory	O
location	O
to	O
be	O
used	O
as	O
a	O
loop	O
counter	O
without	O
tying	O
up	O
an	O
accumulator	B-General_Concept
,	O
but	O
they	O
were	O
slower	O
than	O
performing	O
the	O
equivalent	O
arithmetic	O
instructions	O
.	O
</s>
<s>
Transfers	O
the	O
contents	O
of	O
the	O
memory	O
location	O
labeled	O
COUNT	O
into	O
accumulator	B-General_Concept
1	O
.	O
</s>
<s>
Jump	O
indirect	O
to	O
the	O
memory	O
address	O
specified	O
by	O
the	O
contents	O
of	O
location	O
17	O
,	O
in	O
page	B-General_Concept
zero	I-General_Concept
space	O
,	O
and	O
deposit	O
the	O
return	B-Language
address	I-Language
in	O
accumulator	B-General_Concept
3	O
.	O
</s>
<s>
This	O
was	O
the	O
standard	O
method	O
for	O
making	O
an	O
RDOS	B-Operating_System
system	O
call	O
on	O
early	O
Nova	O
models	O
;	O
the	O
assembly	O
language	O
mnemonic	O
"	O
.SYSTM	O
"	O
translated	O
to	O
this	O
.	O
</s>
<s>
Jump	O
to	O
the	O
memory	O
location	O
whose	O
address	O
is	O
contained	O
in	O
accumulator	B-General_Concept
3	O
.	O
</s>
<s>
This	O
was	O
a	O
common	O
means	O
of	O
returning	O
from	O
a	O
function	O
or	O
subroutine	O
call	O
,	O
since	O
the	O
JSR	O
instruction	O
left	O
the	O
return	B-Language
address	I-Language
in	O
accumulator	B-General_Concept
3	O
.	O
</s>
<s>
Store	O
the	O
contents	O
of	O
accumulator	B-General_Concept
0	O
in	O
the	O
location	O
that	O
is	O
one	O
less	O
than	O
the	O
address	O
contained	O
in	O
accumulator	B-General_Concept
3	O
.	O
</s>
<s>
Decrement	O
the	O
value	O
in	O
the	O
location	O
labeled	O
COUNT	O
,	O
and	O
skip	O
the	O
next	B-General_Concept
instruction	I-General_Concept
if	O
the	O
result	O
is	O
zero	O
.	O
</s>
<s>
The	O
Novas	O
implemented	O
a	O
channelized	O
model	O
for	O
interfacing	O
to	O
I/O	B-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
In	O
the	O
model	O
,	O
each	O
I/O	B-General_Concept
device	I-General_Concept
was	O
expected	O
to	O
implement	O
two	O
flags	O
,	O
referred	O
to	O
as	O
"	O
Busy	O
"	O
and	O
"	O
Done	O
"	O
,	O
and	O
three	O
data	O
and	O
control	O
registers	O
,	O
referred	O
to	O
as	O
A	O
,	O
B	O
,	O
and	O
C	B-Language
.	O
I/O	B-General_Concept
instructions	O
were	O
available	O
to	O
read	O
and	O
write	O
the	O
registers	O
,	O
and	O
to	O
send	O
one	O
of	O
three	O
signals	O
to	O
the	O
device	O
,	O
referred	O
to	O
as	O
"	O
start	O
"	O
,	O
"	O
clear	O
"	O
,	O
and	O
"	O
pulse	O
"	O
.	O
</s>
<s>
In	O
general	O
,	O
sending	O
a	O
start	O
signal	O
initiated	O
an	O
I/O	B-General_Concept
operation	I-General_Concept
that	O
had	O
been	O
set	O
up	O
by	O
loading	O
values	O
into	O
the	O
A/B/C	O
registers	O
.	O
</s>
<s>
The	O
clear	O
signal	O
halted	O
an	O
I/O	B-General_Concept
operation	I-General_Concept
and	O
cleared	O
any	O
resulting	O
interrupt	O
.	O
</s>
<s>
DMA	O
devices	O
generally	O
used	O
the	O
A	O
register	O
to	O
specify	O
the	O
memory	O
address	O
,	O
the	O
B	O
register	O
to	O
specify	O
the	O
number	O
of	O
words	O
to	O
be	O
transferred	O
,	O
and	O
the	O
C	B-Language
register	O
for	O
control	O
flags	O
.	O
</s>
<s>
Each	O
I/O	B-General_Concept
instruction	O
contained	O
a	O
six-bit	O
channel	O
number	O
field	O
,	O
a	O
four-bit	O
to	O
specify	O
which	O
register	O
to	O
read	O
or	O
write	O
,	O
and	O
a	O
two-bit	O
field	O
to	O
specify	O
which	O
signal	O
was	O
to	O
be	O
sent	O
.	O
</s>
<s>
In	O
assembly	O
language	O
,	O
the	O
signal	O
was	O
specified	O
by	O
adding	O
a	O
letter	O
to	O
the	O
opcode	O
:	O
'	O
S	O
 '	O
for	O
start	O
,	O
'	O
C	B-Language
 '	O
for	O
clear	O
,	O
'	O
P	O
 '	O
for	O
pulse	O
,	O
and	O
nothing	O
for	O
no	O
signal	O
.	O
</s>
<s>
—	O
"	O
no	O
I/O	B-General_Concept
"	O
,	O
a	O
misnomer	O
.	O
</s>
<s>
All	O
of	O
them	O
were	O
actually	O
shorthand	O
mnemonics	O
for	O
I/O	B-General_Concept
instructions	O
on	O
channel	O
63	O
,	O
the	O
CPU	O
's	O
self-referential	O
I/O	B-General_Concept
channel	O
.	O
</s>
<s>
Transferred	O
the	O
channel	O
number	O
of	O
the	O
interrupting	O
device	O
to	O
the	O
specified	O
accumulator	B-General_Concept
.	O
</s>
<s>
—	O
I/O	B-General_Concept
reset	O
.	O
</s>
<s>
Sent	O
a	O
reset	O
signal	O
on	O
the	O
I/O	B-General_Concept
bus	I-General_Concept
,	O
which	O
stopped	O
all	O
I/O	B-General_Concept
,	O
disabled	O
interrupts	O
and	O
cleared	O
all	O
pending	O
interrupts	O
.	O
</s>
<s>
Used	O
the	O
contents	O
of	O
the	O
specified	O
accumulator	B-General_Concept
to	O
set	O
up	O
the	O
interrupt	O
mask	O
.	O
</s>
<s>
How	O
the	O
mask	O
was	O
interpreted	O
was	O
up	O
to	O
the	O
implementation	O
of	O
each	O
I/O	B-General_Concept
device	I-General_Concept
.	O
</s>
<s>
—	O
transferred	O
the	O
contents	O
of	O
the	O
16	O
front	B-Device
panel	I-Device
data	O
switches	O
to	O
the	O
specified	O
accumulator	B-General_Concept
.	O
</s>
<s>
Once	O
halted	O
,	O
the	O
CPU	O
could	O
be	O
made	O
to	O
start	O
again	O
only	O
by	O
manual	O
intervention	O
at	O
the	O
front	B-Device
panel	I-Device
.	O
</s>
<s>
The	O
backplane	B-Architecture
supported	O
a	O
single	O
interrupt	O
request	O
line	O
,	O
which	O
all	O
devices	O
capable	O
of	O
interrupting	O
connected	O
to	O
.	O
</s>
<s>
The	O
CPU	O
took	O
the	O
interrupt	O
as	O
soon	O
as	O
it	O
completed	O
the	O
current	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
As	O
stated	O
above	O
,	O
a	O
device	O
was	O
expected	O
to	O
raise	O
its	O
"	O
done	O
"	O
I/O	B-General_Concept
flag	O
when	O
it	O
requested	O
an	O
interrupt	O
,	O
and	O
the	O
convention	O
was	O
that	O
the	O
device	O
would	O
clear	O
its	O
interrupt	O
request	O
when	O
the	O
CPU	O
executed	O
a	O
I/O	B-General_Concept
clear	O
instruction	O
on	O
the	O
device	O
's	O
channel	O
number	O
.	O
</s>
<s>
The	O
CPU	O
expected	O
the	O
operating	B-General_Concept
system	I-General_Concept
to	O
place	O
the	O
address	O
of	O
its	O
interrupt	O
service	O
routine	O
into	O
memory	O
address	O
1	O
.	O
</s>
<s>
When	O
a	O
device	O
interrupted	O
,	O
the	O
CPU	O
did	O
an	O
indirect	O
jump	O
through	O
address	O
1	O
,	O
placing	O
the	O
return	B-Language
address	I-Language
into	O
memory	O
address	O
0	O
,	O
and	O
disabling	O
further	O
interrupts	O
.	O
</s>
<s>
This	O
worked	O
by	O
raising	O
an	O
"	O
acknowledge	O
"	O
signal	O
on	O
the	O
backplane	B-Architecture
.	O
</s>
<s>
The	O
acknowledge	O
signal	O
was	O
wired	O
in	O
a	O
daisy-chain	O
format	O
across	O
the	O
backplane	B-Architecture
,	O
such	O
that	O
it	O
looped	O
through	O
each	O
board	O
on	O
the	O
bus	O
.	O
</s>
<s>
After	O
the	O
interrupt	O
had	O
been	O
processed	O
and	O
the	O
service	O
routine	O
had	O
sent	O
the	O
device	O
an	O
I/O	B-General_Concept
clear	O
,	O
it	O
resumed	O
normal	O
processing	O
by	O
enabling	O
interrupts	O
and	O
then	O
returning	O
via	O
an	O
indirect	O
jump	O
through	O
memory	O
address	O
0	O
.	O
</s>
<s>
In	O
order	O
to	O
prevent	O
a	O
pending	O
interrupt	O
from	O
interrupting	O
immediately	O
before	O
the	O
return	O
jump	O
(	O
which	O
would	O
cause	O
the	O
return	B-Language
address	I-Language
to	O
be	O
overwritten	O
)	O
,	O
the	O
INTEN	O
instruction	O
had	O
a	O
one-instruction-cycle	O
delay	O
.	O
</s>
<s>
The	O
operating	B-General_Concept
system	I-General_Concept
's	O
interrupt	O
service	O
routine	O
then	O
typically	O
performed	O
an	O
indexed	O
jump	O
using	O
the	O
received	O
channel	O
number	O
,	O
to	O
jump	O
to	O
the	O
specific	O
interrupt	O
handling	O
routine	O
for	O
the	O
device	O
.	O
</s>
<s>
The	O
operating	B-General_Concept
system	I-General_Concept
could	O
somewhat	O
manage	O
the	O
ordering	O
of	O
interrupts	O
by	O
setting	O
an	O
interrupt	O
mask	O
using	O
the	O
MSKO	O
instruction	O
.	O
</s>
<s>
This	O
was	O
intended	O
to	O
allow	O
the	O
operating	B-General_Concept
system	I-General_Concept
to	O
determine	O
which	O
devices	O
were	O
permitted	O
to	O
interrupt	O
at	O
a	O
given	O
time	O
.	O
</s>
<s>
When	O
this	O
instruction	O
was	O
issued	O
,	O
a	O
16-bit	B-Device
interrupt	O
mask	O
was	O
transmitted	O
to	O
all	O
devices	O
on	O
the	O
backplane	B-Architecture
.	O
</s>
<s>
On	O
the	O
systems	O
having	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
(	O
which	O
retained	O
its	O
contents	O
without	O
power	O
)	O
,	O
recovery	O
from	O
a	O
power	O
failure	O
was	O
possible	O
.	O
</s>
<s>
This	O
was	O
enough	O
time	O
to	O
stop	O
I/O	B-General_Concept
in	O
progress	O
,	O
by	O
issuing	O
an	O
IORST	O
instruction	O
,	O
and	O
then	O
save	O
the	O
contents	O
of	O
the	O
four	O
accumulators	B-General_Concept
and	O
the	O
carry	B-Algorithm
bit	I-Algorithm
to	O
memory	O
.	O
</s>
<s>
When	O
the	O
power	O
returned	O
,	O
if	O
the	O
CPU	O
's	O
front	B-Device
panel	I-Device
key	O
switch	O
was	O
in	O
the	O
LOCK	O
position	O
,	O
the	O
CPU	O
would	O
start	O
and	O
perform	O
an	O
indirect	O
jump	O
through	O
memory	O
address	O
2	O
.	O
</s>
<s>
This	O
was	O
expected	O
to	O
be	O
the	O
address	O
of	O
an	O
operating	B-General_Concept
system	I-General_Concept
service	O
routine	O
that	O
would	O
reload	O
the	O
accumulators	B-General_Concept
and	O
carry	B-Algorithm
bit	I-Algorithm
,	O
and	O
then	O
resume	O
normal	O
processing	O
.	O
</s>
<s>
It	O
was	O
up	O
to	O
the	O
service	O
routine	O
to	O
figure	O
out	O
how	O
to	O
restart	O
I/O	B-General_Concept
operations	I-General_Concept
that	O
were	O
aborted	O
by	O
the	O
power	O
failure	O
.	O
</s>
<s>
As	O
was	O
the	O
convention	O
of	O
the	O
day	O
,	O
most	O
Nova	O
models	O
provided	O
a	O
front	B-Device
panel	I-Device
console	I-Device
to	O
control	O
and	O
monitor	O
CPU	O
functions	O
.	O
</s>
<s>
Models	O
prior	O
to	O
the	O
Nova	O
3	O
all	O
relied	O
on	O
a	O
canonical	O
front	B-Device
panel	I-Device
layout	O
,	O
as	O
shown	O
in	O
the	O
Nova	O
840	O
panel	O
photo	O
above	O
.	O
</s>
<s>
The	O
address	O
lamps	O
always	O
displayed	O
the	O
current	O
value	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
in	O
binary	O
.	O
</s>
<s>
To	O
the	O
left	O
of	O
the	O
leftmost	O
data	O
lamp	O
,	O
an	O
additional	O
lamp	O
displayed	O
the	O
current	O
value	O
of	O
the	O
carry	B-Algorithm
bit	I-Algorithm
.	O
</s>
<s>
Each	O
of	O
the	O
data	O
switches	O
controlled	O
the	O
value	O
of	O
one	O
bit	O
in	O
a	O
16-bit	B-Device
value	O
,	O
and	O
per	O
Data	O
General	O
convention	O
,	O
they	O
were	O
numbered	O
0-15	O
from	O
left	O
to	O
right	O
.	O
</s>
<s>
Referencing	O
the	O
Nova	O
840	O
photo	O
,	O
the	O
first	O
four	O
switches	O
from	O
the	O
left	O
performed	O
the	O
EXAMINE	O
and	O
DEPOSIT	O
functions	O
for	O
the	O
four	O
accumulators	B-General_Concept
.	O
</s>
<s>
Pressing	O
EXAMINE	O
on	O
one	O
of	O
these	O
caused	O
the	O
current	O
value	O
of	O
the	O
accumulator	B-General_Concept
to	O
be	O
displayed	O
in	O
binary	O
by	O
the	O
data	O
lamps	O
.	O
</s>
<s>
Pressing	O
DEPOSIT	O
transferred	O
the	O
binary	O
value	O
represented	O
by	O
the	O
current	O
settings	O
of	O
the	O
data	O
switches	O
to	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
Pressing	O
STOP	O
caused	O
the	O
CPU	O
to	O
halt	O
after	O
completing	O
the	O
current	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
Pressing	O
RESET	O
caused	O
the	O
CPU	O
to	O
halt	O
immediately	O
,	O
cleared	O
a	O
number	O
of	O
CPU	O
internal	O
registers	O
,	O
and	O
sent	O
an	O
I/O	B-General_Concept
reset	O
signal	O
to	O
all	O
connected	O
devices	O
.	O
</s>
<s>
Pressing	O
CONTINUE	O
caused	O
the	O
CPU	O
to	O
resume	O
executing	O
at	O
the	O
instruction	O
currently	O
pointed	O
at	O
by	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Pressing	O
START	O
transferred	O
the	O
value	O
currently	O
set	O
in	O
data	O
switches	O
1-15	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
and	O
then	O
began	O
executing	O
from	O
there	O
.	O
</s>
<s>
The	O
next	O
two	O
switches	O
provided	O
read	O
and	O
write	O
access	O
to	O
memory	O
from	O
the	O
front	B-Device
panel	I-Device
.	O
</s>
<s>
Pressing	O
EXAMINE	O
transferred	O
the	O
value	O
set	O
in	O
data	O
switches	O
1-15	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
fetched	O
the	O
value	O
in	O
the	O
corresponding	O
memory	O
location	O
,	O
and	O
displayed	O
its	O
value	O
in	O
the	O
data	O
lamps	O
.	O
</s>
<s>
Pressing	O
EXAMINE	O
NEXT	O
incremented	O
the	O
program	B-General_Concept
counter	I-General_Concept
and	O
then	O
performed	O
an	O
examine	O
operation	O
on	O
that	O
memory	O
location	O
,	O
allowing	O
the	O
user	O
to	O
step	O
through	O
a	O
series	O
of	O
memory	O
locations	O
.	O
</s>
<s>
Pressing	O
DEPOSIT	O
wrote	O
the	O
value	O
contained	O
in	O
the	O
data	O
switches	O
to	O
the	O
memory	O
location	O
pointed	O
at	O
by	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Pressing	O
DEPOSIT	O
NEXT	O
first	O
incremented	O
the	O
program	B-General_Concept
counter	I-General_Concept
and	O
then	O
deposited	O
to	O
the	O
pointed-to	O
memory	O
location	O
.	O
</s>
<s>
The	O
INST	O
STEP	O
function	O
caused	O
the	O
CPU	O
to	O
execute	O
one	O
instruction	O
,	O
at	O
the	O
current	O
program	B-General_Concept
counter	I-General_Concept
location	O
,	O
and	O
then	O
halt	O
.	O
</s>
<s>
Since	O
the	O
program	B-General_Concept
counter	I-General_Concept
would	O
be	O
incremented	O
as	O
part	O
of	O
the	O
instruction	O
execution	O
,	O
this	O
allowed	O
the	O
user	O
to	O
single-step	O
through	O
a	O
program	O
.	O
</s>
<s>
When	O
this	O
switch	O
was	O
triggered	O
,	O
it	O
caused	O
the	O
32-word	O
boot	O
ROM	B-Device
to	O
be	O
mapped	O
over	O
the	O
first	O
32	O
words	O
of	O
memory	O
,	O
set	O
the	O
program	B-General_Concept
counter	I-General_Concept
to	O
0	O
,	O
and	O
started	O
the	O
CPU	O
.	O
</s>
<s>
The	O
boot	O
ROM	B-Device
contained	O
code	O
that	O
would	O
read	O
256	O
words	O
(	O
512	O
bytes	O
)	O
of	O
code	O
from	O
a	O
selected	O
I/O	B-General_Concept
device	I-General_Concept
into	O
memory	O
and	O
then	O
transfer	O
control	O
to	O
the	O
read-in	O
code	O
.	O
</s>
<s>
The	O
data	O
switches	O
8-15	O
were	O
used	O
to	O
tell	O
the	O
boot	O
ROM	B-Device
which	O
I/O	B-General_Concept
channel	O
to	O
boot	O
from	O
.	O
</s>
<s>
If	O
switch	O
0	O
was	O
off	O
,	O
the	O
boot	O
ROM	B-Device
would	O
assume	O
the	O
device	O
was	O
a	O
polled	O
device	O
(	O
e.g.	O
,	O
the	O
paper	O
tape	O
reader	O
)	O
and	O
run	O
a	O
polled	O
input	O
loop	O
until	O
512	O
bytes	O
had	O
been	O
read	O
.	O
</s>
<s>
If	O
switch	O
0	O
was	O
on	O
,	O
the	O
boot	O
ROM	B-Device
assumed	O
the	O
device	O
was	O
a	O
DMA-capable	O
device	O
and	O
it	O
initiated	O
a	O
DMA	O
data	O
transfer	O
.	O
</s>
<s>
The	O
boot	O
ROM	B-Device
was	O
not	O
smart	O
enough	O
to	O
position	O
the	O
device	O
prior	O
to	O
initiating	O
the	O
transfer	O
.	O
</s>
<s>
They	O
had	O
to	O
be	O
repositioned	O
to	O
cylinder	O
0	O
,	O
where	O
RDOS	B-Operating_System
wrote	O
the	O
first-level	O
boot	O
block	O
,	O
in	O
order	O
for	O
the	O
boot	O
sequence	O
to	O
work	O
.	O
</s>
<s>
Conventionally	O
this	O
was	O
done	O
by	O
cycling	O
the	O
drive	O
through	O
its	O
load	O
sequence	O
,	O
but	O
users	O
who	O
got	O
frustrated	O
with	O
the	O
wait	O
time	O
(	O
up	O
to	O
5	O
minutes	O
depending	O
on	O
the	O
drive	O
model	O
)	O
learned	O
how	O
to	O
input	O
from	O
the	O
front	B-Device
panel	I-Device
a	O
drive	O
"	O
recalibrate	O
"	O
I/O	B-General_Concept
code	O
and	O
single-step	O
the	O
CPU	O
through	O
it	O
,	O
an	O
operation	O
that	O
took	O
an	O
experienced	O
user	O
only	O
a	O
few	O
seconds	O
.	O
</s>
<s>
Turning	O
the	O
switch	O
to	O
LOCK	O
disabled	O
the	O
front	B-Device
panel	I-Device
function	O
switches	O
;	O
by	O
turning	O
the	O
switch	O
to	O
LOCK	O
and	O
removing	O
the	O
key	O
,	O
the	O
user	O
could	O
render	O
the	O
CPU	O
resistant	O
to	O
tampering	O
.	O
</s>
<s>
On	O
systems	O
with	O
magnetic	O
core	B-General_Concept
memory	I-General_Concept
,	O
the	O
LOCK	O
position	O
also	O
enabled	O
the	O
auto	O
power	O
failure	O
recovery	O
function	O
.	O
</s>
<s>
The	O
Nova	O
1200	O
executed	O
core	B-General_Concept
memory	I-General_Concept
access	O
instructions	O
(	O
LDA	O
and	O
STA	O
)	O
in	O
2.55	O
microseconds	O
( μs	O
)	O
.	O
</s>
<s>
Use	O
of	O
read-only	B-Device
memory	I-Device
saved	O
0.4	O
μs	O
.	O
</s>
<s>
Accumulator	B-General_Concept
instructions	O
(	O
ADD	O
,	O
SUB	O
,	O
COM	O
,	O
NEG	O
,	O
etc	O
.	O
)	O
</s>
<s>
It	O
is	O
designed	O
to	O
run	O
under	O
RDOS	B-Operating_System
and	O
prints	O
the	O
string	O
“	O
Hello	O
,	O
world.	O
”	O
on	O
the	O
console	O
.	O
</s>
<s>
The	O
following	O
routine	O
multiplies	O
two	O
16-bit	B-Device
words	O
to	O
produce	O
a	O
16-bit	B-Device
word	O
result	O
(	O
overflow	O
is	O
ignored	O
)	O
.	O
</s>
<s>
It	O
demonstrates	O
combined	O
use	O
of	O
ALU	B-General_Concept
op	O
,	O
shift	O
,	O
and	O
test	O
(	O
skip	O
)	O
.	O
</s>
<s>
Note	O
that	O
when	O
this	O
routine	O
is	O
called	O
by	O
jsr	O
,	O
AC3	O
holds	O
the	O
return	B-Language
address	I-Language
.	O
</s>
<s>
This	O
is	O
used	O
by	O
the	O
return	B-Language
instruction	I-Language
jmp	O
0	O
,	O
3	O
.	O
</s>
<s>
An	O
idiomatic	O
way	O
to	O
clear	O
an	O
accumulator	B-General_Concept
is	O
sub	O
0	O
,	O
0	O
.	O
</s>
<s>
The	O
following	O
routine	O
prints	O
the	O
value	O
of	O
AC1	O
as	O
a	O
16-digit	O
binary	O
number	O
,	O
on	O
the	O
RDOS	B-Operating_System
console	O
.	O
</s>
<s>
It	O
reveals	O
further	O
quirks	O
of	O
the	O
Nova	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
For	O
instance	O
,	O
there	O
is	O
no	O
instruction	O
to	O
load	O
an	O
arbitrary	O
"	O
immediate	O
"	O
value	O
into	O
an	O
accumulator	B-General_Concept
(	O
although	O
memory	O
reference	O
instructions	O
do	O
encode	O
such	O
a	O
value	O
to	O
form	O
an	O
effective	B-Language
address	I-Language
)	O
.	O
</s>
<s>
Accumulators	B-General_Concept
must	O
generally	O
be	O
loaded	O
from	O
initialized	O
memory	O
locations	O
(	O
e.g.	O
</s>
<s>
Other	O
contemporary	O
machines	O
such	O
as	O
the	O
PDP-11	B-Device
,	O
and	O
practically	O
all	O
modern	O
architectures	O
,	O
allow	O
for	O
immediate	O
loads	O
,	O
although	O
many	O
such	O
as	O
ARM	B-Architecture
restrict	O
the	O
range	O
of	O
values	O
that	O
can	O
be	O
loaded	O
immediately	O
.	O
</s>
<s>
Because	O
the	O
RDOS	B-Operating_System
.systm	O
call	O
macro	O
implements	O
a	O
jsr	O
,	O
AC3	O
is	O
overwritten	O
by	O
the	O
return	B-Language
address	I-Language
for	O
the	O
.pchar	O
function	O
.	O
</s>
<s>
Therefore	O
,	O
a	O
temporary	O
location	O
is	O
needed	O
to	O
preserve	O
the	O
return	B-Language
address	I-Language
of	O
the	O
caller	O
of	O
this	O
function	O
.	O
</s>
<s>
The	O
return	B-Language
instruction	I-Language
becomes	O
jmp	O
@	O
retrn	O
which	O
exploits	O
the	O
Nova	O
's	O
indirect	B-Language
addressing	I-Language
mode	O
to	O
load	O
the	O
return	O
PC	O
.	O
</s>
