<s>
The	O
DLX	B-Architecture
(	O
pronounced	O
"	O
Deluxe	O
"	O
)	O
is	O
a	O
RISC	B-Architecture
processor	I-Architecture
architecture	B-General_Concept
designed	O
by	O
John	O
L	O
.	O
Hennessy	O
and	O
David	O
A	O
.	O
Patterson	O
,	O
the	O
principal	O
designers	O
of	O
the	O
Stanford	B-General_Concept
MIPS	I-General_Concept
and	O
the	O
Berkeley	B-General_Concept
RISC	I-General_Concept
designs	O
(	O
respectively	O
)	O
,	O
the	O
two	O
benchmark	O
examples	O
of	O
RISC	B-Architecture
design	O
(	O
named	O
after	O
the	O
Berkeley	O
design	O
)	O
.	O
</s>
<s>
The	O
DLX	B-Architecture
is	O
essentially	O
a	O
cleaned	O
up	O
(	O
and	O
modernized	O
)	O
simplified	O
Stanford	B-General_Concept
MIPS	I-General_Concept
CPU	O
.	O
</s>
<s>
The	O
DLX	B-Architecture
has	O
a	O
simple	O
32-bit	O
load/store	B-Architecture
architecture	I-Architecture
,	O
somewhat	O
unlike	O
the	O
modern	O
MIPS	B-Device
architecture	I-Device
CPU	O
.	O
</s>
<s>
As	O
the	O
DLX	B-Architecture
was	O
intended	O
primarily	O
for	O
teaching	O
purposes	O
,	O
the	O
DLX	B-Architecture
design	O
is	O
widely	O
used	O
in	O
university-level	O
computer	B-General_Concept
architecture	I-General_Concept
courses	O
.	O
</s>
<s>
There	O
are	O
two	O
known	O
"	O
softcore	B-Device
"	O
hardware	O
implementations	O
:	O
ASPIDA	O
and	O
VAMP	O
.	O
</s>
<s>
The	O
ASPIDA	O
project	O
resulted	O
in	O
a	O
core	O
with	O
many	O
nice	O
features	O
:	O
it	O
is	O
open	O
source	O
,	O
supports	O
Wishbone	B-Architecture
,	O
has	O
an	O
asynchronous	O
design	O
,	O
supports	O
multiple	O
ISAs	O
,	O
and	O
is	O
ASIC	O
proven	O
.	O
</s>
<s>
VAMP	O
is	O
a	O
DLX-variant	O
that	O
was	O
mathematically	O
verified	O
as	O
part	O
of	O
Verisoft	O
project	O
.	O
</s>
<s>
It	O
was	O
specified	O
with	O
PVS	B-Application
,	O
implemented	O
in	O
Verilog	B-Language
,	O
and	O
runs	O
on	O
a	O
Xilinx	O
FPGA	B-Architecture
.	O
</s>
<s>
A	O
full	O
stack	O
from	O
compiler	O
to	O
kernel	O
to	O
TCP/IP	B-Protocol
was	O
built	O
on	O
it	O
.	O
</s>
<s>
In	O
the	O
Stanford	B-General_Concept
MIPS	I-General_Concept
architecture	B-General_Concept
,	O
one	O
of	O
the	O
methods	O
used	O
to	O
gain	O
performance	O
was	O
to	O
force	O
all	O
instructions	O
to	O
complete	O
in	O
one	O
clock	O
cycle	O
.	O
</s>
<s>
This	O
forced	O
compilers	O
to	O
insert	O
"	O
no-ops	B-Language
"	O
in	O
cases	O
where	O
the	O
instruction	O
would	O
definitely	O
take	O
longer	O
than	O
one	O
clock	O
cycle	O
.	O
</s>
<s>
In	O
general	O
MIPS	O
programs	O
were	O
forced	O
to	O
have	O
a	O
lot	O
of	O
wasteful	O
NOP	B-Language
instructions	O
,	O
a	O
behaviour	O
that	O
was	O
an	O
unintended	O
consequence	O
.	O
</s>
<s>
The	O
DLX	B-Architecture
architecture	B-General_Concept
does	O
not	O
force	O
single	O
clock	O
cycle	O
execution	O
,	O
and	O
is	O
therefore	O
immune	O
to	O
this	O
problem	O
.	O
</s>
<s>
In	O
the	O
DLX	B-Architecture
design	O
a	O
more	O
modern	O
approach	O
to	O
handling	O
long	O
instructions	O
was	O
used	O
:	O
data-forwarding	O
and	O
instruction	O
reordering	O
.	O
</s>
<s>
DLX	B-Architecture
instructions	O
can	O
be	O
broken	O
down	O
into	O
three	O
types	O
,	O
R-type	O
,	O
I-type	O
and	O
J-type	O
.	O
</s>
<s>
Opcodes	B-Language
are	O
6	O
bits	O
long	O
,	O
for	O
a	O
total	O
of	O
64	O
possible	O
basic	O
instructions	O
.	O
</s>
<s>
The	O
DLX	B-Architecture
can	O
support	O
more	O
than	O
64	O
instructions	O
,	O
as	O
long	O
as	O
those	O
instructions	O
work	O
purely	O
on	O
registers	O
.	O
</s>
<s>
This	O
quirk	O
is	O
useful	O
for	O
things	O
like	O
FPU	B-General_Concept
support	O
.	O
</s>
<s>
The	O
DLX	B-Architecture
,	O
like	O
the	O
MIPS	O
design	O
,	O
bases	O
its	O
performance	O
on	O
the	O
use	O
of	O
an	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
In	O
the	O
DLX	B-Architecture
design	O
this	O
is	O
a	O
fairly	O
simple	O
one	O
,	O
"	B-General_Concept
classic	I-General_Concept
"	I-General_Concept
RISC	I-General_Concept
in	O
concept	O
.	O
</s>
<s>
Operation	O
:	O
Send	O
out	O
the	O
PC	O
and	O
fetch	O
the	O
instruction	O
from	O
memory	O
into	O
the	O
Instruction	B-General_Concept
Register	I-General_Concept
(	O
IR	O
)	O
;	O
increment	O
the	O
PC	O
by	O
4	O
to	O
address	O
the	O
next	O
sequential	O
instruction	O
.	O
</s>
<s>
This	O
unit	O
gets	O
instruction	O
from	O
IF	O
,	O
and	O
extracts	O
opcode	B-Language
and	O
operand	O
from	O
that	O
instruction	O
.	O
</s>
<s>
Operation	O
:	O
The	O
ALU	B-General_Concept
operates	O
on	O
the	O
operands	O
prepared	O
in	O
prior	O
cycle	O
,	O
performing	O
one	O
of	O
the	O
four	O
functions	O
depending	O
on	O
the	O
DLX	B-Architecture
instruction	O
type	O
.	O
</s>
<s>
The	O
DLX	B-Architecture
instructions	O
active	O
in	O
this	O
unit	O
are	O
loads	O
,	O
stores	O
and	O
branches	O
.	O
</s>
<s>
Write	O
the	O
result	O
into	O
the	O
register	O
file	O
,	O
whether	O
it	O
comes	O
from	O
the	O
memory	O
system	O
or	O
from	O
the	O
ALU	B-General_Concept
.	O
</s>
