<s>
The	O
J-11	O
is	O
a	O
microprocessor	B-Architecture
chip	O
set	O
that	O
implements	O
the	O
PDP-11	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
jointly	O
developed	O
by	O
Digital	O
Equipment	O
Corporation	O
and	O
Intersil	O
.	O
</s>
<s>
It	O
was	O
a	O
high-end	O
chip	O
set	O
designed	O
to	O
integrate	O
the	O
performance	O
and	O
features	O
of	O
the	O
PDP-11/70	B-Device
onto	O
a	O
handful	O
of	O
chips	O
.	O
</s>
<s>
It	O
was	O
used	O
in	O
the	O
PDP-11/73	B-Device
,	O
PDP-11/83	O
and	O
Professional	B-Device
380	I-Device
.	O
</s>
<s>
The	O
data	O
path	O
chip	O
and	O
control	O
chip	O
were	O
fabricated	O
by	O
Intersil	O
in	O
a	O
CMOS	O
process	O
while	O
the	O
FPA	O
was	O
fabricated	O
by	O
Digital	O
in	O
their	O
"	O
ZMOS	B-Device
"	O
NMOS	O
process	O
.	O
</s>
<s>
The	O
design	O
originally	O
was	O
intended	O
to	O
support	O
multiple	O
control	O
chips	O
to	O
allow	O
implementation	O
of	O
additional	O
instructions	O
such	O
as	O
the	O
Commercial	O
Instruction	B-General_Concept
Set	I-General_Concept
(	O
CIS	O
)	O
,	O
but	O
no	O
such	O
control	O
chips	O
were	O
ever	O
offered	O
.	O
</s>
