<s>
The	O
Firefly	B-Device
was	O
a	O
shared	B-Operating_System
memory	I-Operating_System
asymmetric	B-Operating_System
multiprocessor	I-Operating_System
workstation	B-Device
,	O
developed	O
by	O
the	O
Systems	O
Research	O
Center	O
,	O
a	O
research	O
organization	O
within	O
Digital	O
Equipment	O
Corporation	O
.	O
</s>
<s>
The	O
first	O
version	O
built	O
contained	O
up	O
to	O
seven	O
MicroVAX	B-Device
78032	I-Device
microprocessors	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
from	O
each	O
of	O
the	O
microprocessors	O
kept	O
a	O
consistent	O
view	O
of	O
the	O
same	O
main	O
memory	O
using	O
a	O
cache	B-General_Concept
coherency	I-General_Concept
algorithm	O
,	O
the	O
Firefly	B-Device
protocol	I-Device
.	O
</s>
<s>
The	O
second	O
version	O
of	O
the	O
Firefly	B-Device
used	O
faster	O
CVAX	O
78034	O
microprocessors	O
.	O
</s>
<s>
The	O
Firefly	B-Device
was	O
an	O
asymmetric	B-Operating_System
multiprocessor	I-Operating_System
specialized	O
racked	O
computer	O
as	O
only	O
one	O
of	O
the	O
microprocessors	O
had	O
access	O
to	O
a	O
Q-Bus	B-Architecture
interface	O
that	O
implemented	O
the	O
I/O	O
subsystem	O
.	O
</s>
<s>
The	O
Firefly	B-Device
contained	O
a	O
primary	O
processor	O
board	O
and	O
zero	O
,	O
one	O
,	O
two	O
or	O
three	O
secondary	O
processor	O
boards	O
.	O
</s>
<s>
The	O
primary	O
processor	O
board	O
contained	O
a	O
microprocessor	O
,	O
its	O
floating-point	O
coprocessor	O
and	O
cache	B-General_Concept
,	O
and	O
the	O
Q-Bus	B-Architecture
control	O
logic	O
.	O
</s>
<s>
The	O
secondary	O
processor	O
boards	O
each	O
contained	O
two	O
microprocessors	O
,	O
their	O
floating-point	O
coprocessors	O
and	O
caches	B-General_Concept
.	O
</s>
<s>
The	O
original	O
Firefly	B-Device
processor	O
boards	O
used	O
the	O
MicroVAX	B-Device
78032	I-Device
microprocessor	O
and	O
MicroVAX	B-Device
78132	O
floating-point	O
coprocessor	O
,	O
but	O
later	O
Firefly	B-Device
systems	O
used	O
the	O
faster	O
CVAX	O
78034	O
microprocessors	O
,	O
CVAX	O
Floating	O
Point	O
Chips	O
(	O
floating-point	O
coprocessors	O
)	O
.	O
</s>
<s>
The	O
components	O
used	O
in	O
the	O
processor	O
boards	O
of	O
the	O
original	O
Firefly	B-Device
were	O
the	O
same	O
as	O
those	O
originally	O
designed	O
for	O
the	O
MicroVAX	B-Device
II	O
system	O
.	O
</s>
<s>
The	O
caches	B-General_Concept
in	O
the	O
Firefly	B-Device
were	O
direct-mapped	O
for	O
simplicity	O
and	O
to	O
support	O
multiprocessing	O
;	O
they	O
used	O
the	O
Firefly	B-Device
protocol	I-Device
to	O
ensure	O
cache	B-General_Concept
coherency	I-General_Concept
.	O
</s>
<s>
The	O
caches	B-General_Concept
on	O
the	O
MicroVAX	B-Device
processor	O
boards	O
had	O
a	O
capacity	O
of	O
16	O
KB	O
(	O
4,096	O
4-byte	O
lines	O
)	O
and	O
were	O
implemented	O
with	O
eleven	O
2	O
KB	O
(	O
4-bit	O
by	O
4,096	O
-word	O
)	O
SRAMs	B-Architecture
and	O
twenty	O
transistor	B-General_Concept
–	I-General_Concept
transistor	I-General_Concept
logic	I-General_Concept
(	O
TTL	B-General_Concept
)	O
devices	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
control	O
logic	O
was	O
implemented	O
with	O
fifteen	O
devices	O
,	O
mostly	O
consisting	O
of	O
programmable	O
array	O
logic	O
(	O
PAL	O
)	O
devices	O
.	O
</s>
<s>
The	O
caches	B-General_Concept
on	O
CVAX	O
processor	O
boards	O
differed	O
only	O
in	O
the	O
capacity	O
:	O
64	O
KB	O
(	O
16,384	O
4-byte	O
lines	O
)	O
and	O
were	O
implemented	O
with	O
8	O
KB	O
(	O
4-bit	O
by	O
16,384	O
-word	O
)	O
SRAMs	B-Architecture
.	O
</s>
<s>
Processors	O
in	O
the	O
Firefly	B-Device
communicated	O
with	O
the	O
main	O
memory	O
through	O
their	O
individual	O
caches	B-General_Concept
and	O
over	O
the	O
MBus	O
.	O
</s>
<s>
The	O
original	O
Firefly	B-Device
had	O
a	O
master	O
memory	O
module	O
with	O
a	O
capacity	O
of	O
4	O
MB	O
and	O
up	O
to	O
three	O
slave	O
memory	O
modules	O
of	O
the	O
same	O
capacity	O
for	O
a	O
memory	O
capacity	O
of	O
4	O
to	O
16	O
MB	O
.	O
</s>
<s>
Later	O
Firefly	B-Device
systems	O
used	O
a	O
memory	O
module	O
with	O
a	O
capacity	O
of	O
32	O
MB	O
,	O
for	O
a	O
memory	O
capacity	O
of	O
32	O
to	O
128	O
MB	O
.	O
</s>
<s>
The	O
memory	O
access	O
time	O
in	O
the	O
original	O
MicroVAX-based	O
Firefly	B-Device
was	O
400	O
ns	O
,	O
while	O
the	O
CVAX	O
version	O
had	O
a	O
memory	O
access	O
time	O
of	O
200	O
ns	O
.	O
</s>
<s>
I/O	O
devices	O
were	O
connected	O
to	O
the	O
system	O
via	O
the	O
Q-Bus	B-Architecture
,	O
whose	O
22-bit	O
address	O
space	O
was	O
mapped	O
onto	O
the	O
24-bit	O
memory	O
address	O
space	O
of	O
the	O
Firefly	B-Device
by	O
using	O
mapping	O
registers	O
controlled	O
by	O
the	O
master	O
processor	O
.	O
</s>
<s>
The	O
devices	O
used	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
to	O
access	O
the	O
memory	O
though	O
the	O
cache	B-General_Concept
of	O
the	O
main	O
processor	O
.	O
</s>
<s>
The	O
Firefly	B-Device
's	O
I/O	O
devices	O
were	O
:	O
a	O
monochrome	O
display	O
controller	O
(	O
MDC	O
)	O
,	O
a	O
buffered	O
controller	O
for	O
magnetic	O
disk	O
drives	O
,	O
the	O
RQDX3	O
and	O
an	O
DEQNA	O
Ethernet	O
controller	O
.	O
</s>
<s>
While	O
DEC	O
used	O
existing	O
components	O
for	O
most	O
of	O
the	O
I/O	O
system	O
,	O
the	O
display	O
controller	O
was	O
designed	O
specifically	O
for	O
the	O
Firefly	B-Device
by	O
the	O
project	O
's	O
engineers	O
who	O
felt	O
that	O
no	O
existing	O
product	O
met	O
their	O
performance	O
requirements	O
.	O
</s>
<s>
A	O
1024	O
by	O
1024-pixel	O
frame	O
buffer	O
was	O
implemented	O
with	O
VRAMs	O
,	O
with	O
three	O
quarters	O
used	O
to	O
hold	O
the	O
display	O
bitmap	O
with	O
the	O
rest	O
available	O
for	O
the	O
display	B-Device
manager	I-Device
or	O
used	O
to	O
cache	B-General_Concept
fonts	O
.	O
</s>
<s>
The	O
commands	O
performed	O
BitBlt	B-Algorithm
operations	O
within	O
the	O
frame	O
buffer	O
,	O
between	O
the	O
system	O
memory	O
and	O
frame	O
buffer	O
and	O
were	O
also	O
used	O
to	O
paint	O
characters	O
from	O
the	O
font	O
cache	B-General_Concept
.	O
</s>
<s>
As	O
a	O
result	O
of	O
implementing	O
the	O
MDC	O
as	O
an	O
I/O	O
device	O
,	O
the	O
Firefly	B-Device
supported	O
multiple	O
display	O
controllers	O
in	O
one	O
system	O
connected	O
to	O
multiple	O
monitors	O
.	O
</s>
<s>
Two	O
of	O
the	O
variants	O
of	O
the	O
Firefly	B-Device
used	O
system	O
software	O
called	O
Topaz	O
,	O
which	O
consisted	O
of	O
multiple	O
components	O
such	O
as	O
the	O
Taos	O
operating	B-General_Concept
system	I-General_Concept
that	O
used	O
a	O
microkernel	B-Operating_System
named	O
the	O
Nub	O
and	O
the	O
Trestle	O
window	B-Application
system	I-Application
.	O
</s>
<s>
One	O
of	O
the	O
features	O
of	O
Taos	O
was	O
that	O
it	O
supported	O
the	O
Ultrix	B-Operating_System
binary	O
calling	O
interface	O
,	O
allowed	O
existing	O
Ultrix	B-Operating_System
binaries	O
compiled	O
for	O
the	O
MicroVAX	B-Device
run	O
unmodified	O
image	O
on	O
the	O
Firefly	B-Device
.	O
</s>
<s>
In	O
contrast	O
to	O
Ultrix	B-Operating_System
,	O
Topaz	O
supported	O
processes	O
with	O
multiple	O
threads	O
which	O
could	O
span	O
multiple	O
processors	O
,	O
and	O
the	O
Taos	O
system	O
could	O
run	O
both	O
Ultrix	B-Operating_System
and	O
Topaz	O
applications	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Modula-2	B-Language
+	I-Language
,	O
(	O
a	O
Modula-2	B-Language
extended	O
language	O
)	O
was	O
used	O
to	O
program	O
both	O
Topaz	O
and	O
its	O
applications	O
.	O
</s>
<s>
The	O
Stanford	O
V	B-Operating_System
(	O
operating	B-General_Concept
system	I-General_Concept
)	O
also	O
supported	O
Firefly	B-Device
in	O
a	O
configuration	O
with	O
one	O
CVAX	O
and	O
four	O
Microvax-II	O
CPUs	O
in	O
a	O
BA123	O
chassis	O
and	O
QVSS	O
?	O
VCB01	O
graphics	O
.	O
</s>
