<s>
The	O
DEC	B-Device
4000	I-Device
AXP	I-Device
is	O
a	O
series	O
of	O
departmental	O
server	B-Application
computers	I-Application
developed	O
and	O
manufactured	O
by	O
Digital	O
Equipment	O
Corporation	O
introduced	O
on	O
10	O
November	O
1992	O
.	O
</s>
<s>
These	O
systems	O
formed	O
part	O
of	O
the	O
first	O
generation	O
of	O
systems	O
based	O
on	O
the	O
64-bit	B-Device
Alpha	B-Device
AXP	I-Device
architecture	B-General_Concept
and	O
at	O
the	O
time	O
of	O
introduction	O
,	O
ran	O
Digital	O
's	O
OpenVMS	B-Operating_System
AXP	I-Operating_System
or	O
OSF/1	B-Operating_System
AXP	I-Operating_System
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
The	O
DEC	B-Device
4000	I-Device
AXP	I-Device
was	O
succeeded	O
by	O
the	O
end	O
of	O
1994	O
by	O
the	O
AlphaServer	B-Device
2000	O
and	O
2100	O
departmental	O
servers	O
.	O
</s>
<s>
There	O
are	O
two	O
models	O
of	O
the	O
DEC	B-Device
4000	I-Device
AXP	I-Device
:	O
</s>
<s>
Model	O
6x0	O
,	O
code	O
named	O
Cobra	O
:	O
160	O
MHz	O
DECchip	B-General_Concept
21064	I-General_Concept
(	O
EV4	O
)	O
processor(s )	O
with	O
1	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
each	O
.	O
</s>
<s>
Model	O
7x0	O
,	O
code	O
named	O
Fang	O
:	O
190	O
MHz	O
DECchip	B-General_Concept
21064	I-General_Concept
(	O
EV4	O
)	O
processor(s )	O
with	O
4	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
each	O
.	O
</s>
<s>
These	O
numbers	O
specify	O
the	O
number	O
of	O
microprocessors	B-Architecture
in	O
the	O
system	O
.	O
</s>
<s>
The	O
DEC	B-Device
4000	I-Device
AXP	I-Device
are	O
two-way	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
capable	O
systems	O
that	O
are	O
housed	O
in	O
either	O
a	O
BA640	O
half-height	O
cabinet	O
or	O
a	O
BA641	O
19-inch	O
rackmountable	O
enclosure	O
that	O
contains	O
two	O
backplanes	B-Architecture
,	O
a	O
system	O
backplane	B-Architecture
and	O
a	O
storage	O
backplane	B-Architecture
.	O
</s>
<s>
Plugged	O
in	O
the	O
system	O
backplane	B-Architecture
were	O
one	O
or	O
two	O
CPU	O
modules	O
,	O
one	O
to	O
four	O
memory	O
modules	O
,	O
an	O
I/O	B-General_Concept
module	O
,	O
up	O
to	O
six	O
Futurebus+	B-Architecture
Profile	I-Architecture
B	I-Architecture
modules	O
,	O
and	O
in	O
the	O
storage	O
backplane	B-Architecture
,	O
were	O
one	O
to	O
four	O
fixed	O
media	O
mass	O
storage	O
compartments	O
and	O
one	O
removable	O
media	O
mass	O
storage	O
compartment	O
.	O
</s>
<s>
Two	O
models	O
of	O
CPU	O
module	O
were	O
used	O
in	O
the	O
DEC	B-Device
4000	I-Device
AXP	I-Device
,	O
the	O
KN430	O
(	O
also	O
known	O
as	O
the	O
B2001-BA	O
)	O
,	O
used	O
in	O
the	O
Model	O
600	O
Series	O
,	O
and	O
the	O
B2012-AA	O
,	O
used	O
in	O
the	O
Model	O
700	O
Series	O
.	O
</s>
<s>
The	O
KN430	O
contains	O
a	O
160	O
MHz	O
DECchip	B-General_Concept
21064	I-General_Concept
microprocessor	B-Architecture
with	O
1	O
MB	O
of	O
B-cache	O
(	O
L2	B-General_Concept
cache	I-General_Concept
)	O
,	O
whereas	O
the	O
B2012-AA	O
contains	O
a	O
190	O
MHz	O
DECchip	B-General_Concept
21064	I-General_Concept
with	O
4	O
MB	O
of	O
B-cache	O
.	O
</s>
<s>
Two	O
C3	O
(	O
Command	O
,	O
Control	O
and	O
Communication	O
)	O
ASICs	O
on	O
the	O
CPU	O
module	O
provide	O
a	O
number	O
of	O
functions	O
,	O
such	O
as	O
implementing	O
the	O
B-cache	O
controller	O
and	O
the	O
bus	O
interface	O
unit	O
(	O
BIU	O
)	O
,	O
which	O
interfaces	O
the	O
microprocessor	B-Architecture
to	O
the	O
128-bit	O
address	B-Architecture
and	O
data	B-General_Concept
multiplexed	B-Architecture
system	O
bus	O
to	O
enable	O
communication	O
between	O
the	O
CPU	O
,	O
memory	O
and	O
I/O	B-General_Concept
modules	O
.	O
</s>
<s>
The	O
memory	O
is	O
organised	O
into	O
four	O
banks	O
,	O
each	O
280	O
bits	O
wide	O
,	O
of	O
which	O
256	O
bits	O
are	O
used	O
to	O
store	O
data	B-General_Concept
and	O
24	O
bits	O
are	O
used	O
to	O
store	O
error	O
detection	O
and	O
correction	O
(	O
EDC	O
)	O
information	O
.	O
</s>
<s>
The	O
memory	O
is	O
implemented	O
using	O
280	O
surface	O
mounted	O
dual	B-Algorithm
in-line	I-Algorithm
package	I-Algorithm
(	O
DIP	B-Algorithm
)	O
4-bit	O
dynamic	O
random	O
access	O
memory	O
(	O
DRAM	O
)	O
chips	O
with	O
capacities	O
of	O
1	O
,	O
4	O
and	O
16	O
Mb	O
that	O
reside	O
on	O
both	O
sides	O
of	O
the	O
module	O
.	O
</s>
<s>
The	O
CMIC	O
ASICs	O
are	O
fabricated	O
in	O
a	O
CMOS	O
process	O
and	O
are	O
packaged	O
in	O
a	O
299-position	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PGA	O
)	O
package	O
.	O
</s>
<s>
The	O
memory	O
module	O
is	O
the	O
same	O
size	O
as	O
the	O
CPU	O
module	O
and	O
connects	O
to	O
the	O
backplane	B-Architecture
via	O
two	O
129-pin	O
and	O
four	O
24-pin	O
connectors	O
.	O
</s>
<s>
The	O
DEC	B-Device
4000	I-Device
AXP	I-Device
uses	O
the	O
KFA40	O
I/O	B-General_Concept
module	O
,	O
which	O
contains	O
the	O
entire	O
I/O	B-General_Concept
subsystem	O
.	O
</s>
<s>
The	O
I/O	B-General_Concept
module	O
is	O
the	O
largest	O
module	O
in	O
the	O
system	O
,	O
and	O
two	O
variants	O
existed	O
.	O
</s>
<s>
The	O
first	O
variant	O
offered	O
four	O
SCSI-2	B-Architecture
buses	O
and	O
two	O
Ethernet	O
ports	O
and	O
the	O
second	O
variant	O
offered	O
four	O
DSSI/SCSI	O
buses	O
and	O
one	O
Ethernet	O
port	O
.	O
</s>
<s>
The	O
second	O
variant	O
however	O
only	O
has	O
half	O
the	O
bandwidth	O
of	O
the	O
SCSI-2	B-Architecture
buses	O
of	O
the	O
first	O
variant	O
,	O
although	O
the	O
advanced	O
features	O
of	O
DSSI	B-Architecture
justified	O
its	O
use	O
in	O
some	O
cases	O
.	O
</s>
<s>
Aside	O
from	O
these	O
differences	O
,	O
the	O
rest	O
of	O
the	O
I/O	B-General_Concept
module	O
was	O
essentially	O
the	O
same	O
.	O
</s>
<s>
I/O	B-General_Concept
module	O
features	O
common	O
to	O
both	O
variants	O
are	O
an	O
additional	O
SCSI-2	B-Architecture
bus	O
for	O
removable	O
media	O
drives	O
only	O
,	O
a	O
Zilog	O
85C30	O
Serial	O
Communications	O
Controller	O
(	O
UART	O
)	O
that	O
provides	O
two	O
serial	B-Protocol
lines	I-Protocol
,	O
a	O
Dallas	O
Semiconductor	O
DS1287	O
real-time	O
clock	O
,	O
and	O
most	O
of	O
the	O
firmware	O
in	O
the	O
DEC	B-Device
4000	I-Device
AXP	I-Device
.	O
</s>
<s>
For	O
controlling	O
the	O
Futurebus+	O
and	O
to	O
interface	O
the	O
I/O	B-General_Concept
module	O
to	O
the	O
system	O
bus	O
,	O
two	O
IONIC	O
ASICs	O
are	O
used	O
.	O
</s>
<s>
The	O
Ethernet	O
functionality	O
in	O
the	O
I/O	B-General_Concept
function	O
is	O
provided	O
by	O
the	O
TGEC	O
(	O
Third	O
Generation	O
Ethernet	O
Chip	O
)	O
,	O
also	O
known	O
as	O
the	O
DC253	O
,	O
while	O
the	O
SCSI/DSSI	O
buses	O
are	O
provided	O
by	O
four	O
NCR	O
53C710	O
SCSI/DSSI	O
controllers	O
and	O
their	O
associated	O
DSSI	B-Architecture
drivers	O
(	O
second	O
I/O	B-General_Concept
module	O
variant	O
only	O
)	O
.	O
</s>
<s>
Most	O
of	O
the	O
I/O	B-General_Concept
devices	I-General_Concept
are	O
connected	O
to	O
the	O
local	O
I/O	B-General_Concept
bus	I-General_Concept
,	O
known	O
as	O
the	O
"	O
Lbus	O
"	O
,	O
a	O
32-bit	O
address	B-Architecture
and	O
data	B-General_Concept
multiplexed	B-Architecture
bus	O
.	O
</s>
<s>
The	O
DEC	B-Device
4000	I-Device
AXP	I-Device
has	O
four	O
fixed	O
media	O
mass	O
storage	O
compartments	O
,	O
each	O
capable	O
of	O
holding	O
one	O
5¼	O
inch	O
or	O
four	O
3½	O
inch	O
devices	O
.	O
</s>
<s>
In	O
addition	O
to	O
internal	O
storage	O
,	O
an	O
external	O
storage	O
cabinet	O
could	O
be	O
attached	O
via	O
an	O
external	O
SCSI	B-Architecture
port	O
to	O
provide	O
more	O
storage	O
.	O
</s>
<s>
The	O
DEC	B-Device
4000	I-Device
AXP	I-Device
systems	O
used	O
the	O
Futurebus+	B-Architecture
Profile	I-Architecture
B	I-Architecture
for	O
expansion	O
,	O
with	O
six	O
slots	O
.	O
</s>
