<s>
The	O
Cyrix	B-Device
Cx486DLC	I-Device
is	O
an	O
x86	B-Operating_System
desktop	O
microprocessor	B-Architecture
developed	O
by	O
Cyrix	O
.	O
</s>
<s>
It	O
was	O
Cyrix	O
's	O
second	O
CPU	B-Device
offering	O
,	O
released	O
years	O
after	O
selling	O
math	B-General_Concept
coprocessors	I-General_Concept
that	O
competed	O
with	O
Intel	O
's	O
units	O
and	O
offered	O
better	O
performance	O
at	O
a	O
comparable	O
or	O
lower	O
price	O
.	O
</s>
<s>
The	O
486DLC	B-Device
was	O
a	O
486	B-General_Concept
desktop	O
CPU	B-Device
from	O
Cyrix	O
,	O
intended	O
to	O
compete	O
with	O
the	O
Intel	O
486SX	O
and	O
DX	O
.	O
</s>
<s>
Texas	O
Instruments	O
,	O
who	O
manufactured	O
the	O
486DLC	B-Device
for	O
Cyrix	O
,	O
later	O
released	O
its	O
own	O
version	O
of	O
the	O
chip	O
,	O
the	O
TI486SXL	O
,	O
with	O
8	O
KB	O
internal	O
cache	O
vs	O
1	O
KB	O
of	O
the	O
original	O
Cyrix	O
design	O
.	O
</s>
<s>
The	O
similarly	O
named	O
IBM	B-Device
486DLC	I-Device
,	O
486DLC2	O
,	O
486DLC3	O
(	O
aka	O
Blue	O
Lightning	O
)	O
are	O
often	O
confused	O
with	O
the	O
Cyrix	O
chips	O
,	O
but	O
are	O
not	O
related	O
and	O
are	O
instead	O
based	O
on	O
Intel	O
's	O
i486	B-General_Concept
design	O
.	O
</s>
<s>
Like	O
the	O
later	O
and	O
more	O
famous	O
Cyrix	B-Device
Cx5x86	I-Device
,	O
it	O
was	O
a	O
hybrid	O
CPU	B-Device
,	O
incorporating	O
features	O
of	O
a	O
new	O
CPU	B-Device
(	O
the	O
Intel	B-General_Concept
80486	I-General_Concept
)	O
while	O
plugging	O
into	O
its	O
predecessor	O
's	O
(	O
386DX	O
)	O
PGA132	O
socket	B-General_Concept
.	O
</s>
<s>
The	O
486DLC	B-Device
can	O
be	O
described	O
as	O
a	O
386DX	O
with	O
the	O
486	B-General_Concept
instruction	O
set	O
and	O
1KB	O
of	O
on-board	O
L1	O
cache	O
added	O
.	O
</s>
<s>
Because	O
it	O
used	O
the	O
386DX	O
bus	O
(	O
unlike	O
its	O
16-bit	O
cousin	O
,	O
the	O
486SLC	B-Device
)	O
,	O
it	O
was	O
a	O
fully	O
32-bit	O
chip	O
.	O
</s>
<s>
Like	O
the	O
386	O
and	O
486SX	O
,	O
it	O
had	O
no	O
on-board	O
math	B-General_Concept
coprocessor	I-General_Concept
,	O
but	O
unlike	O
the	O
486SX	O
,	O
it	O
could	O
make	O
use	O
of	O
an	O
Intel	O
387DX	O
or	O
compatible	O
numeric	O
x87	B-Application
coprocessor	B-General_Concept
.	O
</s>
<s>
Due	O
to	O
the	O
smaller	O
L1	O
cache	O
,	O
the	O
486DLC	B-Device
could	O
not	O
compete	O
on	O
a	O
clock-for-clock	O
basis	O
with	O
the	O
486SX	O
,	O
but	O
a	O
33MHz	O
486DLC	B-Device
could	O
keep	O
pace	O
with	O
a	O
25MHz	O
486SX	O
,	O
cost	O
less	O
,	O
and	O
offered	O
the	O
ability	O
to	O
upgrade	O
further	O
with	O
the	O
addition	O
of	O
an	O
inexpensive	O
math	B-General_Concept
coprocessor	I-General_Concept
.	O
</s>
<s>
While	O
some	O
advertisements	O
from	O
smaller	O
manufacturers	O
touted	O
the	O
superiority	O
of	O
their	O
486DLC	B-Device
over	O
name-brand	O
computers	O
sporting	O
a	O
486SX	O
,	O
in	O
reality	O
the	O
only	O
advantage	O
the	O
486DLC	B-Device
offered	O
feature-wise	O
over	O
the	O
486SX	O
was	O
the	O
ability	O
to	O
add	O
an	O
inexpensive	O
math	B-General_Concept
coprocessor	I-General_Concept
.	O
</s>
<s>
The	O
Intel	O
487	O
"	O
math	B-General_Concept
coprocessor	I-General_Concept
"	O
for	O
486SX	O
users	O
was	O
in	O
reality	O
a	O
CPU	B-Device
replacementa	O
486DX	B-General_Concept
with	O
a	O
different	O
pinoutand	O
originally	O
cost	O
several	O
hundred	O
dollars	O
more	O
than	O
a	O
387	O
.	O
</s>
<s>
As	O
prices	O
on	O
Intel	O
's	O
486	B-General_Concept
line	O
fell	O
,	O
Cyrix	O
found	O
it	O
more	O
and	O
more	O
difficult	O
for	O
its	O
486SLC	B-Device
and	O
DLC	O
CPUs	B-Device
to	O
compete	O
and	O
released	O
a	O
fully	O
pin-compatible	O
version	O
of	O
the	O
486SX	O
and	O
DX	O
in	O
1993	O
.	O
</s>
<s>
The	O
486DLC	B-Device
did	O
not	O
see	O
widespread	O
use	O
among	O
large	O
OEMs	O
,	O
but	O
it	O
was	O
widely	O
known	O
among	O
the	O
hardware	O
enthusiast	O
community	O
that	O
an	O
AMD	B-Device
386DX-40	I-Device
or	O
Cyrix	O
486DLC-33	O
could	O
keep	O
up	O
with	O
a	O
486SX-25	O
at	O
a	O
lower	O
cost	O
,	O
so	O
it	O
gained	O
a	O
small	O
following	O
among	O
budget-minded	O
enthusiasts	O
.	O
</s>
<s>
It	O
was	O
also	O
sometimes	O
used	O
as	O
a	O
replacement	O
for	O
a	O
386	O
CPU	B-Device
to	O
give	O
a	O
small	O
speed	O
boost	O
.	O
</s>
<s>
However	O
,	O
the	O
486DLC	B-Device
was	O
not	O
designed	O
to	O
be	O
a	O
direct	O
CPU	B-Device
replacement	O
and	O
could	O
lead	O
to	O
stability	O
problems	O
in	O
older	O
boards	O
it	O
was	O
not	O
intended	O
for	O
.	O
</s>
<s>
"	O
Cyrix-aware	O
"	O
motherboards	O
usually	O
had	O
a	O
few	O
extra	O
cache	O
control	O
lines	O
to	O
maintain	O
cache	O
coherency	O
,	O
as	O
well	O
as	O
CPU	B-Device
register	O
control	O
in	O
the	O
BIOS	O
to	O
enable/disable	O
the	O
on-board	O
cache	O
.	O
</s>
<s>
This	O
kit	O
included	O
a	O
standard	O
486DLC	B-Device
with	O
an	O
extra	O
"	O
dingus	O
"	O
that	O
sat	O
between	O
the	O
CPU	B-Device
and	O
socket	B-General_Concept
and	O
provided	O
the	O
control	O
lines	O
for	O
cache	O
coherency	O
.	O
</s>
<s>
These	O
kits	O
were	O
quickly	O
superseded	O
by	O
the	O
Cx486DRx2	O
CPU	B-Device
,	O
which	O
integrated	O
the	O
cache	O
coherency	O
circuitry	O
into	O
the	O
CPU	B-Device
itself	O
.	O
</s>
<s>
The	O
Cx486DRx2	O
appeared	O
on	O
the	O
market	O
in	O
1994	O
,	O
by	O
which	O
time	O
the	O
486	B-General_Concept
was	O
already	O
being	O
displaced	O
by	O
the	O
Pentium	O
.	O
</s>
<s>
It	O
was	O
often	O
cheaper	O
to	O
purchase	O
a	O
new	O
486	B-General_Concept
motherboard	O
than	O
to	O
invest	O
in	O
an	O
upgrade	O
CPU	B-Device
.	O
</s>
<s>
ModelBus	O
SpeedFrequencyCacheVoltageNotesTX486DLC-25-GA25	O
MHz25	O
MHz1	O
KB5V132-pin	O
PGA	B-Algorithm
package.TX486DLC-33-BGA33	O
MHz33	O
MHz1	O
KB5VTX486DLC/E	O
-33-GA33	O
MHz33	O
MHz1	O
KB5VAdvanced	O
power	O
management	O
,	O
132-pin	O
PGA	B-Algorithm
package.TX486DLC/E	O
-V33-GA33	O
MHz33	O
MHz1	O
KB3.3VAdvanced	O
power	O
management	O
,	O
low	O
voltage	O
,	O
132-pin	O
PGA	B-Algorithm
package.TX486DLC-40-BGA40	O
MHz40	O
MHz1	O
KB5V132-pin	O
PGA	B-Algorithm
package.TX486DLC/E	O
-40-GA40	O
MHz40	O
MHz1	O
KB5VAdvanced	O
power	O
management	O
,	O
132-pin	O
PGA	B-Algorithm
package	O
.	O
</s>
<s>
+Reference	O
GuideModelBus	O
SpeedFrequencyCacheVoltageNotesTI486SXL-040S-GA20-40	O
MHz†40	O
MHz8	O
KB5V132-pin	O
PGA	B-Algorithm
package.TI486SXL2-050S-GA25	O
MHz50	O
MHz8	O
KB5VTI486SXL-040-PCE20-40	O
MHz†40	O
MHz8	O
KB5V144-pin	O
TEP	O
package.TI486SXL-G40-HBN20-40	O
MHz†40	O
MHz8	O
KB3.3	O
,	O
5V•	O
144-pin	O
QFP	B-Algorithm
ceramic	O
package.TI486SXL2-G50-HBN25	O
MHz50	O
MHz8	O
KB3.3	O
,	O
5V•	O
TI486SXL-040-HBN20-40	O
MHz†40	O
MHz8	O
KB5VTI486SXL2-050-HBN25	O
MHz50	O
MHz8	O
KB5VTI486SXL-G40-GA20-40	O
MHz†40	O
MHz8	O
KB3.3	O
,	O
5V•	O
168-pin	O
PGA	B-Algorithm
package.TI486SXL2-G50-GA25	O
MHz50	O
MHz8	O
KB3.3	O
,	O
5V•	O
TI486SXL2-G66-GA33	O
MHz66	O
MHz8	O
KB3.3	O
,	O
5V•	O
TI486SXL-V40-GA20-40	O
MHz†40	O
MHz8	O
KB3.3VLow-power	O
version	O
,	O
168-pin	O
PGA	B-Algorithm
package.TI486SXL2-V50-GA25	O
MHz50	O
MHz8	O
KB3.3VTI486SXL-040-GA20-40	O
MHz†40	O
MHz8	O
KB5V168-pin	O
PGA	B-Algorithm
package.TI486SXL2-050-GA25	O
MHz50	O
MHz8	O
KB5V†	O
-	O
Can	O
operate	O
at	O
nonclock-doubled	O
40	O
MHz	O
or	O
clock-doubled	O
20/40	O
MHz	O
.	O
</s>
