<s>
The	O
Cyrix	B-General_Concept
6x86	I-General_Concept
is	O
a	O
line	O
of	O
sixth-generation	O
,	O
32-bit	B-Device
x86	I-Device
microprocessors	B-Architecture
designed	O
and	O
released	O
by	O
Cyrix	O
in	O
1995	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
was	O
made	O
as	O
a	O
direct	O
competitor	O
to	O
Intel	O
's	O
Pentium	B-General_Concept
microprocessor	B-Architecture
line	O
,	O
and	O
was	O
pin	O
compatible	O
.	O
</s>
<s>
During	O
the	O
6x86	B-General_Concept
's	O
development	O
,	O
the	O
majority	O
of	O
applications	O
(	O
office	B-Application
software	I-Application
as	O
well	O
as	O
games	O
)	O
performed	O
almost	O
entirely	O
integer	O
operations	O
.	O
</s>
<s>
This	O
would	O
later	O
prove	O
to	O
be	O
a	O
strategic	O
mistake	O
,	O
as	O
the	O
popularity	O
of	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
caused	O
many	O
software	B-Application
developers	I-Application
to	O
hand-optimize	O
code	O
in	O
assembly	B-Language
language	I-Language
,	O
to	O
take	O
advantage	O
of	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
's	O
tightly	O
pipelined	O
and	O
lower	O
latency	O
FPU	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
the	O
highly	O
anticipated	O
first-person	O
shooter	O
Quake	B-Application
used	O
highly	O
optimized	O
assembly	O
code	O
designed	O
almost	O
entirely	O
around	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
's	O
FPU	B-General_Concept
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
significantly	O
outperformed	O
other	O
CPUs	O
in	O
the	O
game	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
,	O
previously	O
under	O
the	O
codename	O
"	O
M1	O
"	O
was	O
announced	O
by	O
Cyrix	O
in	O
October	O
1995	O
.	O
</s>
<s>
The	O
100MHz	O
(	O
P120+	O
)	O
6x86	B-General_Concept
was	O
available	O
to	O
OEMs	O
for	O
a	O
price	O
of	O
$450	O
per	O
chip	O
in	O
bulk	O
quantities	O
.	O
</s>
<s>
In	O
mid	O
February	O
1996	O
Cyrix	O
announced	O
the	O
P166+	O
,	O
P150+	O
,	O
and	O
P133+	O
to	O
be	O
added	O
to	O
the	O
6x86	B-General_Concept
model	O
line	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
P200+	O
was	O
planned	O
for	O
the	O
end	O
of	O
1996	O
,	O
and	O
ended	O
up	O
being	O
released	O
in	O
June	O
.	O
</s>
<s>
The	O
M2	O
(	O
6x86MX	B-General_Concept
)	O
was	O
first	O
announced	O
to	O
be	O
in	O
development	O
in	O
mid	O
1996	O
.	O
</s>
<s>
It	O
would	O
have	O
MMX	B-Architecture
and	O
32-bit	O
optimization	O
.	O
</s>
<s>
The	O
M2	O
would	O
also	O
have	O
some	O
of	O
the	O
same	O
features	O
as	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
such	O
as	O
register	B-Architecture
renaming	I-Architecture
,	O
out-of-order	O
completion	O
,	O
and	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
Additionally	O
it	O
would	O
have	O
64	O
KB	O
of	O
cache	B-General_Concept
over	O
the	O
original	O
6x86	B-General_Concept
and	O
Pentium	B-Device
Pro	I-Device
's	O
16	O
KB	O
.	O
</s>
<s>
The	O
6x86L	B-General_Concept
was	O
first	O
released	O
in	O
January	O
1997	O
to	O
address	O
the	O
heat	O
issues	O
with	O
the	O
original	O
6x86	B-General_Concept
line	O
.	O
</s>
<s>
The	O
6x86L	B-General_Concept
had	O
a	O
lower	O
V-core	O
voltage	O
and	O
required	O
a	O
split	O
powerplane	O
voltage	O
regulator	O
.	O
</s>
<s>
In	O
April	O
1997	O
the	O
first	O
laptop	O
to	O
use	O
the	O
6x86	B-General_Concept
processor	O
was	O
put	O
on	O
sale	O
.	O
</s>
<s>
Later	O
by	O
the	O
end	O
of	O
May	O
1997	O
on	O
the	O
27th	O
,	O
Cyrix	O
said	O
they	O
would	O
announce	O
details	O
of	O
the	O
new	O
chip	O
line	O
(	O
6x86MX	B-General_Concept
)	O
the	O
day	O
before	O
Computex	O
in	O
June	O
1997	O
.	O
</s>
<s>
For	O
the	O
low	O
end	O
of	O
the	O
series	O
,	O
the	O
PR166	O
6x86MX	B-General_Concept
was	O
available	O
for	O
$190	O
with	O
higher	O
end	O
PR200	O
and	O
PR233	O
versions	O
available	O
for	O
$240	O
and	O
$320	O
.	O
</s>
<s>
They	O
had	O
slightly	O
better	O
floating	O
point	O
performance	O
,	O
which	O
cut	O
adding	O
and	O
multiply	O
times	O
by	O
a	O
third	O
,	O
but	O
it	O
was	O
still	O
slower	O
than	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
.	O
</s>
<s>
The	O
M2	O
also	O
had	O
full	O
MMX	B-Architecture
instructions	O
,	O
64KB	O
of	O
cache	B-General_Concept
over	O
the	O
original	O
16KB	O
,	O
and	O
had	O
a	O
lower	O
core	O
voltage	O
of	O
2.5V	O
over	O
3.3V	O
of	O
the	O
original	O
6x86	B-General_Concept
line	O
.	O
</s>
<s>
National	O
Semiconductor	O
was	O
not	O
interested	O
in	O
high	O
performance	O
processors	O
but	O
rather	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
devices	O
,	O
and	O
wanted	O
to	O
shift	O
the	O
focus	O
of	O
Cyrix	O
to	O
the	O
MediaGX	B-Device
line	O
.	O
</s>
<s>
In	O
January	O
1998	O
National	O
Semiconductors	O
produced	O
a	O
6x86MX	B-General_Concept
processor	O
on	O
a	O
0.25	O
micron	O
process	O
technology	O
.	O
</s>
<s>
National	O
shifted	O
their	O
production	O
of	O
the	O
MII	O
and	O
MediaGX	B-Device
to	O
0.25	O
by	O
August	O
.	O
</s>
<s>
These	O
chips	O
were	O
not	O
exciting	O
like	O
people	O
had	O
hoped	O
,	O
as	O
they	O
were	O
just	O
a	O
rebranding	O
of	O
the	O
6x86MX	B-General_Concept
.	O
</s>
<s>
Additionally	O
after	O
VIA	O
's	O
acquisition	O
,	O
the	O
6x86/L	O
was	O
discontinued	O
,	O
but	O
the	O
6x86MX/MII	O
line	O
continued	O
to	O
be	O
sold	O
by	O
VIA	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
is	O
superscalar	B-General_Concept
and	O
superpipelined	B-General_Concept
and	O
performs	O
register	B-Architecture
renaming	I-Architecture
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
and	O
data	B-Operating_System
dependency	I-Operating_System
removal	O
.	O
</s>
<s>
However	O
,	O
it	O
continued	O
to	O
use	O
native	O
x86	B-Operating_System
execution	O
and	O
ordinary	O
microcode	B-Device
only	O
,	O
like	O
Centaur	O
's	O
Winchip	B-Device
,	O
unlike	O
competitors	O
Intel	O
and	O
AMD	O
which	O
introduced	O
the	O
method	O
of	O
dynamic	O
translation	O
to	O
micro-operations	B-General_Concept
with	O
Pentium	B-Device
Pro	I-Device
and	O
K5	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
is	O
socket-compatible	O
with	O
the	O
Intel	O
P54C	O
Pentium	B-General_Concept
,	O
and	O
was	O
offered	O
in	O
six	O
performance	O
levels	O
:	O
PR	O
90+	O
,	O
PR	O
120+	O
,	O
PR	O
133+	O
,	O
PR	O
150+	O
,	O
PR	O
166+	O
and	O
PR	O
200+	O
.	O
</s>
<s>
With	O
regard	O
to	O
internal	B-General_Concept
caches	I-General_Concept
,	O
it	O
has	O
a	O
16-KB	O
primary	O
cache	B-General_Concept
and	O
a	O
fully	O
associative	O
256-byte	O
instruction	O
line	O
cache	B-General_Concept
is	O
included	O
alongside	O
the	O
primary	O
cache	B-General_Concept
,	O
which	O
functions	O
as	O
the	O
primary	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
6x86	B-General_Concept
and	O
6x86L	B-General_Concept
were	O
not	O
completely	O
compatible	O
with	O
the	O
Intel	B-General_Concept
P5	I-General_Concept
Pentium	B-General_Concept
instruction	O
set	O
and	O
is	O
not	O
multi-processor	O
capable	O
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
the	O
chip	O
identified	O
itself	O
as	O
an	O
80486	B-General_Concept
and	O
disabled	O
the	O
CPUID	B-Architecture
instruction	O
by	O
default	O
.	O
</s>
<s>
CPUID	B-Architecture
support	O
could	O
be	O
enabled	O
by	O
first	O
enabling	O
extended	O
CCR	O
registers	O
then	O
setting	O
bit	O
7	O
in	O
CCR4	O
.	O
</s>
<s>
The	O
lack	O
of	O
full	O
P5	B-General_Concept
Pentium	B-General_Concept
compatibility	O
caused	O
problems	O
with	O
some	O
applications	O
because	O
programmers	B-Application
had	O
begun	O
to	O
use	O
P5	B-General_Concept
Pentium-specific	O
instructions	O
.	O
</s>
<s>
Some	O
companies	O
released	O
patches	O
for	O
their	O
products	O
to	O
make	O
them	O
function	O
on	O
the	O
6x86	B-General_Concept
.	O
</s>
<s>
Compatibility	O
with	O
the	O
Pentium	B-General_Concept
was	O
improved	O
in	O
the	O
6x86MX	B-General_Concept
,	O
by	O
adding	O
a	O
Time	B-Device
Stamp	I-Device
Counter	I-Device
to	O
support	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
's	O
RDTSC	B-Device
instruction	O
.	O
</s>
<s>
Support	O
for	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
CMOVcc	O
instructions	O
were	O
also	O
added	O
.	O
</s>
<s>
Similarly	O
to	O
AMD	O
with	O
their	O
K5	O
and	O
early	O
K6	B-Architecture
processors	O
,	O
Cyrix	O
used	O
a	O
PR	O
rating	O
(	O
Performance	O
Rating	O
)	O
to	O
relate	O
their	O
performance	O
to	O
the	O
Intel	B-General_Concept
P5	I-General_Concept
Pentium	B-General_Concept
(	O
pre-P55C	O
)	O
,	O
as	O
the	O
6x86	B-General_Concept
's	O
higher	O
per-clock	O
performance	O
relative	O
to	O
a	O
P5	B-General_Concept
Pentium	B-General_Concept
could	O
be	O
quantified	O
against	O
a	O
higher-clocked	O
Pentium	B-General_Concept
part	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
133MHz	O
6x86	B-General_Concept
will	O
match	O
or	O
outperform	O
a	O
P5	B-General_Concept
Pentium	B-General_Concept
at	O
166MHz	O
,	O
and	O
as	O
a	O
result	O
Cyrix	O
could	O
market	O
the	O
133MHz	O
chip	O
as	O
being	O
a	O
P5	B-General_Concept
Pentium	B-General_Concept
166	O
's	O
equal	O
.	O
</s>
<s>
However	O
,	O
the	O
PR	O
rating	O
was	O
not	O
an	O
entirely	O
truthful	O
representation	O
of	O
the	O
6x86	B-General_Concept
's	O
performance	O
.	O
</s>
<s>
While	O
the	O
6x86	B-General_Concept
's	O
integer	O
performance	O
was	O
significantly	O
higher	O
than	O
P5	B-General_Concept
Pentium	B-General_Concept
's	O
,	O
its	O
floating	O
point	O
performance	O
was	O
more	O
mediocre	O
—	O
between	O
2	O
and	O
4	O
times	O
the	O
performance	O
of	O
the	O
486	B-General_Concept
FPU	B-General_Concept
per	O
clock	O
cycle	O
(	O
depending	O
on	O
the	O
operation	O
and	O
precision	O
)	O
.	O
</s>
<s>
The	O
FPU	B-General_Concept
in	O
the	O
6x86	B-General_Concept
was	O
largely	O
the	O
same	O
circuitry	O
that	O
was	O
developed	O
for	O
Cyrix	O
's	O
earlier	O
high	O
performance	O
8087/80287/80387	O
-compatible	O
coprocessors	O
,	O
which	O
was	O
very	O
fast	O
for	O
its	O
time	O
—	O
the	O
Cyrix	O
FPU	B-General_Concept
was	O
much	O
faster	O
than	O
the	O
80387	O
,	O
and	O
even	O
the	O
80486	B-General_Concept
FPU	B-General_Concept
.	O
</s>
<s>
However	O
,	O
it	O
was	O
still	O
considerably	O
slower	O
than	O
the	O
new	O
and	O
completely	O
redesigned	O
P5	B-General_Concept
Pentium	B-General_Concept
and	O
P6	B-Device
Pentium	B-General_Concept
Pro-Pentium	O
III	O
FPUs	O
.	O
</s>
<s>
One	O
of	O
the	O
main	O
features	O
of	O
the	O
P5/P6	O
FPUs	O
is	O
that	O
they	O
supported	O
interleaving	O
of	O
FPU	B-General_Concept
and	O
integer	O
instructions	O
in	O
their	O
design	O
,	O
which	O
Cyrix	O
chips	O
did	O
not	O
integrate	O
.	O
</s>
<s>
Therefore	O
,	O
despite	O
being	O
very	O
fast	O
clock	O
by	O
clock	O
,	O
the	O
6x86	B-General_Concept
and	O
MII	O
were	O
forced	O
to	O
compete	O
at	O
the	O
low-end	O
of	O
the	O
market	O
as	O
AMD	B-Architecture
K6	I-Architecture
and	O
Intel	B-Device
P6	I-Device
Pentium	B-General_Concept
II	I-General_Concept
were	O
always	O
ahead	O
on	O
clock	O
speed	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
's	O
and	O
MII	O
's	O
old	O
generation	O
"	O
486	B-General_Concept
class	O
"	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
combined	O
with	O
an	O
integer	O
section	O
that	O
was	O
at	O
best	O
on-par	O
with	O
the	O
newer	O
P6	B-Device
and	O
K6	B-Architecture
chips	O
meant	O
that	O
Cyrix	O
could	O
no	O
longer	O
compete	O
in	O
performance	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
(	O
codename	O
M1	O
)	O
was	O
released	O
by	O
Cyrix	O
in	O
1996	O
.	O
</s>
<s>
The	O
first	O
generation	O
of	O
6x86	B-General_Concept
had	O
heat	O
problems	O
.	O
</s>
<s>
This	O
was	O
primarily	O
caused	O
by	O
their	O
higher	O
heat	O
output	O
than	O
other	O
x86	B-Operating_System
CPUs	O
of	O
the	O
day	O
and	O
,	O
as	O
such	O
,	O
computer	O
builders	O
sometimes	O
did	O
not	O
equip	O
them	O
with	O
adequate	O
cooling	O
.	O
</s>
<s>
The	O
CPUs	O
topped	O
out	O
at	O
around	O
25W	O
heat	O
output	O
(	O
like	O
the	O
AMD	B-Architecture
K6	I-Architecture
)	O
,	O
whereas	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
produced	O
around	O
15W	O
of	O
waste	O
heat	O
at	O
its	O
peak	O
.	O
</s>
<s>
The	O
M1R	O
was	O
a	O
switch	O
from	O
SGS-Thomson	O
3M	O
process	O
to	O
IBM	O
5M	O
process	O
,	O
making	O
the	O
6x86	B-General_Concept
chips	O
50%	O
smaller	O
.	O
</s>
<s>
The	O
6x86L	B-General_Concept
(	O
codename	O
M1L	O
)	O
was	O
later	O
released	O
by	O
Cyrix	O
to	O
address	O
heat	O
issues	O
;	O
the	O
L	O
standing	O
for	O
low-power	O
.	O
</s>
<s>
Just	O
like	O
the	O
Pentium	B-General_Concept
MMX	B-Architecture
,	O
the	O
6x86L	B-General_Concept
required	O
a	O
split	O
powerplane	O
voltage	O
regulator	O
with	O
separate	O
voltages	O
for	O
I/O	O
and	O
CPU	O
core	O
.	O
</s>
<s>
Another	O
release	O
of	O
the	O
6x86	B-General_Concept
,	O
the	O
6x86MX	B-General_Concept
,	O
added	O
MMX	B-Architecture
compatibility	O
along	O
with	O
the	O
EMMI	B-Device
instruction	O
set	O
,	O
improved	O
compatibility	O
with	O
the	O
Pentium	B-General_Concept
and	O
Pentium	B-Device
Pro	I-Device
by	O
adding	O
a	O
Time	B-Device
Stamp	I-Device
Counter	I-Device
and	O
CMOVcc	O
instructions	O
respectively	O
,	O
and	O
quadrupled	O
the	O
primary	O
cache	B-General_Concept
size	O
to	O
64KB	O
.	O
</s>
<s>
The	O
256-byte	O
instruction	O
line	O
cache	B-General_Concept
can	O
be	O
turned	O
into	O
a	O
scratchpad	B-General_Concept
cache	I-General_Concept
to	O
provide	O
support	O
for	O
multimedia	O
operations	O
.	O
</s>
<s>
Later	O
revisions	O
of	O
this	O
chip	O
were	O
renamed	O
MII	O
,	O
to	O
better	O
compete	O
with	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
processor	O
.	O
</s>
<s>
Unfortunately	O
,	O
6x86MX	B-General_Concept
/	O
MII	O
was	O
late	O
to	O
market	O
,	O
and	O
could	O
n't	O
scale	O
well	O
in	O
clock	O
speed	O
with	O
the	O
manufacturing	O
processes	O
used	O
at	O
the	O
time	O
.	O
</s>
<s>
(	O
millions	O
)	O
Socket(s )	O
PackageCore	O
VoltageTDP	O
(	O
W	O
)	O
Clock	O
speedBus	O
SpeedL1	O
CachePrice	O
(	O
USD	O
)	O
LaunchPR90+M10	O
,	O
653943.0Socket	O
7CPGA3.315.580	O
MHz40	O
MHz16	O
KB$84Nov	O
1995PR120+M10	O
,	O
653943.0Socket	O
7CPGA3.3	O
?	O
100	O
MHz50	O
MHz16	O
KB$450Oct	O
1995PR133+M1R0	O
,	O
652253.0Socket	O
7CPGA3.319.1110	O
MHz55	O
MHz16	O
KB$	O
3262-5-1996PR150	O
+M1R0	O
,	O
652253.0Socket	O
7CPGA3.3/3.5220.1120	O
MHz60	O
MHz16	O
KB$	O
4512-5-1996PR166	O
+M1R0	O
,	O
652253.0Socket	O
7CPGA3.3/3.5221.8133	O
MHz66	O
MHz16	O
KB$	O
6212-5-1996PR200	O
+M1R0	O
,	O
44	O
?	O
3.0Socket	O
7CPGA3.5217.13150	O
MHz75	O
MHz16	O
KB$	O
4996-6-1996L-PR120	O
+M1L0	O
,	O
351693.0Socket	O
7CPGA2.8/3.3	O
?	O
100	O
MHz50	O
MHz16	O
KB	O
?	O
Jan-1997L-PR133	O
+M1L0	O
,	O
351693.0Socket	O
7CPGA2.8/3.3	O
?	O
110	O
MHz55	O
MHz16	O
KB	O
?	O
Feb-1997L-PR150	O
+M1L0	O
,	O
351693.0Socket	O
7CPGA2.8/3.3	O
?	O
120	O
MHz60	O
MHz16	O
KB	O
?	O
Mar-1997L-PR166	O
+M1L0	O
,	O
351693.0Socket	O
7CPGA2.8/3.315.98133	O
MHz66	O
MHz16	O
KB	O
?	O
Apr-1997L-PR200	O
+M1L0	O
,	O
351693.0Socket	O
7CPGA2.8/3.317.13150	O
MHz75	O
MHz16	O
KB	O
?	O
Apr-1997PR166-MMXMII0	O
,	O
351976.0Socket	O
7CPGA2.9/3.3	O
?	O
</s>
<s>
?	O
MII-366-MMX	O
MII0	O
,	O
25886.0Super	O
7CPGA2.9/3.3	O
?	O
250	O
MHz100	O
MHz64	O
KB	O
?	O
Mar-1999MII-400-MMX	O
( *	O
m	O
)	O
MII0	O
,	O
18656.0Super	O
7CPGA2.2/3.3	O
?	O
285	O
MHz95	O
MHz64	O
KB	O
?	O
Jun-1999MII-433-MMX	O
( *	O
m	O
)	O
MII0	O
,	O
18656.0Super	O
7CPGA2.2/3.3	O
?	O
300	O
MHz100	O
MHz64	O
KB	O
?	O
Jun-1999	O
?	O
SGS-Thomson	O
6x86	B-General_Concept
ModelsST6x86P90+HSM10	O
,	O
653943.0Socket	O
7CPGA3.5217.3980	O
MHz40	O
MHz16	O
KB	O
?	O
</s>
<s>
?	O
IBM	O
6x86	B-General_Concept
Models2V2100GBM10	O
,	O
653943.0Socket	O
7CPGA3.3	O
?	O
80	O
MHz40	O
MHz16	O
KB	O
?	O
</s>
