<s>
In	O
computing	O
,	O
traditionally	O
cycle	B-General_Concept
stealing	I-General_Concept
is	O
a	O
method	O
of	O
accessing	O
computer	B-General_Concept
memory	I-General_Concept
(	O
RAM	B-Architecture
)	O
or	O
bus	B-General_Concept
without	O
interfering	O
with	O
the	O
CPU	O
.	O
</s>
<s>
It	O
is	O
similar	O
to	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
for	O
allowing	O
I/O	O
controllers	O
to	O
read	O
or	O
write	O
RAM	B-Architecture
without	O
CPU	O
intervention	O
.	O
</s>
<s>
Clever	O
exploitation	O
of	O
specific	O
CPU	O
or	O
bus	B-General_Concept
timings	O
can	O
permit	O
the	O
CPU	O
to	O
run	O
at	O
full	O
speed	O
without	O
any	O
delay	O
if	O
external	O
devices	O
access	O
memory	O
not	O
actively	O
participating	O
in	O
the	O
CPU	O
's	O
current	O
activity	O
and	O
complete	O
the	O
operations	O
before	O
any	O
possible	O
CPU	O
conflict	O
.	O
</s>
<s>
Cycle	B-General_Concept
stealing	I-General_Concept
was	O
common	O
in	O
older	O
platforms	O
,	O
first	O
on	O
supercomputers	B-Architecture
which	O
used	O
complex	O
systems	O
to	O
time	O
their	O
memory	O
access	O
,	O
and	O
later	O
on	O
early	O
microcomputers	B-Architecture
where	O
cycle	B-General_Concept
stealing	I-General_Concept
was	O
used	O
both	O
for	O
peripherals	O
as	O
well	O
as	O
display	O
drivers	O
.	O
</s>
<s>
It	O
is	O
more	O
difficult	O
to	O
implement	O
in	O
modern	O
platforms	O
because	O
there	O
are	O
often	O
several	O
layers	O
of	O
memory	O
running	O
at	O
different	O
speeds	O
,	O
and	O
access	O
is	O
often	O
mediated	O
by	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
In	O
the	O
cases	O
where	O
the	O
functionality	O
is	O
needed	O
,	O
modern	O
systems	O
often	O
use	O
dual-port	B-General_Concept
RAM	I-General_Concept
which	O
allows	O
access	O
by	O
two	O
systems	O
,	O
but	O
this	O
tends	O
to	O
be	O
expensive	O
.	O
</s>
<s>
In	O
this	O
case	O
the	O
device	O
is	O
stealing	B-General_Concept
cycles	I-General_Concept
from	O
the	O
CPU	O
,	O
so	O
it	O
is	O
the	O
opposite	O
sense	O
of	O
the	O
more	O
modern	O
usage	O
.	O
</s>
<s>
In	O
the	O
smaller	O
models	O
of	O
the	O
IBM	B-Application
System/360	I-Application
and	O
System/370	B-Device
,	O
the	O
control	B-General_Concept
store	I-General_Concept
contains	O
microcode	B-Device
for	O
both	O
the	O
processor	O
architecture	O
and	O
the	O
channel	O
architecture	O
.	O
</s>
<s>
When	O
a	O
channel	O
needs	O
service	O
,	O
the	O
hardware	O
steals	O
cycles	O
from	O
the	O
CPU	O
microcode	B-Device
in	O
order	O
to	O
run	O
the	O
channel	O
microcode	B-Device
.	O
</s>
<s>
Some	O
processors	O
were	O
designed	O
to	O
allow	O
cycle	B-General_Concept
stealing	I-General_Concept
,	O
or	O
at	O
least	O
supported	O
it	O
easily	O
.	O
</s>
<s>
This	O
was	O
the	O
case	O
for	O
the	O
Motorola	B-Device
6800	I-Device
and	O
MOS	B-General_Concept
6502	I-General_Concept
systems	O
due	O
to	O
a	O
design	O
feature	O
which	O
meant	O
the	O
CPU	O
only	O
accessed	O
memory	O
every	O
other	O
clock	O
cycle	O
.	O
</s>
<s>
Using	O
RAM	B-Architecture
that	O
was	O
running	O
twice	O
as	O
fast	O
as	O
the	O
CPU	O
clock	O
allowed	O
a	O
second	O
system	O
to	O
interleave	O
its	O
accesses	O
between	O
the	O
CPUs	O
by	O
timing	O
themselves	O
on	O
every	O
other	O
clock	O
cycle	O
.	O
</s>
<s>
This	O
was	O
widely	O
used	O
for	O
updating	O
the	O
display	O
using	O
main	O
memory	O
as	O
a	O
framebuffer	B-Algorithm
.	O
</s>
<s>
Common	O
RAM	B-Architecture
of	O
the	O
late	O
1970s	O
ran	O
at	O
2MHz	O
,	O
so	O
most	O
machines	O
had	O
a	O
CPU	O
running	O
around	O
1MHz	O
.	O
</s>
<s>
The	O
BBC	B-Device
Micro	I-Device
secured	O
a	O
supply	O
of	O
4MHz	O
RAM	B-Architecture
which	O
allowed	O
its	O
CPU	O
to	O
run	O
at	O
2MHz	O
.	O
</s>
<s>
One	O
example	O
is	O
the	O
Zilog	B-General_Concept
Z80	I-General_Concept
,	O
whose	O
M1	O
line	O
indicates	O
that	O
the	O
processor	O
is	O
reading	O
instructions	O
;	O
if	O
those	O
instructions	O
are	O
in	O
a	O
different	O
bank	O
,	O
or	O
more	O
commonly	O
ROM	B-Device
,	O
the	O
I/O	O
systems	O
can	O
access	O
RAM	B-Architecture
without	O
interfering	O
with	O
the	O
processor	O
.	O
</s>
<s>
Cycle	B-General_Concept
stealing	I-General_Concept
is	O
difficult	O
to	O
achieve	O
in	O
modern	O
systems	O
due	O
to	O
many	O
factors	O
such	O
as	O
pipelining	B-General_Concept
,	O
where	O
pre-fetch	O
and	O
concurrent	O
elements	O
are	O
constantly	O
accessing	O
memory	O
,	O
leaving	O
few	O
predictable	O
idle	O
times	O
to	O
sneak	O
in	O
memory	O
access	O
.	O
</s>
<s>
DMA	O
is	O
the	O
only	O
formal	O
and	O
predictable	O
method	O
for	O
external	O
devices	O
to	O
access	O
RAM	B-Architecture
.	O
</s>
<s>
This	O
term	O
is	O
less	O
common	O
in	O
modern	O
computer	O
architecture	O
(	O
above	O
66-100MHz	O
)	O
,	O
where	O
the	O
various	O
external	O
buses	O
and	O
controllers	O
generally	O
run	O
at	O
different	O
rates	O
,	O
and	O
CPU	O
internal	O
operations	O
are	O
no	O
longer	O
closely	O
coupled	O
to	O
I/O	B-General_Concept
bus	I-General_Concept
operations	O
.	O
</s>
<s>
Unexpected	O
cycle	B-General_Concept
stealing	I-General_Concept
by	O
the	O
rendezvous	O
radar	O
during	O
descent	O
nearly	O
caused	O
the	O
Apollo	O
11	O
landing	O
to	O
be	O
aborted	O
,	O
but	O
the	O
design	O
of	O
the	O
Guidance	O
Computer	O
allowed	O
the	O
landing	O
to	O
continue	O
by	O
dropping	O
low-priority	O
tasks	O
.	O
</s>
<s>
The	O
IBM	B-Device
1130	I-Device
's	O
"	O
cycle	O
steal	O
"	O
is	O
really	O
DMA	O
because	O
the	O
CPU	O
clock	O
is	O
stopped	O
during	O
memory	O
access	O
.	O
</s>
<s>
Several	O
I/O	O
controllers	O
access	O
RAM	B-Architecture
this	O
way	O
.	O
</s>
<s>
Most	O
controllers	O
deliberately	O
pace	O
RAM	B-Architecture
access	O
to	O
minimize	O
impact	O
on	O
the	O
system	O
's	O
ability	O
to	O
run	O
instructions	O
,	O
but	O
others	O
,	O
such	O
as	O
graphic	O
video	O
adapters	O
,	O
operate	O
at	O
higher	O
speed	O
and	O
may	O
slow	O
down	O
the	O
system	O
.	O
</s>
<s>
Cycle	B-General_Concept
stealing	I-General_Concept
has	O
been	O
the	O
cause	O
of	O
major	O
performance	O
degradation	O
on	O
machine	O
such	O
as	O
the	O
Sinclair	B-Device
QL	I-Device
,	O
where	O
,	O
for	O
economy	O
reasons	O
,	O
the	O
video	O
RAM	B-Architecture
was	O
not	O
dual	B-General_Concept
access	I-General_Concept
.	O
</s>
<s>
Consequently	O
,	O
the	O
M68008	B-Device
CPU	O
was	O
denied	O
access	O
to	O
the	O
memory	O
bus	B-General_Concept
when	O
the	O
ZX8301	O
"	O
master	O
controller	O
"	O
was	O
accessing	O
memory	O
,	O
and	O
the	O
machine	O
performed	O
poorly	O
when	O
compared	O
with	O
machines	O
using	O
similar	O
processors	O
at	O
similar	O
speeds	O
.	O
</s>
