<s>
Cray	B-Device
XMT	I-Device
(	O
Cray	O
eXtreme	O
MultiThreading	B-General_Concept
,	O
codenamed	O
Eldorado	O
)	O
is	O
a	O
scalable	B-Architecture
multithreaded	B-Operating_System
shared	B-Operating_System
memory	I-Operating_System
supercomputer	B-Architecture
architecture	O
by	O
Cray	O
,	O
based	O
on	O
the	O
third	O
generation	O
of	O
the	O
Tera	B-Device
MTA	I-Device
architecture	O
,	O
targeted	O
at	O
large	O
graph	O
problems	O
(	O
e.g.	O
</s>
<s>
semantic	O
databases	O
,	O
big	B-Application
data	I-Application
,	O
pattern	B-Language
matching	I-Language
)	O
.	O
</s>
<s>
Presented	O
in	O
2005	O
,	O
it	O
supersedes	O
the	O
earlier	O
unsuccessful	O
Cray	B-Device
MTA-2	I-Device
.	O
</s>
<s>
It	O
uses	O
the	O
Threadstorm3	O
CPUs	O
inside	O
Cray	B-Device
XT3	I-Device
blades	O
.	O
</s>
<s>
Designed	O
to	O
make	O
use	O
of	O
commodity	O
parts	O
and	O
existing	O
subsystems	O
for	O
other	O
commercial	O
systems	O
,	O
it	O
alleviated	O
the	O
shortcomings	O
of	O
Cray	B-Device
MTA-2	I-Device
'	O
s	O
high	O
cost	O
of	O
fully	O
custom	O
manufacture	O
and	O
support	O
.	O
</s>
<s>
It	O
brought	O
various	O
substantial	O
improvements	O
over	O
Cray	B-Device
MTA-2	I-Device
,	O
most	O
notably	O
nearly	O
tripling	O
the	O
peak	O
performance	O
,	O
and	O
vastly	O
increased	O
maximum	O
CPU	O
count	O
to	O
8,192	O
and	O
maximum	O
memory	O
to	O
128	O
TB	O
,	O
with	O
a	O
data	O
TLB	B-Architecture
of	O
maximal	O
512	O
TB	O
.	O
</s>
<s>
Cray	B-Device
XMT	I-Device
uses	O
a	O
scrambled	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
model	O
on	O
DDR1	O
ECC	B-Error_Name
modules	O
to	O
implicitly	O
load-balance	O
memory	O
access	O
across	O
the	O
whole	O
shared	O
global	O
address	O
space	O
of	O
the	O
system	O
.	O
</s>
<s>
There	O
are	O
no	O
hardware	O
interrupts	O
and	O
hardware	B-General_Concept
threads	I-General_Concept
are	O
allocated	O
by	O
an	O
instruction	O
,	O
not	O
the	O
OS	O
.	O
</s>
<s>
Front-end	O
(	O
login	O
,	O
I/O	O
,	O
and	O
other	O
service	O
nodes	O
,	O
utilizing	O
AMD	B-General_Concept
Opteron	I-General_Concept
processors	O
and	O
running	O
SLES	O
Linux	B-Operating_System
)	O
and	O
back-end	O
(	O
compute	O
nodes	O
,	O
utilizing	O
Threadstorm3	O
processors	O
and	O
running	O
MTK	O
,	O
a	O
simple	O
BSD	O
Unix-based	O
microkernel	B-Operating_System
)	O
communicate	O
through	O
the	O
LUC	O
(	O
Lightweight	O
User	O
Communication	O
)	O
interface	O
,	O
a	O
RPC-style	O
bidirectional	O
client/server	O
interface	O
.	O
</s>
<s>
Threadstorm3	O
(	O
referred	O
to	O
as	O
"	O
MT	O
processor	O
"	O
and	O
Threadstorm	O
before	O
XMT2	O
)	O
is	O
a	O
64-bit	O
single-core	O
VLIW	B-General_Concept
barrel	B-Operating_System
processor	I-Operating_System
(	O
compatible	O
with	O
940-pin	O
Socket	O
940	O
used	O
by	O
AMD	B-General_Concept
Opteron	I-General_Concept
processors	O
)	O
with	O
128	O
hardware	O
streams	O
,	O
onto	O
each	O
a	O
software	O
thread	O
can	O
be	O
mapped	O
(	O
effectively	O
creating	O
128	O
hardware	B-General_Concept
threads	I-General_Concept
per	O
CPU	O
)	O
,	O
running	O
at	O
500MHz	O
and	O
using	O
the	O
MTA	O
instruction	O
set	O
or	O
a	O
superset	O
of	O
it	O
.	O
</s>
<s>
Each	O
Threadstorm3	O
has	O
128	O
separate	O
register	O
sets	O
and	O
program	O
counters	O
(	O
one	O
per	O
each	O
stream	O
)	O
,	O
which	O
are	O
fairly	O
fully	O
context-switched	B-Operating_System
at	O
each	O
cycle	O
.	O
</s>
<s>
It	O
has	O
3	O
functional	O
units	O
(	O
memory	O
,	O
fused	B-Algorithm
multiply-add	I-Algorithm
and	O
control	O
)	O
,	O
which	O
receive	O
operations	O
from	O
the	O
same	O
MTA	O
instruction	O
and	O
operate	O
within	O
the	O
same	O
cycle	O
.	O
</s>
<s>
Due	O
to	O
the	O
MTA	O
's	O
pipeline	B-General_Concept
length	O
of	O
21	O
,	O
each	O
stream	O
is	O
selected	O
to	O
execute	O
instructions	O
again	O
no	O
prior	O
than	O
21	O
cycles	O
later	O
.	O
</s>
<s>
The	O
TDP	B-General_Concept
of	O
the	O
processor	O
package	O
is	O
30	O
W	O
.	O
</s>
<s>
Due	O
to	O
their	O
thread-level	O
context	B-Operating_System
switch	I-Operating_System
at	O
each	O
cycle	O
,	O
performance	O
of	O
Threadstorm	O
CPUs	O
is	O
not	O
constrained	O
by	O
memory	O
access	O
time	O
.	O
</s>
<s>
Cray	O
XMT2	O
(	O
also	O
"	O
next-generation	O
XMT	O
"	O
or	O
simply	O
XMT	O
)	O
is	O
a	O
scalable	B-Architecture
multithreaded	B-Operating_System
shared	B-Operating_System
memory	I-Operating_System
supercomputer	B-Architecture
by	O
Cray	O
,	O
based	O
on	O
the	O
fourth	O
generation	O
of	O
the	O
Tera	B-Device
MTA	I-Device
architecture	O
.	O
</s>
<s>
Presented	O
in	O
2011	O
,	O
it	O
supersedes	O
Cray	B-Device
XMT	I-Device
,	O
which	O
had	O
issues	O
with	O
memory	O
hotspots	O
.	O
</s>
<s>
It	O
uses	O
Threadstorm4	O
CPUs	O
inside	O
Cray	B-Device
XT5	I-Device
blades	O
and	O
increases	O
memory	O
capacity	O
eightfold	O
to	O
512	O
TB	O
and	O
memory	O
bandwidth	O
trifold	O
(	O
300MHz	O
instead	O
200MHz	O
)	O
compared	O
to	O
XMT	O
by	O
using	O
twice	O
the	O
memory	O
modules	O
per	O
node	O
and	O
DDR2	O
.	O
</s>
<s>
It	O
introduces	O
the	O
Node	O
Pair	O
Link	O
inter-Threadstorm	O
connect	O
,	O
as	O
well	O
as	O
memory-only	O
nodes	O
,	O
with	O
Threadstorm4	O
packages	O
having	O
their	O
CPU	O
and	O
HyperTransport	B-Device
1.x	I-Device
components	O
disabled	O
.	O
</s>
<s>
The	O
underlying	O
scrambled	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
model	O
has	O
been	O
inherited	O
from	O
XMT	O
.	O
</s>
<s>
Threadstorm4	O
(	O
also	O
"	O
Threadstorm	O
IV	O
"	O
and	O
"	O
Threadstorm	O
4.0	O
"	O
)	O
is	O
a	O
64-bit	O
single-core	O
VLIW	B-General_Concept
barrel	B-Operating_System
processor	I-Operating_System
(	O
compatible	O
with	O
1207-pin	O
Socket	O
F	O
used	O
by	O
AMD	B-General_Concept
Opteron	I-General_Concept
processors	O
)	O
with	O
128	O
hardware	O
streams	O
,	O
very	O
similar	O
to	O
its	O
predecessor	O
,	O
Threadstorm3	O
.	O
</s>
<s>
Cray	O
intentionally	O
decided	O
against	O
a	O
DDR3	O
controller	O
,	O
citing	O
the	O
reusing	O
of	O
existing	O
Cray	B-Device
XT5	I-Device
infrastructure	O
and	O
a	O
shorter	O
burst	O
length	O
than	O
DDR3	O
.	O
</s>
<s>
Most	O
of	O
Threadstorm3	O
's	O
features	O
would	O
be	O
retained	O
,	O
including	O
the	O
multiplexing	O
of	O
many	O
hardware	O
streams	O
onto	O
an	O
execution	O
pipeline	B-General_Concept
and	O
the	O
implementation	O
of	O
additional	O
state	O
bits	O
for	O
every	O
64-bit	O
memory	O
word	O
.	O
</s>
<s>
Development	O
on	O
Threadstorm4	O
,	O
as	O
well	O
as	O
the	O
whole	O
MTA	O
architecture	O
,	O
ended	O
silently	O
after	O
XMT2	O
,	O
probably	O
due	O
to	O
competition	O
from	O
commodity	O
processors	O
such	O
as	O
Intel	O
's	O
Xeon	B-Device
and	O
possibly	O
Xeon	B-General_Concept
Phi	I-General_Concept
,	O
even	O
though	O
Cray	O
never	O
officially	O
discontinued	O
neither	O
XMT	O
nor	O
XMT2	O
.	O
</s>
