<s>
The	O
Cray	B-Device
XD1	I-Device
was	O
an	O
entry-level	O
supercomputer	B-Architecture
range	O
,	O
made	O
by	O
Cray	O
Inc	O
.	O
</s>
<s>
The	O
XD1	O
uses	O
AMD	B-General_Concept
Opteron	I-General_Concept
64-bit	B-Device
CPUs	I-Device
,	O
and	O
utilizes	O
the	O
Direct	O
Connect	O
Architecture	O
over	O
HyperTransport	B-Device
to	O
remove	O
the	O
bottleneck	B-Architecture
at	O
the	O
PCI	B-Protocol
and	O
contention	B-General_Concept
at	O
the	O
memory	O
.	O
</s>
<s>
The	O
MPI	B-Application
latency	O
is	O
¼	O
that	O
of	O
Infiniband	B-Architecture
,	O
and	O
1/30	O
that	O
of	O
Gigabit	O
Ethernet	O
.	O
</s>
<s>
Announced	O
on	O
4	O
October	O
2004	O
,	O
the	O
Cray	B-Device
XD1	I-Device
range	O
incorporate	O
Xilinx	O
Virtex-II	O
Pro	O
FPGAs	B-Architecture
for	O
application	O
acceleration	O
.	O
</s>
<s>
With	O
12	O
CPUs	O
in	O
a	O
chassis	O
,	O
and	O
up	O
to	O
12	O
chassis	O
installable	O
in	O
a	O
rack	O
,	O
XD1	O
systems	O
may	O
hold	O
several	O
144-CPU	O
multiples	O
in	O
multirack	O
configurations	O
.	O
</s>
<s>
The	O
operating	B-General_Concept
system	I-General_Concept
used	O
on	O
the	O
XD1	O
is	O
a	O
customized	O
version	O
of	O
Linux	B-Application
,	O
and	O
the	O
machine	O
's	O
load	B-Application
balancing	I-Application
/	O
resource	O
management	O
system	O
is	O
an	O
enhanced	O
version	O
of	O
Sun	O
Microsystems	O
 '	O
Sun	B-Operating_System
Grid	I-Operating_System
Engine	I-Operating_System
.	O
</s>
