<s>
The	O
Cray	B-Device
X2	I-Device
is	O
a	O
vector	B-Operating_System
processing	I-Operating_System
node	O
for	O
the	O
Cray	B-Device
XT5h	I-Device
supercomputer	B-Architecture
,	O
developed	O
and	O
sold	O
by	O
Cray	O
Inc	O
.	O
and	O
launched	O
in	O
2007	O
.	O
</s>
<s>
The	O
X2	O
,	O
developed	O
under	O
the	O
code	O
name	O
Black	O
Widow	O
,	O
was	O
originally	O
expected	O
to	O
be	O
a	O
standalone	O
supercomputer	B-Architecture
system	O
,	O
superseding	O
the	O
Cray	B-Device
X1	I-Device
parallel	O
vector	O
supercomputer	B-Architecture
.	O
</s>
<s>
However	O
,	O
the	O
X2	O
was	O
eventually	O
launched	O
as	O
one	O
of	O
the	O
four	O
processor	O
"	O
blade	B-Architecture
"	O
options	O
for	O
the	O
XT5h	O
system	O
.	O
</s>
<s>
An	O
X2	O
blade	B-Architecture
comprises	O
two	O
nodes	O
,	O
each	O
with	O
four	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
vector	B-Operating_System
processors	I-Operating_System
and	O
32	O
or	O
64	O
GB	O
of	O
shared	O
memory	O
.	O
</s>
<s>
X2	O
processors	O
are	O
connected	O
using	O
a	O
radix-64	O
"	O
fat-tree	B-Protocol
"	O
interconnect	O
implemented	O
by	O
the	O
YARC	O
router	O
ASIC	O
.	O
</s>
<s>
The	O
X2	O
processor	O
nodes	O
integrate	O
with	O
the	O
Cray	B-Device
XT5h	I-Device
's	O
UNICOS/lc	O
OS	O
,	O
user	O
environment	O
,	O
and	O
storage	O
subsystem	O
,	O
as	O
part	O
of	O
the	O
Rainier	O
project	O
.	O
</s>
