<s>
The	O
Cray	B-Device
X1	I-Device
is	O
a	O
non-uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
,	O
vector	B-Operating_System
processor	I-Operating_System
supercomputer	B-Architecture
manufactured	O
and	O
sold	O
by	O
Cray	O
Inc	O
.	O
since	O
2003	O
.	O
</s>
<s>
The	O
X1	O
is	O
often	O
described	O
as	O
the	O
unification	O
of	O
the	O
Cray	B-Device
T90	I-Device
,	O
Cray	B-Device
SV1	I-Device
,	O
and	O
Cray	B-Device
T3E	I-Device
architectures	O
into	O
a	O
single	O
machine	O
.	O
</s>
<s>
The	O
X1	O
shares	O
the	O
multistreaming	O
processors	O
,	O
vector	O
caches	O
,	O
and	O
CMOS	B-Device
design	O
of	O
the	O
SV1	O
,	O
the	O
highly	O
scalable	O
distributed	O
memory	B-General_Concept
design	O
of	O
the	O
T3E	B-Device
,	O
and	O
the	O
high	O
memory	B-General_Concept
bandwidth	O
and	O
liquid	O
cooling	O
of	O
the	O
T90	O
.	O
</s>
<s>
Liquid-cooled	O
systems	O
scale	O
to	O
a	O
theoretical	O
maximum	O
of	O
4096	O
processors	O
,	O
comprising	O
1024	O
shared-memory	O
nodes	B-Protocol
connected	O
in	O
a	O
two-dimensional	O
torus	O
network	O
,	O
in	O
32	O
frames	O
.	O
</s>
<s>
The	O
X1	O
can	O
be	O
programmed	O
either	O
with	O
widely	O
used	O
message	O
passing	O
software	O
like	O
MPI	B-Application
and	O
PVM	B-Operating_System
,	O
or	O
with	O
shared-memory	O
languages	O
like	O
Unified	B-Operating_System
Parallel	I-Operating_System
C	I-Operating_System
programming	O
language	O
or	O
Co-array	B-Language
Fortran	I-Language
.	O
</s>
<s>
The	O
X1	O
runs	O
an	O
operating	B-General_Concept
system	I-General_Concept
called	O
UNICOS/mp	B-Operating_System
which	O
shares	O
more	O
with	O
the	O
SGI	B-Operating_System
IRIX	I-Operating_System
operating	B-General_Concept
system	I-General_Concept
than	O
it	O
does	O
with	O
the	O
UNICOS	B-Operating_System
found	O
on	O
prior	O
generation	O
Cray	O
machines	O
.	O
</s>
<s>
In	O
2005	O
,	O
Cray	O
released	O
the	O
X1E	O
upgrade	O
,	O
which	O
uses	O
dual-core	O
processors	O
,	O
allowing	O
two	O
quad-processor	O
nodes	B-Protocol
to	O
fit	O
on	O
a	O
node	O
board	O
.	O
</s>
<s>
This	O
upgrade	O
almost	O
triples	O
the	O
peak	O
performance	O
per	O
board	O
,	O
but	O
reduces	O
the	O
per-processor	O
memory	B-General_Concept
and	O
interconnect	O
bandwidth	O
.	O
</s>
