<s>
The	O
Cray	B-Device
MTA	I-Device
,	O
formerly	O
known	O
as	O
the	O
Tera	B-Device
MTA	I-Device
,	O
is	O
a	O
supercomputer	B-Architecture
architecture	O
based	O
on	O
thousands	O
of	O
independent	O
threads	O
,	O
fine-grain	O
communication	O
and	O
synchronization	O
between	O
threads	O
,	O
and	O
latency	O
tolerance	O
for	O
irregular	O
computations	O
.	O
</s>
<s>
Each	O
MTA	O
processor	O
(	O
CPU	B-Device
)	O
has	O
a	O
high-performance	O
ALU	B-General_Concept
with	O
many	O
independent	O
register	O
sets	O
,	O
each	O
running	O
an	O
independent	O
thread	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
Cray	B-Device
MTA-2	I-Device
uses	O
128	O
register	O
sets	O
and	O
thus	O
128	O
threads	O
per	O
CPU/ALU	O
.	O
</s>
<s>
All	O
MTAs	O
to	O
date	O
use	O
a	O
barrel	B-Operating_System
processor	I-Operating_System
arrangement	O
,	O
with	O
a	O
thread	O
switch	O
on	O
every	O
cycle	O
,	O
with	O
blocked	O
(	O
stalled	O
)	O
threads	O
skipped	O
to	O
avoid	O
wasting	O
ALU	B-General_Concept
cycles	O
.	O
</s>
<s>
A	O
parallelizing	O
FORTRAN	B-Application
compiler	B-Language
can	O
produce	O
high	O
performance	O
for	O
some	O
codes	O
with	O
little	O
manual	O
intervention	O
.	O
</s>
<s>
A	O
further	O
goal	O
is	O
that	O
programs	O
for	O
the	O
MTA	O
will	O
be	O
scalable	B-Architecture
that	O
is	O
,	O
when	O
run	O
on	O
an	O
MTA	O
with	O
twice	O
as	O
many	O
CPUs	B-Device
,	O
the	O
same	O
program	O
will	O
have	O
nearly	O
twice	O
the	O
performance	O
.	O
</s>
<s>
Both	O
of	O
these	O
are	O
challenges	O
for	O
many	O
other	O
high-performance	B-Architecture
computer	I-Architecture
systems	O
.	O
</s>
<s>
Typically	O
,	O
supercomputers	B-Architecture
are	O
dedicated	O
to	O
a	O
task	O
at	O
a	O
time	O
.	O
</s>
<s>
MTA-1	O
The	O
MTA-1	O
uses	O
a	O
GaAs	O
processor	O
and	O
was	O
installed	O
at	O
the	O
San	O
Diego	O
Supercomputer	B-Architecture
Center	O
.	O
</s>
<s>
MTA-2	B-Device
The	O
MTA-2	B-Device
uses	O
a	O
CMOS	B-Device
processor	O
and	O
was	O
installed	O
at	O
the	O
Naval	O
Research	O
Laboratory	O
.	O
</s>
<s>
MTA-3	O
The	O
MTA-3	O
uses	O
the	O
same	O
CPU	B-Device
as	O
the	O
MTA-2	B-Device
but	O
a	O
dramatically	O
cheaper	O
and	O
slower	O
network	O
interface	O
.	O
</s>
<s>
About	O
six	O
Cray	B-Device
XMT	I-Device
systems	O
have	O
been	O
sold	O
(	O
2009	O
)	O
using	O
the	O
MTA-3	O
.	O
</s>
<s>
Only	O
a	O
few	O
systems	O
have	O
been	O
deployed	O
,	O
and	O
only	O
MTA-2	B-Device
benchmarks	O
have	O
been	O
reported	O
widely	O
,	O
making	O
performance	O
comparisons	O
difficult	O
.	O
</s>
<s>
Across	O
several	O
benchmarks	O
,	O
a	O
2-CPU	O
MTA-2	B-Device
shows	O
performance	O
similar	O
to	O
a	O
2-processor	O
Cray	O
T90	O
.	O
</s>
<s>
For	O
the	O
specific	O
application	O
of	O
ray	O
tracing	O
,	O
a	O
4-CPU	O
MTA-2	B-Device
was	O
about	O
5x	O
faster	O
than	O
a	O
4-CPU	O
Cray	O
T3E	O
,	O
and	O
in	O
scaling	B-Architecture
from	O
1	O
CPU	B-Device
to	O
4	O
CPUs	B-Device
the	O
Tera	O
performance	O
improved	O
by	O
3.8x	O
,	O
while	O
the	O
T3E	O
going	O
from	O
1	O
to	O
4	O
CPUs	B-Device
improved	O
by	O
only	O
3.0x	O
.	O
</s>
<s>
In	O
existing	O
MTA	O
implementations	O
,	O
single-thread	O
performance	O
is	O
21	O
cycles	O
per	O
instruction	O
,	O
so	O
performance	O
suffers	O
when	O
there	O
are	O
fewer	O
than	O
21	O
threads	O
per	O
CPU	B-Device
.	O
</s>
<s>
This	O
reduces	O
CPU	B-Device
complexity	O
and	O
avoids	O
cache	O
coherency	O
problems	O
.	O
</s>
<s>
Second	O
,	O
memory	O
references	O
take	O
150-170	O
cycles	O
,	O
a	O
much	O
higher	O
latency	O
than	O
even	O
a	O
slow	O
cache	O
,	O
thus	O
increasing	O
the	O
number	O
of	O
runable	O
threads	O
required	O
to	O
keep	O
the	O
ALU	B-General_Concept
busy	O
.	O
</s>
<s>
The	O
MTA-4	O
will	O
have	O
a	O
non-coherent	O
cache	O
,	O
which	O
can	O
be	O
used	O
for	O
read-only	O
and	O
unshared	O
data	O
(	O
such	O
as	O
non-shared	O
stack	O
frames	O
)	O
,	O
but	O
which	O
requires	O
software	O
coherency	O
e.g.	O
,	O
if	O
a	O
thread	O
is	O
migrated	O
between	O
CPUs	B-Device
.	O
</s>
