<s>
The	O
Cray-3/SSS	B-Device
(	O
Super	B-Device
Scalable	I-Device
System	I-Device
)	O
was	O
a	O
pioneering	O
massively	B-Operating_System
parallel	I-Operating_System
supercomputer	B-Architecture
project	O
that	O
bonded	O
a	O
two-processor	O
Cray-3	B-Device
to	O
a	O
new	O
SIMD	B-Device
processing	O
unit	O
based	O
entirely	O
in	O
the	O
computer	O
's	O
main	O
memory	O
.	O
</s>
<s>
It	O
was	O
later	O
considered	O
as	O
an	O
add-on	O
for	O
the	O
Cray	B-Device
T90	I-Device
series	O
in	O
the	O
form	O
of	O
the	O
T94/SSS	O
,	O
but	O
there	O
is	O
no	O
evidence	O
this	O
was	O
ever	O
built	O
.	O
</s>
<s>
The	O
SSS	O
project	O
started	O
after	O
a	O
Supercomputing	B-Architecture
Research	O
Center	O
(	O
SRC	O
)	O
engineer	O
,	O
Ken	O
Iobst	O
,	O
noticed	O
a	O
novel	O
way	O
to	O
implement	O
a	O
parallel	O
computer	O
.	O
</s>
<s>
Previous	O
massively	O
SIMD	B-Device
designs	O
,	O
like	O
the	B-Device
Connection	I-Device
Machines	I-Device
,	O
consisted	O
of	O
a	O
large	O
number	O
of	O
individual	O
processing	O
elements	O
consisting	O
of	O
a	O
simple	O
processor	O
and	O
some	O
local	O
memory	O
.	O
</s>
<s>
Iobst	O
's	O
idea	O
was	O
to	O
use	O
the	O
super-fast	O
scatter/gather	O
hardware	O
from	O
the	O
Cray-3	B-Device
to	O
move	O
the	O
data	O
around	O
instead	O
of	O
using	O
a	O
separate	O
network	O
.	O
</s>
<s>
Better	O
yet	O
,	O
the	O
machine	O
would	O
still	O
include	O
a	O
complete	O
Cray-3	B-Device
CPU	B-General_Concept
,	O
allowing	O
the	O
machine	O
as	O
a	O
whole	O
to	O
use	O
either	O
SIMD	B-Device
or	O
vector	O
instructions	O
depending	O
on	O
the	O
particulars	O
of	O
the	O
problem	O
.	O
</s>
<s>
Since	O
the	O
Cray-3	B-Device
already	O
had	O
a	O
vector	B-Operating_System
processor	I-Operating_System
for	O
heavy	O
computing	O
,	O
the	O
SIMD	B-Device
processors	O
themselves	O
could	O
be	O
considerably	O
simpler	O
,	O
handling	O
only	O
the	O
most	O
basic	O
instructions	O
.	O
</s>
<s>
This	O
is	O
where	O
the	O
SSS	O
concept	O
was	O
truly	O
unique	O
;	O
since	O
the	O
problem	O
with	O
most	O
SIMD	B-Device
machines	O
was	O
moving	O
data	O
around	O
,	O
Iobst	O
suggested	O
that	O
the	O
processors	O
be	O
built	O
into	O
the	O
SRAM	B-Architecture
chips	O
themselves	O
.	O
</s>
<s>
Memory	O
is	O
normally	O
organized	O
within	O
the	O
RAM	O
chips	O
in	O
a	O
row/column	O
format	O
,	O
with	O
a	O
controller	O
on	O
the	O
chip	O
reading	O
requested	O
data	O
from	O
the	O
chip	O
in	O
parallel	O
across	O
the	O
rows	O
,	O
then	O
assembling	O
the	O
results	O
into	O
32	O
-	O
or	O
64-bit	B-Device
words	O
for	O
processing	O
by	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Add	O
to	O
this	O
the	O
speed	O
of	O
the	O
"	O
network	O
"	O
implemented	O
by	O
the	O
scatter/gather	O
hardware	O
,	O
and	O
the	O
system	O
could	O
be	O
scaled	O
to	O
sizes	O
considerably	O
greater	O
than	O
existing	O
SIMD	B-Device
systems	O
.	O
</s>
