<s>
Core	B-Device
Multiplexing	I-Device
Technology	I-Device
is	O
a	O
term	O
that	O
appeared	O
in	O
some	O
BIOSes	O
.	O
</s>
<s>
A	O
subset	O
of	O
traditional	O
applications	O
are	O
often	O
difficult	O
to	O
parallelize	O
and	O
make	O
use	O
of	O
additional	O
CPU	B-Device
hardware	O
available	O
on	O
the	O
platform	O
,	O
restraining	O
applications	O
to	O
use	O
only	O
one	O
CPU	B-Device
.	O
</s>
<s>
Core	B-Device
Multiplexing	I-Device
Technology	I-Device
would	O
allow	O
for	O
a	O
process	O
to	O
be	O
split	O
into	O
multiple	O
threads	O
at	O
compilation	O
time	O
and	O
execution	O
time	O
by	O
the	O
introduction	O
of	O
speculative	O
multithreading	O
.	O
</s>
<s>
Much	O
in	O
the	O
same	O
way	O
a	O
branch	B-General_Concept
predictor	I-General_Concept
allows	O
for	O
a	O
processor	O
to	O
speculate	O
on	O
the	O
outcome	O
of	O
a	O
branch	O
operation	O
without	O
actually	O
performing	O
the	O
operation	O
,	O
speculative	O
multithreading	O
allows	O
for	O
the	O
processor	O
to	O
speculate	O
deeper	O
,	O
executing	O
entire	O
branches	O
of	O
code	O
on	O
an	O
additional	O
core	O
.	O
</s>
<s>
Most	O
of	O
the	O
implementation	O
is	O
done	O
in	O
software	O
,	O
with	O
the	O
compiler	O
rearranging	O
code	O
to	O
take	O
better	O
use	O
of	O
a	O
multithreaded	O
platform	O
,	O
which	O
allows	O
Simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
and	O
Multicore	B-Architecture
systems	O
(	O
or	O
a	O
combination	O
of	O
the	O
two	O
)	O
to	O
take	O
advantage	O
of	O
the	O
technology	O
.	O
</s>
<s>
Core	B-Device
Multiplexing	I-Device
Technology	I-Device
is	O
thought	O
to	O
leverage	O
Intel	O
's	O
Advanced	O
Smart	O
Cache	O
technology	O
of	O
the	O
upcoming	O
Core	B-Device
2	I-Device
chips	O
,	O
which	O
allows	O
two	O
cores	O
to	O
share	O
a	O
single	O
L2	O
cache	O
,	O
and	O
actively	O
resize	O
the	O
cache	O
between	O
the	O
two	O
processors	O
if	O
one	O
is	O
idle	O
,	O
by	O
allowing	O
the	O
two	O
cores	O
to	O
share	O
data	O
to	O
manage	O
inter-thread	O
dependent	O
data	O
.	O
</s>
