<s>
CoreConnect	B-Architecture
is	O
a	O
microprocessor	B-Architecture
bus-architecture	O
from	O
IBM	O
for	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
designs	O
.	O
</s>
<s>
It	O
was	O
designed	O
to	O
ease	O
the	O
integration	O
and	O
reuse	O
of	O
processor	O
,	O
system	O
,	O
and	O
peripheral	O
cores	B-Architecture
within	O
standard	O
and	O
custom	O
SoC	O
designs	O
.	O
</s>
<s>
Elements	O
of	O
this	O
architecture	O
include	O
the	O
processor	B-Architecture
local	I-Architecture
bus	I-Architecture
(	O
PLB	O
)	O
,	O
the	O
on-chip	O
peripheral	O
bus	B-General_Concept
(	O
OPB	O
)	O
,	O
a	O
bus	B-General_Concept
bridge	O
,	O
and	O
a	O
device	B-General_Concept
control	I-General_Concept
register	I-General_Concept
(	O
DCR	O
)	O
bus	B-General_Concept
.	O
</s>
<s>
Slower	O
peripheral	O
cores	B-Architecture
connect	O
to	O
the	O
OPB	O
,	O
which	O
reduces	O
traffic	O
on	O
the	O
PLB	O
.	O
</s>
<s>
CoreConnect	B-Architecture
has	O
bridging	O
capabilities	O
to	O
the	O
competing	O
AMBA	B-Architecture
bus	B-General_Concept
architecture	O
,	O
allowing	O
reuse	O
of	O
existing	O
SoC-components	O
.	O
</s>
<s>
IBM	O
makes	O
the	O
CoreConnect	B-Architecture
bus	B-General_Concept
available	O
as	O
a	O
no-fee	O
,	O
no-royalty	O
architecture	O
to	O
tool-vendors	O
,	O
core	O
IP-companies	O
,	O
and	O
chip-development	O
companies	O
.	O
</s>
<s>
The	O
CoreConnect	B-Architecture
is	O
an	O
integral	O
part	O
of	O
IBM	O
's	O
embedded	O
offerings	O
and	O
is	O
used	O
extensively	O
in	O
their	O
PowerPC	B-General_Concept
4x0	I-General_Concept
based	O
designs	O
.	O
</s>
<s>
In	O
the	O
past	O
,	O
Xilinx	O
was	O
using	O
CoreConnect	B-Architecture
as	O
the	O
infrastructure	O
for	O
all	O
of	O
their	O
embedded	O
processor	O
designs	O
.	O
</s>
<s>
This	O
bus	B-General_Concept
:	O
</s>
